/*
 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
 *
 * Copyright (C) 2014-2015, Freescale Semiconductor
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include "fsl-ls1043a-rdb-sdk.dts"

&soc {
	bp7: buffer-pool@7 {
		compatible = "fsl,p4080-bpool", "fsl,bpool";
		fsl,bpid = <7>;
		fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
		fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
		dma-coherent;
	};

	bp8: buffer-pool@8 {
		compatible = "fsl,p4080-bpool", "fsl,bpool";
		fsl,bpid = <8>;
		fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
		fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
		dma-coherent;
	};

	bp9: buffer-pool@9 {
		compatible = "fsl,p4080-bpool", "fsl,bpool";
		fsl,bpid = <9>;
		fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
		fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
		dma-coherent;
	};

	fsl,dpaa {
		compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
		dma-coherent;

		ethernet@0 {
			compatible = "fsl,dpa-ethernet-init";
			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
			fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
			fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
		};

		ethernet@1 {
			compatible = "fsl,dpa-ethernet-init";
			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
			fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
			fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
		};

		ethernet@2 {
			compatible = "fsl,dpa-ethernet-init";
			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
			fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
			fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
		};

		ethernet@3 {
			compatible = "fsl,dpa-ethernet-init";
			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
			fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
			fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
		};

		ethernet@4 {
			compatible = "fsl,dpa-ethernet-init";
			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
			fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
			fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
		};

		ethernet@5 {
			compatible = "fsl,dpa-ethernet-init";
			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
			fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
			fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
		};

		ethernet@8 {
			compatible = "fsl,dpa-ethernet-init";
			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
			fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
			fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;

		};
		dpa-fman0-oh@2 {
			compatible = "fsl,dpa-oh";
			/* Define frame queues for the OH port*/
			/* <OH Rx error, OH Rx default> */
			fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
			fsl,fman-oh-port = <&fman0_oh2>;
		};
	};

	pcie@3400000 {
	       /delete-property/ iommu-map;
	};

	pcie@3500000 {
	       /delete-property/ iommu-map;
	};

	pcie@3600000 {
	       /delete-property/ iommu-map;
	};

	/delete-node/ iommu@9000000;
};
/ {
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* For legacy usdpaa based use-cases, update the size and
		   alignment parameters. e.g. to allocate 256 MB memory:
		   size = <0 0x10000000>;
		   alignment = <0 0x10000000>;
		*/
		usdpaa_mem: usdpaa_mem {
			compatible = "fsl,usdpaa-mem";
			alloc-ranges = <0 0 0x10000 0>;
			size = <0 0x1000>;
			alignment = <0 0x1000>;
		};
	};
};

&fman0 {
	fman0_oh2: port@83000 {
		cell-index = <1>;
		compatible = "fsl,fman-port-oh";
		reg = <0x83000 0x1000>;
	};
};