/* * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. * * Mingkai Hu * * This file is dual-licensed: you can use it either under the terms * of the GPLv2 or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This library is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "fsl-ls1046a.dtsi" / { model = "LS1046A RDB Board"; compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; aliases { serial0 = &duart0; serial1 = &duart1; serial2 = &duart2; serial3 = &duart3; }; chosen { stdout-path = "serial0:115200n8"; }; }; &duart0 { status = "okay"; }; &duart1 { status = "okay"; }; &esdhc { mmc-hs200-1_8v; sd-uhs-sdr104; sd-uhs-sdr50; sd-uhs-sdr25; sd-uhs-sdr12; }; &i2c0 { status = "okay"; ina220@40 { compatible = "ti,ina220"; reg = <0x40>; shunt-resistor = <1000>; }; temp-sensor@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; eeprom@56 { compatible = "atmel,24c512"; reg = <0x52>; }; eeprom@57 { compatible = "atmel,24c512"; reg = <0x53>; }; }; &i2c3 { status = "okay"; rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; }; }; &ifc { #address-cells = <2>; #size-cells = <1>; /* NAND Flashe and CPLD on board */ ranges = <0x0 0x0 0x0 0x7e800000 0x00010000 0x2 0x0 0x0 0x7fb00000 0x00000100>; status = "okay"; nand@0,0 { compatible = "fsl,ifc-nand"; #address-cells = <1>; #size-cells = <1>; reg = <0x0 0x0 0x10000>; }; cpld: board-control@2,0 { compatible = "fsl,ls1046ardb-cpld"; reg = <0x2 0x0 0x0000100>; }; }; &qspi { num-cs = <2>; bus-num = <0>; status = "okay"; qflash0: s25fs512s@0 { compatible = "spansion,m25p80"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; }; qflash1: s25fs512s@1 { compatible = "spansion,m25p80"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <1>; }; }; #include "fsl-ls1046-post.dtsi" &fman0 { ethernet@e4000 { phy-handle = <&rgmii_phy1>; phy-connection-type = "rgmii"; }; ethernet@e6000 { phy-handle = <&rgmii_phy2>; phy-connection-type = "rgmii"; }; ethernet@e8000 { phy-handle = <&sgmii_phy1>; phy-connection-type = "sgmii"; }; ethernet@ea000 { phy-handle = <&sgmii_phy2>; phy-connection-type = "sgmii"; }; ethernet@f0000 { /* 10GEC1 */ phy-handle = <&aqr106_phy>; phy-connection-type = "xgmii"; }; ethernet@f2000 { /* 10GEC2 */ fixed-link = <0 1 1000 0 0>; phy-connection-type = "xgmii"; }; mdio@fc000 { rgmii_phy1: ethernet-phy@1 { reg = <0x1>; }; rgmii_phy2: ethernet-phy@2 { reg = <0x2>; }; sgmii_phy1: ethernet-phy@3 { reg = <0x3>; }; sgmii_phy2: ethernet-phy@4 { reg = <0x4>; }; }; mdio@fd000 { aqr106_phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c45"; interrupts = <0 131 4>; reg = <0x0>; }; }; };