// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for NXP Layerscape-1088A family SoC. * * Copyright 2017-2020 NXP * * Harninder Rai * */ #include #include #include / { compatible = "fsl,ls1088a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { crypto = &crypto; rtc1 = &ftm_alarm0; }; cpus { #address-cells = <1>; #size-cells = <0>; /* We have 2 clusters having 4 Cortex-A53 cores each */ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; clocks = <&clockgen QORIQ_CLK_CMUX 0>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x100>; clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; cpu5: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x101>; clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; cpu6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x102>; clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; cpu7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x103>; clocks = <&clockgen QORIQ_CLK_CMUX 1>; cpu-idle-states = <&CPU_PH20>; #cooling-cells = <2>; }; CPU_PH20: cpu-ph20 { compatible = "arm,idle-state"; idle-state-name = "PH20"; arm,psci-suspend-param = <0x0>; entry-latency-us = <1000>; exit-latency-us = <1000>; min-residency-us = <3000>; }; }; gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ <0x0 0x0c0c0000 0 0x2000>, /* GICC */ <0x0 0x0c0d0000 0 0x1000>, /* GICH */ <0x0 0x0c0e0000 0 0x20000>; /* GICV */ interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <2>; #size-cells = <2>; ranges; its: gic-its@6020000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0x6020000 0 0x20000>; }; }; thermal-zones { core-cluster { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 0>; trips { core_cluster_alert: core-cluster-alert { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; core-cluster-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&core_cluster_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; soc { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 1>; trips { soc-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ }; pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "sysclk"; }; rstcr: syscon@1e60000 { compatible = "fsl,ls1088a-rstcr", "syscon"; reg = <0x0 0x1e60000 0x0 0x4>; }; reboot { compatible = "syscon-reboot"; regmap = <&rstcr>; offset = <0x0>; mask = <0x02>; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; clockgen: clocking@1300000 { compatible = "fsl,ls1088a-clockgen"; reg = <0 0x1300000 0 0xa0000>; #clock-cells = <2>; clocks = <&sysclk>; }; dcfg: dcfg@1e00000 { compatible = "fsl,ls1088a-dcfg", "syscon"; reg = <0x0 0x1e00000 0x0 0x10000>; little-endian; }; isc: syscon@1f70000 { compatible = "fsl,ls1088a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; little-endian; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1f70000 0x10000>; extirq: interrupt-controller@14 { compatible = "fsl,ls1088a-extirq"; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; reg = <0x14 4>; interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0xffffffff 0x0>; }; }; tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; interrupts = <0 23 0x4>; fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; fsl,tmu-calibration = /* Calibration data group 1 */ <0x00000000 0x00000023 0x00000001 0x0000002a 0x00000002 0x00000030 0x00000003 0x00000037 0x00000004 0x0000003d 0x00000005 0x00000044 0x00000006 0x0000004a 0x00000007 0x00000051 0x00000008 0x00000057 0x00000009 0x0000005e 0x0000000a 0x00000064 0x0000000b 0x0000006b /* Calibration data group 2 */ 0x00010000 0x00000022 0x00010001 0x0000002a 0x00010002 0x00000032 0x00010003 0x0000003a 0x00010004 0x00000042 0x00010005 0x0000004a 0x00010006 0x00000052 0x00010007 0x0000005a 0x00010008 0x00000062 0x00010009 0x0000006a /* Calibration data group 3 */ 0x00020000 0x00000021 0x00020001 0x0000002b 0x00020002 0x00000035 0x00020003 0x00000040 0x00020004 0x0000004a 0x00020005 0x00000054 0x00020006 0x0000005e /* Calibration data group 4 */ 0x00030000 0x00000010 0x00030001 0x0000001c 0x00030002 0x00000027 0x00030003 0x00000032 0x00030004 0x0000003e 0x00030005 0x00000049 0x00030006 0x00000054 0x00030007 0x00000060>; little-endian; #thermal-sensor-cells = <1>; }; dspi: spi@2100000 { compatible = "fsl,ls1088a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; interrupts = ; clock-names = "dspi"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>; spi-num-chipselects = <6>; status = "disabled"; }; duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0500 0x0 0x100>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; gpio0: gpio@2300000 { compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; little-endian; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio1: gpio@2310000 { compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; little-endian; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@2320000 { compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; little-endian; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@2330000 { compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; reg = <0x0 0x2330000 0x0 0x10000>; interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; little-endian; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; ifc: memory-controller@2240000 { compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; little-endian; #address-cells = <2>; #size-cells = <1>; status = "disabled"; }; i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; scl-gpios = <&gpio3 30 0>; status = "disabled"; }; i2c1: i2c@2010000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; }; i2c2: i2c@2020000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; }; i2c3: i2c@2030000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(8)>; status = "disabled"; }; qspi: spi@20c0000 { compatible = "fsl,ls2080a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = ; clock-names = "qspi_en", "qspi"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; }; esdhc: esdhc@2140000 { compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; interrupts = <0 28 0x4>; /* Level high type */ clock-frequency = <0>; clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; little-endian; bus-width = <4>; status = "disabled"; }; usb0: usb@3100000 { compatible = "fsl,ls1088a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; snps,host-vbus-glitches; dma-coherent; status = "disabled"; }; usb1: usb@3110000 { compatible = "fsl,ls1088a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; snps,host-vbus-glitches; dma-coherent; status = "disabled"; }; sata: sata@3200000 { compatible = "fsl,ls1088a-ahci"; reg = <0x0 0x3200000 0x0 0x10000>, <0x7 0x100520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>; dma-coherent; status = "disabled"; }; crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <8>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x8000000 0x100000>; reg = <0x00 0x8000000 0x0 0x100000>; interrupts = ; dma-coherent; sec_jr0: jr@10000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x10000 0x10000>; interrupts = ; }; sec_jr1: jr@20000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x20000 0x10000>; interrupts = ; }; sec_jr2: jr@30000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x30000 0x10000>; interrupts = ; }; sec_jr3: jr@40000 { compatible = "fsl,sec-v5.0-job-ring", "fsl,sec-v4.0-job-ring"; reg = <0x40000 0x10000>; interrupts = ; }; }; pcie1: pcie@3400000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; dma-coherent; num-viewport = <256>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&its>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ status = "disabled"; }; pcie_ep1: pcie-ep@3400000 { compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; reg = <0x00 0x03400000 0x0 0x00100000>, <0x20 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; interrupts = ; /* PME interrupt */ interrupt-names = "pme"; num-ib-windows = <24>; num-ob-windows = <256>; max-functions = /bits/ 8 <2>; big-endian; status = "disabled"; }; pcie2: pcie@3500000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; dma-coherent; num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&its>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ status = "disabled"; }; pcie_ep2: pcie-ep@3500000 { compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; reg = <0x00 0x03500000 0x0 0x00100000>, <0x28 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; interrupts = ; /* PME interrupt */ interrupt-names = "pme"; num-ib-windows = <6>; num-ob-windows = <6>; big-endian; status = "disabled"; }; pcie3: pcie@3600000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; dma-coherent; num-viewport = <6>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&its>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ status = "disabled"; }; pcie_ep3: pcie-ep@3600000 { compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; reg = <0x00 0x03600000 0x0 0x00100000>, <0x30 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; interrupts = ; /* PME interrupt */ interrupt-names = "pme"; num-ib-windows = <6>; num-ob-windows = <6>; big-endian; status = "disabled"; }; smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; #iommu-cells = <1>; stream-match-mask = <0x7C00>; #global-interrupts = <12>; // global secure fault interrupts = , // combined secure , // global non-secure fault , // combined non-secure , // performance counter interrupts 0-7 , , , , , , , , // per context interrupt, 64 interrupts , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ; }; console@8340020 { compatible = "fsl,dpaa2-console"; reg = <0x00000000 0x08340020 0 0x2>; }; ptp-timer@8b95000 { compatible = "fsl,dpaa2-ptp"; reg = <0x0 0x8b95000 0x0 0x100>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; little-endian; fsl,extts-fifo; }; emdio1: mdio@8b96000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8b96000 0x0 0x1000>; little-endian; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; emdio2: mdio@8b97000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8b97000 0x0 0x1000>; little-endian; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; pcs_mdio1: mdio@8c07000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8c07000 0x0 0x1000>; little-endian; #address-cells = <1>; #size-cells = <0>; status = "disabled"; pcs1: ethernet-phy@0 { reg = <0>; }; }; pcs_mdio2: mdio@8c0b000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8c0b000 0x0 0x1000>; little-endian; #address-cells = <1>; #size-cells = <0>; status = "disabled"; pcs2: ethernet-phy@0 { reg = <0>; }; }; pcs_mdio3: mdio@8c0f000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8c0f000 0x0 0x1000>; little-endian; #address-cells = <1>; #size-cells = <0>; status = "disabled"; pcs3_0: ethernet-phy@0 { reg = <0>; }; pcs3_1: ethernet-phy@1 { reg = <1>; }; pcs3_2: ethernet-phy@2 { reg = <2>; }; pcs3_3: ethernet-phy@3 { reg = <3>; }; }; pcs_mdio7: mdio@8c1f000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8c1f000 0x0 0x1000>; little-endian; #address-cells = <1>; #size-cells = <0>; status = "disabled"; pcs7_0: ethernet-phy@0 { reg = <0>; }; pcs7_1: ethernet-phy@1 { reg = <1>; }; pcs7_2: ethernet-phy@2 { reg = <2>; }; pcs7_3: ethernet-phy@3 { reg = <3>; }; }; cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: wdt@c010000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core2_watchdog: wdt@c020000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc020000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core3_watchdog: wdt@c030000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc030000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core0_watchdog: wdt@c100000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core1_watchdog: wdt@c110000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core2_watchdog: wdt@c120000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc120000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core3_watchdog: wdt@c130000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc130000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; clock-names = "wdog_clk", "apb_pclk"; }; fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ msi-parent = <&its>; iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ dma-coherent; #address-cells = <3>; #size-cells = <1>; /* * Region type 0x0 - MC portals * Region type 0x1 - QBMAN portals */ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; dpmacs { #address-cells = <1>; #size-cells = <0>; dpmac1: ethernet@1 { compatible = "fsl,qoriq-mc-dpmac"; reg = <1>; }; dpmac2: ethernet@2 { compatible = "fsl,qoriq-mc-dpmac"; reg = <2>; }; dpmac3: ethernet@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <3>; }; dpmac4: ethernet@4 { compatible = "fsl,qoriq-mc-dpmac"; reg = <4>; }; dpmac5: ethernet@5 { compatible = "fsl,qoriq-mc-dpmac"; reg = <5>; }; dpmac6: ethernet@6 { compatible = "fsl,qoriq-mc-dpmac"; reg = <6>; }; dpmac7: ethernet@7 { compatible = "fsl,qoriq-mc-dpmac"; reg = <7>; }; dpmac8: ethernet@8 { compatible = "fsl,qoriq-mc-dpmac"; reg = <8>; }; dpmac9: ethernet@9 { compatible = "fsl,qoriq-mc-dpmac"; reg = <9>; }; dpmac10: ethernet@a { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xa>; }; }; }; rcpm: power-controller@1e34040 { compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; reg = <0x0 0x1e34040 0x0 0x18>; #fsl,rcpm-wakeup-cells = <6>; little-endian; }; ftm_alarm0: timer@2800000 { compatible = "fsl,ls1088a-ftm-alarm"; reg = <0x0 0x2800000 0x0 0x10000>; fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; interrupts = ; }; }; firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; }; }; };