// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/firmware/imx/rsrc.h>

conn_subsys: bus@5b000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;

	conn_axi_clk: clock-conn-axi {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <333333333>;
		clock-output-names = "conn_axi_clk";
	};

	conn_ahb_clk: clock-conn-ahb {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <166666666>;
		clock-output-names = "conn_ahb_clk";
	};

	conn_ipg_clk: clock-conn-ipg {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <83333333>;
		clock-output-names = "conn_ipg_clk";
	};

	conn_bch_clk: clock-conn-bch {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <400000000>;
		clock-output-names = "conn_bch_clk";
	};

	usbotg1: usb@5b0d0000 {
		compatible = "fsl,imx8qm-usb", "fsl,imx7ulp-usb",
			"fsl,imx27-usb";
		reg = <0x5b0d0000 0x200>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
		fsl,usbphy = <&usbphy1>;
		fsl,usbmisc = <&usbmisc1 0>;
		clocks = <&usb2_lpcg 0>;
		ahb-burst-config = <0x0>;
		tx-burst-size-dword = <0x10>;
		rx-burst-size-dword = <0x10>;
		power-domains = <&pd IMX_SC_R_USB_0>;
		status = "disabled";
	};

	usbmisc1: usbmisc@5b0d0200 {
		#index-cells = <1>;
		compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
		reg = <0x5b0d0200 0x200>;
	};

	usbphy1: usbphy@0x5b100000 {
		compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy",
			"fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
		reg = <0x5b100000 0x1000>;
		clocks = <&usb2_lpcg 1>;
		power-domains = <&pd IMX_SC_R_USB_0_PHY>;
		status = "disabled";
	};

	usdhc1: mmc@5b010000 {
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x5b010000 0x10000>;
		clocks = <&sdhc0_lpcg 1>,
			 <&sdhc0_lpcg 0>,
			 <&sdhc0_lpcg 2>;
		clock-names = "ipg", "per", "ahb";
		assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <400000000>;
		power-domains = <&pd IMX_SC_R_SDHC_0>;
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		status = "disabled";
	};

	usdhc2: mmc@5b020000 {
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x5b020000 0x10000>;
		clocks = <&sdhc1_lpcg 1>,
			 <&sdhc1_lpcg 0>,
			 <&sdhc1_lpcg 2>;
		clock-names = "ipg", "per", "ahb";
		assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <200000000>;
		power-domains = <&pd IMX_SC_R_SDHC_1>;
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		status = "disabled";
	};

	usdhc3: mmc@5b030000 {
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x5b030000 0x10000>;
		clocks = <&sdhc2_lpcg 1>,
			 <&sdhc2_lpcg 0>,
			 <&sdhc2_lpcg 2>;
		clock-names = "ipg", "per", "ahb";
		assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <200000000>;
		power-domains = <&pd IMX_SC_R_SDHC_2>;
		fsl,tuning-start-tap = <20>;
		fsl,tuning-step= <2>;
		status = "disabled";
	};

	fec1: ethernet@5b040000 {
		reg = <0x5b040000 0x10000>;
		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&enet0_lpcg 4>,
			 <&enet0_lpcg 2>,
			 <&enet0_lpcg 3>,
			 <&enet0_lpcg 0>,
			 <&enet0_lpcg 1>;
		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
		assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
				  <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
		assigned-clock-rates = <250000000>, <125000000>;
		fsl,num-tx-queues=<3>;
		fsl,num-rx-queues=<3>;
		power-domains = <&pd IMX_SC_R_ENET_0>;
		status = "disabled";
	};

	fec2: ethernet@5b050000 {
		reg = <0x5b050000 0x10000>;
		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&enet1_lpcg 4>,
			 <&enet1_lpcg 2>,
			 <&enet1_lpcg 3>,
			 <&enet1_lpcg 0>,
			 <&enet1_lpcg 1>;
		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
				  <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
		assigned-clock-rates = <250000000>, <125000000>;
		fsl,num-tx-queues=<3>;
		fsl,num-rx-queues=<3>;
		power-domains = <&pd IMX_SC_R_ENET_1>;
		status = "disabled";
	};

	mlb: mlb@5b060000 {
		compatible = "fsl,imx8qxp-mlb150";
		reg = <0x5B060000 0x10000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mlb_lpcg 0>,
			 <&mlb_lpcg 1>,
			 <&mlb_lpcg 2>;
		clock-names = "mlb", "hclk", "ipg";
		power-domains = <&pd IMX_SC_R_MLB_0>;
		status = "disabled";
	};

	usb3phynop1: usb3-phy {
		compatible = "usb-nop-xceiv";
		clocks = <&usb3_lpcg 4>;
		clock-names = "main_clk";
		power-domains = <&pd IMX_SC_R_USB_2_PHY>;
		status = "disabled";
	};

	usbotg3: usb3@5b110000 {
		compatible = "Cadence,usb3";
		reg = <0x5B110000 0x10000>,
			<0x5B130000 0x10000>,
			<0x5B140000 0x10000>,
			<0x5B160000 0x40000>,
			<0x5B120000 0x10000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&usb3_lpcg 1>,
			 <&usb3_lpcg 0>,
			 <&usb3_lpcg 5>,
			 <&usb3_lpcg 2>,
			 <&usb3_lpcg 3>;
		clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
			"usb3_ipg_clk", "usb3_core_pclk";
		assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
				  <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
				  <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
		assigned-clock-rates = <125000000>, <12000000>, <250000000>;
		power-domains = <&pd IMX_SC_R_USB_2>;
		cdns3,usbphy = <&usb3phynop1>;
		status = "disabled";
	};

	/* LPCG clocks */
	sdhc0_lpcg: clock-controller@5b200000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b200000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
			 <&conn_ipg_clk>, <&conn_axi_clk>;
		bit-offset = <0 16 20>;
		clock-output-names = "sdhc0_lpcg_per_clk",
				     "sdhc0_lpcg_ipg_clk",
				     "sdhc0_lpcg_ahb_clk";
		power-domains = <&pd IMX_SC_R_SDHC_0>;
	};

	sdhc1_lpcg: clock-controller@5b210000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b210000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
			 <&conn_ipg_clk>, <&conn_axi_clk>;
		bit-offset = <0 16 20>;
		clock-output-names = "sdhc1_lpcg_per_clk",
				     "sdhc1_lpcg_ipg_clk",
				     "sdhc1_lpcg_ahb_clk";
		power-domains = <&pd IMX_SC_R_SDHC_1>;
	};

	sdhc2_lpcg: clock-controller@5b220000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b220000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
			 <&conn_ipg_clk>, <&conn_axi_clk>;
		bit-offset = <0 16 20>;
		clock-output-names = "sdhc2_lpcg_per_clk",
				     "sdhc2_lpcg_ipg_clk",
				     "sdhc2_lpcg_ahb_clk";
		power-domains = <&pd IMX_SC_R_SDHC_2>;
	};

	enet0_lpcg: clock-controller@5b230000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b230000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
			 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
			 <&conn_axi_clk>,
			 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
			 <&conn_ipg_clk>,
			 <&conn_ipg_clk>;
		bit-offset = <0 4 8 12 16 20>;
		clock-output-names = "enet0_lpcg_timer_clk",
				     "enet0_lpcg_txc_sampling_clk",
				     "enet0_lpcg_ahb_clk",
				     "enet0_lpcg_rgmii_txc_clk",
				     "enet0_lpcg_ipg_clk",
				     "enet0_lpcg_ipg_s_clk";
		power-domains = <&pd IMX_SC_R_ENET_0>;
	};

	enet1_lpcg: clock-controller@5b240000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b240000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
			 <&conn_axi_clk>,
			 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
			 <&conn_ipg_clk>,
			 <&conn_ipg_clk>;
		bit-offset = <0 4 8 12 16 20>;
		clock-output-names = "enet1_lpcg_timer_clk",
				     "enet1_lpcg_txc_sampling_clk",
				     "enet1_lpcg_ahb_clk",
				     "enet1_lpcg_rgmii_txc_clk",
				     "enet1_lpcg_ipg_clk",
				     "enet1_lpcg_ipg_s_clk";
		power-domains = <&pd IMX_SC_R_ENET_1>;
	};

	mlb_lpcg: clock-controller@5b260000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b260000 0x10000>;
		#clock-cells = <1>;
		clocks = <&conn_axi_clk>,
			 <&conn_axi_clk>,
			 <&conn_ipg_clk>;
		bit-offset = <0 20 16>;
		clock-output-names = "mlb_lpcg_clk",
				     "mlb_lpcg_hclk",
				     "mlb_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_MLB_0>;
	};

	usb2_lpcg: clock-controller@5b270000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b270000 0x10000>;
		#clock-cells = <1>;
		clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
		bit-offset = <24 28>;
		clock-output-names = "usboh3_ahb_clk",
				     "usboh3_phy_ipg_clk";
		power-domains = <&pd IMX_SC_R_USB_0_PHY>;
	};

	usb3_lpcg: clock-controller@5b280000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b280000 0x10000>;
		#clock-cells = <1>;
		bit-offset = <0 4 16 20 24 28>;
		clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
			 <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
			 <&conn_ipg_clk>,
			 <&conn_ipg_clk>,
			 <&conn_ipg_clk>,
			 <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
		clock-output-names = "usb3_app_clk",
				     "usb3_lpm_clk",
				     "usb3_ipg_clk",
				     "usb3_core_pclk",
				     "usb3_phy_clk",
				     "usb3_aclk";
		power-domains = <&pd IMX_SC_R_USB_2_PHY>;
	};

	rawnand_0_lpcg: clock-controller@5b290000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b290000 0x4>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>,
			 <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>,
			 <&conn_axi_clk>,
			 <&conn_axi_clk>;
		bit-offset = <0 4 16 20>;
		clock-output-names = "bch_clk",
				     "gpmi_clk",
				     "gpmi_apb_clk",
				     "bch_apb_clk";
		power-domains = <&pd IMX_SC_R_NAND>;
	};

	rawnand_4_lpcg: clock-controller@5b290004 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b290004 0x10000>;
		#clock-cells = <1>;
		clocks = <&conn_axi_clk>;
		bit-offset = <16>;
		clock-output-names = "apbhdma_hclk";
		power-domains = <&pd IMX_SC_R_NAND>;
	};

	dma_apbh: dma-apbh@5b810000 {
		compatible = "fsl,imx28-dma-apbh";
		reg = <0x5b810000 0x2000>;
		interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
		#dma-cells = <1>;
		dma-channels = <4>;
		clocks = <&rawnand_4_lpcg 0>;
		clock-names = "apbhdma_hclk";
		power-domains = <&pd IMX_SC_R_NAND>;
	};

	gpmi: gpmi-nand@5b812000{
		compatible = "fsl,imx8qxp-gpmi-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>;
		reg-names = "gpmi-nand", "bch";
		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "bch";
		clocks = <&rawnand_0_lpcg 1>,
			 <&rawnand_0_lpcg 2>,
			 <&rawnand_0_lpcg 0>,
			 <&rawnand_0_lpcg 3>;
		clock-names = "gpmi_clk", "gpmi_apb_clk",
			      "bch_clk", "bch_apb_clk";
		dmas = <&dma_apbh 0>;
		dma-names = "rx-tx";
		power-domains = <&pd IMX_SC_R_NAND>;
		assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>;
		assigned-clock-rates = <50000000>;
		status = "disabled";
	};
};