// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

vpu: vpu@2c000000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
	reg = <0 0x2c000000 0 0x1000000>;
	power-domains = <&pd IMX_SC_R_VPU>;
	status = "disabled";

	vpu_lpcg: clock-controller@2c000000 {
		compatible = "fsl,imx8qxp-lpcg-vpu";
		reg = <0x2c000000 0x2000000>;
		#clock-cells = <1>;
		status = "disabled";
	};

	mu_m0: mailbox@2d000000 {
		compatible = "fsl,imx6sx-mu";
		reg = <0x2d000000 0x20000>;
		interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <2>;
		power-domains = <&pd IMX_SC_R_VPU_MU_0>;
		status = "okay";
	};

	mu1_m0: mailbox@2d020000 {
		compatible = "fsl,imx6sx-mu";
		reg = <0x2d020000 0x20000>;
		interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <2>;
		power-domains = <&pd IMX_SC_R_VPU_MU_1>;
		status = "okay";
	};

	mu2_m0: mailbox@2d040000 {
		compatible = "fsl,imx8-mu2-vpu-m0", "fsl,imx6sx-mu";
		reg = <0x2d040000 0x20000>;
		interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <2>;
		power-domains = <&pd IMX_SC_R_VPU_MU_2>;
		status = "disabled";
	};

	vpu_core0: vpu-core@2d080000 {
		reg = <0x2d080000 0x10000>;
		compatible = "nxp,imx8q-vpu-decoder";
		power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
		mbox-names = "tx0", "tx1", "rx";
		mboxes = <&mu_m0 0 0>,
			<&mu_m0 0 1>,
			<&mu_m0 1 0>;
		status = "disabled";
	};
	vpu_core1: vpu-core@2d090000 {
		reg = <0x2d090000 0x10000>;
		compatible = "nxp,imx8q-vpu-encoder";
		power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
		mbox-names = "tx0", "tx1", "rx";
		mboxes = <&mu1_m0 0 0>,
			<&mu1_m0 0 1>,
			<&mu1_m0 1 0>;
		status = "disabled";
	};
	vpu_core2: vpu-core@2d0a0000 {
		reg = <0x2d0a0000 0x10000>;
		compatible = "nxp,imx8q-vpu-encoder";
		power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
		mbox-names = "tx0", "tx1", "rx";
		mboxes = <&mu2_m0 0 0>,
			<&mu2_m0 0 1>,
			<&mu2_m0 1 0>;
		status = "disabled";
	};
};