// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 NXP
 */

/dts-v1/;

#include "imx8mm-evk.dts"

/ {
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		m4_reserved: m4@0x80000000 {
			no-map;
			reg = <0 0x80000000 0 0x1000000>;
		};

		vdev0vring0: vdev0vring0@b8000000 {
			reg = <0 0xb8000000 0 0x8000>;
			no-map;
		};

		vdev0vring1: vdev0vring1@b8008000 {
			reg = <0 0xb8008000 0 0x8000>;
			no-map;
		};

		rsc_table: rsc_table@b80ff000 {
			reg = <0 0xb80ff000 0 0x1000>;
			no-map;
		};

		vdevbuffer: vdevbuffer@b8400000 {
			compatible = "shared-dma-pool";
			reg = <0 0xb8400000 0 0x100000>;
			no-map;
		};

	};

	bt_sco_codec: bt_sco_codec {
		status = "disabled";
	};

	sound-bt-sco {
		status = "disabled";
	};

	sound-wm8524 {
		status = "disabled";
	};

	sound-micfil {
		status = "disabled";
	};

	wm8524: audio-codec {
		status = "disabled";
	};

	rpmsg_audio: rpmsg_audio {
		compatible = "fsl,imx8mm-rpmsg-audio";
		model = "wm8524-audio";
		fsl,platform = "rpmsg-audio-channel";
		fsl,enable-lpa;
		fsl,rpmsg-out;
		assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
		assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
		assigned-clock-rates = <24576000>;
		clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
			 <&clk IMX8MM_CLK_SAI3_ROOT>,
			 <&clk IMX8MM_CLK_SDMA3_ROOT>,
			 <&clk IMX8MM_AUDIO_PLL1_OUT>,
			 <&clk IMX8MM_AUDIO_PLL2_OUT>;
		clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k";
		status = "okay";
	};

	rpmsg_micfil: rpmsg_micfil {
		compatible = "fsl,imx8mm-rpmsg-audio";
		model = "micfil-audio";
		fsl,platform = "rpmsg-micfil-channel";
		fsl,enable-lpa;
		fsl,rpmsg-in;
		assigned-clocks = <&clk IMX8MM_CLK_PDM>;
		assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
		assigned-clock-rates = <196608000>;
		clocks = <&clk IMX8MM_CLK_PDM_IPG>,
			 <&clk IMX8MM_CLK_PDM_ROOT>,
			 <&clk IMX8MM_CLK_SDMA3_ROOT>,
			 <&clk IMX8MM_AUDIO_PLL1_OUT>,
			 <&clk IMX8MM_AUDIO_PLL2_OUT>;
		clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k";
		status = "okay";
	};

	imx8mm-cm4 {
		compatible = "fsl,imx8mm-cm4";
		rsc-da = <0xb8000000>;
		clocks = <&clk IMX8MM_CLK_M4_DIV>;
		mbox-names = "tx", "rx", "rxdb";
		mboxes = <&mu 0 1
			  &mu 1 1
			  &mu 3 1>;
		memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>;
		syscon = <&src>;
	};
};

&clk {
	init-on-array = <IMX8MM_CLK_UART4_ROOT
	IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE
	IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB
	IMX8MM_CLK_USB_BUS
	IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB
	IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV
	IMX8MM_ARM_PLL_OUT IMX8MM_CLK_DISP_AXI
	IMX8MM_CLK_DISP_APB
	>;
};

/*
 * ATTENTION: M4 may use IPs like below
 * ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1
 */

&i2c3 {
	status = "disabled";
};

&uart4 {
	status = "disabled";
};

&sdma3 {
	status = "disabled";
};

&micfil {
	status = "disabled";
};

&sai6 {
	status = "disabled";
};

&sai3 {
	status = "disabled";
};

&sai1 {
	status = "disabled";
};

&sai2 {
	status = "disabled";
};

&flexspi {
	status = "disabled";
};

&uart3 {
	status = "disabled";
};