/*
 * Copyright 2020 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "imx8mn.dtsi"

/ {
	model = "NXP i.MX8MNano Audio board 2.0";
	compatible = "fsl,imx8mn-ab2", "fsl,imx8mn";

	chosen {
		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
		stdout-path = &uart2;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_led>;

		status {
			label = "status";
			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		panel {
			label = "panel";
			gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};
	};

	modem_reset: modem-reset {
		compatible = "gpio-reset";
		reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
		reset-delay-us = <2000>;
		reset-post-delay-ms = <40>;
		#reset-cells = <0>;
	};

	usdhc1_pwrseq: usdhc1_pwrseq {
		compatible = "mmc-pwrseq-simple";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <12000>;
		enable-active-high;
	};

	reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
		compatible = "regulator-fixed";
		regulator-name = "ANA_12V0";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
		vin-supply = <&buck5_reg>;
		enable-active-high;
	};

	reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "VDD_5V0";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
		vin-supply = <&buck5_reg>;
		enable-active-high;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_adc_dvdd_3v3: reg-adc-dvdd-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "ADC_DVDD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&reg_ab2_ana_pwr>;
	};

	reg_adc_avdd_5v0: reg-adc-avdd-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "ADC_AVDD_5V0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&reg_ab2_ana_pwr>;
	};

	reg_dac_dvdd_3v3: reg-dac-dvdd-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "DAC_DVDD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&reg_ab2_ana_pwr>;
	};

	reg_dac_avdd_5v0: reg-dac-avdd-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "DAC_AVDD_5V0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&reg_ab2_ana_pwr>;
	};

	reg_cph_3v3: reg-cph-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "CPH_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&reg_ab2_vdd_pwr_5v0>;
	};

	reg_cph_1v8: reg-cph-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "CPH_1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&reg_cph_3v3>;
	};

	sound-ak5552 {
		compatible = "fsl,imx-audio-ak5552";
		model = "ak5552-audio";
		audio-cpu = <&sai3>;
		audio-codec = <&ak5552>;
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif1>;
		spdif-out;
		spdif-in;
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&clk {
	assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>;
	assigned-clock-rates = <393216000>, <361267200>;
};

&easrc {
	fsl,asrc-rate  = <48000>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1>;

	imx8mn-ab2 {
		pinctrl_hog_1: hoggrp-1 {
			fsl,pins = <
				MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x16
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
				MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
				MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
				MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
				MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
				MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
				MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
				MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
				MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
				MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
				MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
				MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
				MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
				MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
				MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19
			>;
		};

		pinctrl_flexspi0: flexspi0grp {
			fsl,pins = <
				MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
				MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84

				MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
				MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
				MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
				MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
			>;
		};

		pinctrl_gpio_led: gpioledgrp {
			fsl,pins = <
				MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
			>;
		};

		pinctrl_ecspi2: ecspi2grp {
			fsl,pins = <
				MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
				MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
				MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
			>;
		};

		pinctrl_ecspi2_cs: ecspi2cs {
			fsl,pins = <
				MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x40000
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
				MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
				MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
				MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
			>;
		};

		pinctrl_i2c4: i2c4grp {
			fsl,pins = <
				MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL			0x400001c3
				MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA			0x400001c3
			>;
		};

		pinctrl_i2c1_gpio: i2c1grp-gpio {
			fsl,pins = <
				MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14		0x1c3
				MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15		0x1c3
			>;
		};

		pinctrl_i2c2_gpio: i2c2grp-gpio {
			fsl,pins = <
				MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16		0x1c3
				MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17		0x1c3
			>;
		};

		pinctrl_i2c3_gpio: i2c3grp-gpio {
			fsl,pins = <
				MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18		0x1c3
				MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19		0x1c3
			>;
		};

		pinctrl_i2c4_gpio: i2c4grp-gpio {
			fsl,pins = <
				MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20		0x1c3
				MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21		0x1c3
			>;
		};

		pinctrl_pmic: pmicirq {
			fsl,pins = <
				MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
			>;
		};

		pinctrl_ab2_ana_pwr: ab2anapwrgrp {
			fsl,pins = <
				MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41
			>;
		};

		pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
			fsl,pins = <
				MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x41
			>;
		};

		pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
			fsl,pins = <
				MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
			>;
		};

		pinctrl_sai3: sai3grp {
			fsl,pins = <
				MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK	0xd6
				MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK	0xd6
				MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC	0xd6
				MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
			>;
		};

		pinctrl_spdif1: spdif1grp {
			fsl,pins = <
				MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
				MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
				MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
				MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
				MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
				MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
				MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x140
				MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x140
				MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x140
				MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x140
			>;
		};

		pinctrl_usdhc1_gpio: usdhc1grpgpio {
			fsl,pins = <
				MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
				MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
				MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
				MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
				MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
				MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
				MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
				MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
				MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
				MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
				MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
				MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
				MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
				MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
				MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
				MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2grpgpio {
			fsl,pins = <
				MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
				MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
				MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
				MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
				MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
				MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
				MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
				MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
				MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
				MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
				MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
				MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
				MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
				MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
				MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
				MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
				MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
				MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
				MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
				MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
				MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
				MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
				MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
				MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
				MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
				MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
				MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
				MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
				MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
			fsl,pins = <
				MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
				MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
				MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
				MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
				MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
				MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
				MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
				MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
				MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
				MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
				MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
			fsl,pins = <
				MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
				MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
				MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
				MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
				MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
				MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
				MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
				MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
				MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
				MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
				MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
			>;
		};

		pinctrl_wdog: wdoggrp {
			fsl,pins = <
				MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
			>;
		};

		pinctrl_wlan: wlangrp {
			fsl,pins = <
				MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141
				MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9		0x111
			>;
		};

		pinctrl_mipi_dsi_en: mipi_dsi_en {
			fsl,pins = <
				MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x16
			>;
		};

		pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp {
			fsl,pins = <
				MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
			>;
		};
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: mt25qu256aba@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";

	spidev0: spi@0 {
		reg = <0>;
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <500000>;
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pmic: pca9450@25 {
		reg = <0x25>;
		compatible = "nxp,pca9450";
		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
		pinctrl-0 = <&pinctrl_pmic>;
		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;

		regulators {
			#address-cells = <1>;
			#size-cells = <0>;

			pca9450,pmic-buck2-uses-i2c-dvs;
			/* Run/Standby voltage */
			pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;

			buck1_reg: regulator@0 {
				reg = <0>;
				regulator-compatible = "buck1";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck2_reg: regulator@1 {
				reg = <1>;
				regulator-compatible = "buck2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck3_reg: regulator@2 {
				reg = <2>;
				regulator-compatible = "buck3";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4_reg: regulator@3 {
				reg = <3>;
				regulator-compatible = "buck4";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: regulator@4 {
				reg = <4>;
				regulator-compatible = "buck5";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: regulator@5 {
				reg = <5>;
				regulator-compatible = "buck6";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: regulator@6 {
				reg = <6>;
				regulator-compatible = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: regulator@7 {
				reg = <7>;
				regulator-compatible = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: regulator@8 {
				reg = <8>;
				regulator-compatible = "ldo3";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: regulator@9 {
				reg = <9>;
				regulator-compatible = "ldo4";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5_reg: regulator@10 {
				reg = <10>;
				regulator-compatible = "ldo5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
	status = "okay";

	adv_bridge: adv7535@3d {
		compatible = "adi,adv7533";
		reg = <0x3d>;
		adi,addr-cec = <0x3b>;
		adi,dsi-lanes = <4>;
		status = "okay";

		port {
			adv7535_from_dsim: endpoint {
				remote-endpoint = <&dsim_to_adv7535>;
			};
		};
	};

	pca6408_2: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&buck4_reg>;
	};

	pca6416_2: gpio@21 {
		compatible = "ti,tca6408";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&buck5_reg>;
	};
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&buck5_reg>;
	};

	ak5552: ak5552@13 {
		compatible = "asahi-kasei,ak5552";
		reg = <0x13>;
		reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>;
		AVDD-supply = <&reg_adc_avdd_5v0>;
		DVDD-supply = <&reg_adc_dvdd_3v3>;
	};
};

&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
	status = "disabled";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
	phy-reset-post-delay = <150>;
	phy-reset-duration = <10>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			eee-broken-1000t;
		};
	};
};

&lcdif {
	status = "okay";
};

&mipi_dsi {
	status = "okay";

	port@1 {
		dsim_to_adv7535: endpoint {
			remote-endpoint = <&adv7535_from_dsim>;
			attach-bridge;
		};
	};
};

&uart1 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MN_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
	fsl,uart-has-rtscts;
	resets = <&modem_reset>;
	status = "okay";
};

&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <49152000>;
	clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>,
		<&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>,
		<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>,
		<&clk IMX8MN_AUDIO_PLL2_OUT>;
	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
	status = "okay";
};

&spdif1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif1>;
	assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>,
		<&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>,
		<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>,
		<&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>,
		<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>,
		<&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>;
	clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
		"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
	status = "okay";
};

&uart2 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MN_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usdhc1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
	bus-width = <4>;
	pm-ignore-notify;
	keep-power-in-suspend;
	non-removable;
	cap-power-off-card;
	/delete-property/ vmmc-supply;
	mmc-pwrseq = <&usdhc1_pwrseq>;
	status = "okay";

	brcmf: bcrmf@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
		interrupt-parent = <&gpio2>;
		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "host-wake";
	};
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&gpu {
	status = "okay";
};