// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

/delete-node/ &acm;
/delete-node/ &sai4;
/delete-node/ &sai5;
/delete-node/ &sai4_lpcg;
/delete-node/ &sai5_lpcg;

/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */
&edma0{
	reg =   <0x59200000 0x10000>, /* asrc0 */
		<0x59210000 0x10000>,
		<0x59220000 0x10000>,
		<0x59230000 0x10000>,
		<0x59240000 0x10000>,
		<0x59250000 0x10000>,
		<0x59260000 0x10000>, /* esai0 rx */
		<0x59270000 0x10000>, /* esai0 tx */
		<0x59280000 0x10000>, /* spdif0 rx */
		<0x59290000 0x10000>, /* spdif0 tx */
		<0x592A0000 0x10000>, /* spdif1 rx */
		<0x592B0000 0x10000>, /* spdif1 tx */
		<0x592c0000 0x10000>, /* sai0 rx */
		<0x592d0000 0x10000>, /* sai0 tx */
		<0x592e0000 0x10000>, /* sai1 rx */
		<0x592f0000 0x10000>, /* sai1 tx */
		<0x59300000 0x10000>, /* sai2 rx */
		<0x59310000 0x10000>, /* sai3 rx */
		<0x59320000 0x10000>, /* sai4 rx */
		<0x59330000 0x10000>; /* sai5 tx */
	dma-channels = <20>;
	interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */
			<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
			<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
			<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */
			<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
			<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
			<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
			<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
			<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
			<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
	interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */
			"edma2-chan2-rx", "edma2-chan3-tx",
			"edma2-chan4-tx", "edma2-chan5-tx",
			"edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */
			"edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */
			"edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */
			"edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */
			"edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */
			"edma2-chan16-rx", "edma2-chan17-tx", /* sai2, dai3 */
			"edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */
	power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
			<&pd IMX_SC_R_DMA_2_CH1>,
			<&pd IMX_SC_R_DMA_2_CH2>,
			<&pd IMX_SC_R_DMA_2_CH3>,
			<&pd IMX_SC_R_DMA_2_CH4>,
			<&pd IMX_SC_R_DMA_2_CH5>,
			<&pd IMX_SC_R_DMA_2_CH6>,
			<&pd IMX_SC_R_DMA_2_CH7>,
			<&pd IMX_SC_R_DMA_2_CH8>,
			<&pd IMX_SC_R_DMA_2_CH9>,
			<&pd IMX_SC_R_DMA_2_CH10>,
			<&pd IMX_SC_R_DMA_2_CH11>,
			<&pd IMX_SC_R_DMA_2_CH12>,
			<&pd IMX_SC_R_DMA_2_CH13>,
			<&pd IMX_SC_R_DMA_2_CH14>,
			<&pd IMX_SC_R_DMA_2_CH15>,
			<&pd IMX_SC_R_DMA_2_CH16>,
			<&pd IMX_SC_R_DMA_2_CH17>,
			<&pd IMX_SC_R_DMA_2_CH18>,
			<&pd IMX_SC_R_DMA_2_CH19>;
	power-domain-names = "edma2-chan0", "edma2-chan1",
			     "edma2-chan2", "edma2-chan3",
			     "edma2-chan4", "edma2-chan5",
			     "edma2-chan6", "edma2-chan7",
			     "edma2-chan8", "edma2-chan9",
			     "edma2-chan10", "edma2-chan11",
			     "edma2-chan12", "edma2-chan13",
			     "edma2-chan14", "edma2-chan15",
			     "edma2-chan16", "edma2-chan17",
			     "edma2-chan18", "edma2-chan19";
};

/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */
&edma1{
	reg =   <0x59A00000 0x10000>, /* asrc1 */
		<0x59A10000 0x10000>,
		<0x59A20000 0x10000>,
		<0x59A30000 0x10000>,
		<0x59A40000 0x10000>,
		<0x59A50000 0x10000>,
		<0x59A80000 0x10000>, /* sai6 rx */
		<0x59A90000 0x10000>, /* sai6 tx */
		<0x59AA0000 0x10000>; /* sai7 tx */
	dma-channels = <9>;
	interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */
			<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */
			<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */
	interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */
			"edma3-chan2-rx", "edma3-chan3-tx",
			"edma3-chan4-tx", "edma3-chan5-tx",
			"edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */
			"edma3-chan10-tx";                 /* sai7 */
	power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
			<&pd IMX_SC_R_DMA_3_CH1>,
			<&pd IMX_SC_R_DMA_3_CH2>,
			<&pd IMX_SC_R_DMA_3_CH3>,
			<&pd IMX_SC_R_DMA_3_CH4>,
			<&pd IMX_SC_R_DMA_3_CH5>,
			<&pd IMX_SC_R_DMA_3_CH8>,
			<&pd IMX_SC_R_DMA_3_CH9>,
			<&pd IMX_SC_R_DMA_3_CH10>;
	power-domain-names = "edma3-chan0", "edma3-chan1",
			     "edma3-chan2", "edma3-chan3",
			     "edma3-chan4", "edma3-chan5",
			     "edma3-chan8", "edma3-chan9",
			     "edma3-chan10";
};

&asrc0 {
	clocks = <&asrc0_lpcg 0>,
		<&asrc0_lpcg 1>,
		<&aud_pll_div0_lpcg 0>,
		<&aud_pll_div1_lpcg 0>,
		<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
		<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>;
	power-domains = <&pd IMX_SC_R_ASRC_0>;
};

&esai0 {
	power-domains = <&pd IMX_SC_R_ESAI_0>;
};

&spdif0 {
	power-domains = <&pd IMX_SC_R_SPDIF_0>;
};

&spdif1 {
	power-domains = <&pd IMX_SC_R_SPDIF_1>;
};

&sai0 {
	power-domains = <&pd IMX_SC_R_SAI_0>;
};

&sai1 {
	power-domains = <&pd IMX_SC_R_SAI_1>;
};

&sai2 {
	power-domains = <&pd IMX_SC_R_SAI_2>;
};

&sai3 {
	power-domains = <&pd IMX_SC_R_SAI_3>;
};

&asrc1 {
	clocks = <&asrc1_lpcg 0>,
		<&asrc1_lpcg 1>,
		<&aud_pll_div0_lpcg 0>,
		<&aud_pll_div1_lpcg 0>,
		<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
		<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>,
		<&clk_dummy>;
	power-domains = <&pd IMX_SC_R_ASRC_1>;
};

&amix {
	dais = <&sai6>, <&sai7>;
};

&asrc0_lpcg {
	clocks = <&audio_ipg_clk>,
		 <&audio_ipg_clk>;
	bit-offset = <0 8>;
	clock-output-names = "asrc0_lpcg_ipg_clk",
			     "asrc0_lpcg_mem_clk";
};

&esai0_lpcg {
	bit-offset = <16 0>;
	clock-output-names = "esai0_lpcg_extal_clk",
			     "esai0_lpcg_ipg_clk";
};

&spdif0_lpcg {
	bit-offset = <20 16>;
	clock-output-names = "spdif0_lpcg_tx_clk",
			     "spdif0_lpcg_gclkw";
};

&spdif1_lpcg {
	bit-offset = <20 16>;
	clock-output-names = "spdif1_lpcg_tx_clk",
			     "spdif1_lpcg_gclkw";
};

&sai0_lpcg {
	bit-offset = <16 0>;
	clock-output-names = "sai0_lpcg_mclk",
			     "sai0_lpcg_ipg_clk";
};

&sai1_lpcg {
	bit-offset = <16 0>;
	clock-output-names = "sai1_lpcg_mclk",
			     "sai1_lpcg_ipg_clk";
};

&sai2_lpcg {
	bit-offset = <16 0>;
	clock-output-names = "sai2_lpcg_mclk",
			     "sai2_lpcg_ipg_clk";
};

&sai3_lpcg {
	bit-offset = <16 0>;
	clock-output-names = "sai3_lpcg_mclk",
			     "sai3_lpcg_ipg_clk";
};

&asrc1_lpcg {
	clocks = <&audio_ipg_clk>,
		 <&audio_ipg_clk>;
	bit-offset = <0 8>;
	clock-output-names = "asrc1_lpcg_ipg_clk",
			     "asrc1_lpcg_mem_clk";
};

&mqs0_lpcg {
	bit-offset = <16 0>;
	clock-output-names = "mqs0_lpcg_mclk",
			     "mqs0_lpcg_ipg_clk";
};

&dsp_lpcg {
	status = "disabled";
};

&dsp_ram_lpcg {
	status = "disabled";
};

&audio_subsys {
	acm: acm@59e00000 {
		compatible = "nxp,imx8qm-acm";
		reg = <0x59e00000 0x1D0000>;
		#clock-cells = <1>;
		power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
				<&pd IMX_SC_R_AUDIO_CLK_1>,
				<&pd IMX_SC_R_MCLK_OUT_0>,
				<&pd IMX_SC_R_MCLK_OUT_1>,
				<&pd IMX_SC_R_AUDIO_PLL_0>,
				<&pd IMX_SC_R_AUDIO_PLL_1>,
				<&pd IMX_SC_R_ASRC_0>,
				<&pd IMX_SC_R_ASRC_1>,
				<&pd IMX_SC_R_ESAI_0>,
				<&pd IMX_SC_R_ESAI_1>,
				<&pd IMX_SC_R_SAI_0>,
				<&pd IMX_SC_R_SAI_1>,
				<&pd IMX_SC_R_SAI_2>,
				<&pd IMX_SC_R_SAI_3>,
				<&pd IMX_SC_R_SAI_4>,
				<&pd IMX_SC_R_SAI_5>,
				<&pd IMX_SC_R_SAI_6>,
				<&pd IMX_SC_R_SAI_7>,
				<&pd IMX_SC_R_SPDIF_0>,
				<&pd IMX_SC_R_SPDIF_1>,
				<&pd IMX_SC_R_MQS_0>;
	};

	sai4: sai@59080000 {
		compatible = "fsl,imx8qm-sai";
		reg = <0x59080000 0x10000>;
		interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sai4_lpcg 1>,
			<&clk_dummy>,
			<&sai4_lpcg 0>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dma-names = "rx";
		dmas = <&edma0 18 0 1>;
		fsl,dataline = <0 0xf 0x0>;
		power-domains = <&pd IMX_SC_R_SAI_4>;
		status = "disabled";
	};

	sai5: sai@59090000 {
		compatible = "fsl,imx8qm-sai";
		reg = <0x59090000 0x10000>;
		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sai5_lpcg 1>,
			<&clk_dummy>,
			<&sai5_lpcg 0>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dma-names = "tx";
		dmas = <&edma0 19 0 0>;
		fsl,dataline = <0 0x0 0xf>;
		power-domains = <&pd IMX_SC_R_SAI_5>;
		status = "disabled";
	};

	esai1: esai@59810000 {
		compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";
		reg = <0x59810000 0x10000>;
		interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&esai1_lpcg 1>,
			<&esai1_lpcg 0>,
			<&esai1_lpcg 1>,
			<&clk_dummy>;
		clock-names = "core", "extal", "fsys", "spba";
		dmas = <&edma1 6 0 1>, <&edma1 7 0 0>;
		dma-names = "rx", "tx";
		power-domains = <&pd IMX_SC_R_ESAI_1>;
		status = "disabled";
	};

	sai6: sai@59820000 {
		compatible = "fsl,imx8qm-sai";
		reg = <0x59820000 0x10000>;
		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sai6_lpcg 1>,
			<&clk_dummy>,
			<&sai6_lpcg 0>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dma-names = "rx", "tx";
		dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
		power-domains = <&pd IMX_SC_R_SAI_6>;
		status = "disabled";
	};

	sai7: sai@59830000 {
		compatible = "fsl,imx8qm-sai";
		reg = <0x59830000 0x10000>;
		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sai7_lpcg 1>,
			<&clk_dummy>,
			<&sai7_lpcg 0>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dma-names = "tx";
		dmas = <&edma1 10 0 0>;
		power-domains = <&pd IMX_SC_R_SAI_7>;
		status = "disabled";
	};

	sai4_lpcg: clock-controller@59480000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59480000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <16 0>;
		clock-output-names = "sai4_lpcg_mclk",
				     "sai4_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SAI_4>;
		status = "disabled";
	};

	sai5_lpcg: clock-controller@59490000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59490000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <16 0>;
		clock-output-names = "sai5_lpcg_mclk",
				     "sai5_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SAI_5>;
		status = "disabled";
	};

	esai1_lpcg: clock-controller@59c10000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59c10000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <16 0>;
		clock-output-names = "esai1_lpcg_extal_clk",
				     "esai1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_ESAI_1>;
	};

	sai6_lpcg: clock-controller@59c20000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59c20000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <16 0>;
		clock-output-names = "sai6_lpcg_mclk",
				     "sai6_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SAI_6>;
	};

	sai7_lpcg: clock-controller@59c30000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59c30000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <16 0>;
		clock-output-names = "sai7_lpcg_mclk",
				     "sai7_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SAI_7>;
	};
};