// SPDX-License-Identifier: GPL-2.0+

/*
 * Copyright 2019 NXP
 */

/ {
	dsi_ipg_clk: clock-dsi-ipg {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <120000000>;
		clock-output-names = "dsi_ipg_clk";
	};

	mipi_pll_div2_clk: clock-mipi-div2-pll {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <432000000>;
		clock-output-names = "mipi_pll_div2_clk";
	};

	mipi0_subsys: bus@56220000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x56220000 0x0 0x56220000 0x10000>;

		mipi0_lis_lpcg: clock-controller@56223000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x56223000 0x4>;
			#clock-cells = <1>;
			clocks = <&dsi_ipg_clk>;
			bit-offset = <0>;
			clock-output-names = "mipi0_lis_lpcg_ipg_clk";
			power-domains = <&pd IMX_SC_R_MIPI_0>;
		};

		mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5622301c 0x4>;
			#clock-cells = <1>;
			clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
			bit-offset = <0>;
			clock-output-names = "mipi0_i2c0_lpcg_clk";
			power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
		};

		mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x56223018 0x4>;
			#clock-cells = <1>;
			clocks = <&dsi_ipg_clk>;
			bit-offset = <0>;
			clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
			power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
		};

		mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x56223014 0x4>;
			#clock-cells = <1>;
			clocks = <&mipi0_i2c0_lpcg_ipg_s_clk 0>;
			bit-offset = <0>;
			clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
			power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
		};

		mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5622302c 0x4>;
			#clock-cells = <1>;
			clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
			bit-offset = <0>;
			clock-output-names = "mipi0_i2c1_lpcg_clk";
			power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
		};

		mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x56223028 0x4>;
			#clock-cells = <1>;
			clocks = <&dsi_ipg_clk>;
			bit-offset = <0>;
			clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
			power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
		};

		mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x56223024 0x4>;
			#clock-cells = <1>;
			clocks = <&mipi0_i2c1_lpcg_ipg_s_clk 0>;
			bit-offset = <0>;
			clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
			power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
		};

		irqsteer_mipi0: irqsteer@56220000 {
			compatible = "fsl,imx-irqsteer";
			reg = <0x56220000 0x1000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			interrupt-parent = <&gic>;
			#interrupt-cells = <1>;
			fsl,channel = <0>;
			fsl,num-irqs = <32>;
			clocks = <&mipi0_lis_lpcg 0>;
			clock-names = "ipg";
			power-domains = <&pd IMX_SC_R_MIPI_0>;
		};

		i2c0_mipi0: i2c@56226000 {
			#address-cells = <1>;
		        #size-cells = <0>;
			compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
			reg = <0x56226000 0x1000>;
			interrupts = <8>;
			interrupt-parent = <&irqsteer_mipi0>;
			clocks = <&mipi0_i2c0_lpcg_clk 0>,
				 <&mipi0_i2c0_lpcg_ipg_clk 0>;
			clock-names = "per", "ipg";
			assigned-clocks = <&mipi0_i2c0_lpcg_clk 0>;
			assigned-clock-rates = <24000000>;
			power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
			status = "disabled";
		};

		mipi0_csr: csr@56221000 {
			compatible = "syscon";
			reg = <0x56221000 0x240>;
		};

		mipi0_dphy: dphy@56228300 {
			compatible = "fsl,imx8qm-mipi-dphy";
			reg = <0x56228300 0x100>;
			clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>;
			clock-names = "phy_ref";
			#phy-cells = <0>;
			power-domains = <&pd IMX_SC_R_MIPI_0>;
			status = "disabled";
		};

		mipi0_dsi_host: dsi_host@56228000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,imx8qm-nwl-dsi";
			reg = <0x56228000 0x300>;
			clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>,
				 <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>,
				 <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>,
				 <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>,
				 <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>,
				 <&mipi_pll_div2_clk>;
			clock-names = "pixel",
				      "bypass",
				      "phy_ref",
				      "tx_esc",
				      "rx_esc",
				      "phy_parent";
			interrupts = <16>;
			interrupt-parent = <&irqsteer_mipi0>;
			power-domains = <&pd IMX_SC_R_MIPI_0>;
			phys = <&mipi0_dphy>;
			phy-names = "dphy";
			csr = <&mipi0_csr>;
			use-disp-ss;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				mipi0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <0>;
					mipi0_dsi_in: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&dpu1_disp0_mipi0>;
					};
				};
			};
		};
	};

	mipi1_subsys: bus@57220000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x57220000 0x0 0x57220000 0x10000>;

		mipi1_lis_lpcg: clock-controller@57223000 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x57223000 0x4>;
			#clock-cells = <1>;
			clocks = <&dsi_ipg_clk>;
			bit-offset = <0>;
			clock-output-names = "mipi1_lis_lpcg_ipg_clk";
			power-domains = <&pd IMX_SC_R_MIPI_1>;
		};

		mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5722301c 0x4>;
			#clock-cells = <1>;
			clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
			bit-offset = <0>;
			clock-output-names = "mipi1_i2c0_lpcg_clk";
			power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
		};

		mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x57223018 0x4>;
			#clock-cells = <1>;
			clocks = <&dsi_ipg_clk>;
			bit-offset = <0>;
			clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
			power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
		};

		mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x57223014 0x4>;
			#clock-cells = <1>;
			clocks = <&mipi1_i2c0_lpcg_ipg_s_clk 0>;
			bit-offset = <0>;
			clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
			power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
		};

		mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x5722302c 0x4>;
			#clock-cells = <1>;
			clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
			bit-offset = <0>;
			clock-output-names = "mipi1_i2c1_lpcg_clk";
			power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
		};

		mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x57223028 0x4>;
			#clock-cells = <1>;
			clocks = <&dsi_ipg_clk>;
			bit-offset = <0>;
			clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
			power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
		};

		mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
			compatible = "fsl,imx8qxp-lpcg";
			reg = <0x57223024 0x4>;
			#clock-cells = <1>;
			clocks = <&mipi1_i2c1_lpcg_ipg_s_clk 0>;
			bit-offset = <0>;
			clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
			power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
		};

		irqsteer_mipi1: irqsteer@57220000 {
			compatible = "fsl,imx-irqsteer";
			reg = <0x57220000 0x1000>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			interrupt-parent = <&gic>;
			#interrupt-cells = <1>;
			fsl,channel = <0>;
			fsl,num-irqs = <32>;
			clocks = <&mipi1_lis_lpcg 0>;
			clock-names = "ipg";
			power-domains = <&pd IMX_SC_R_MIPI_1>;
		};

		i2c0_mipi1: i2c@57226000 {
			#address-cells = <1>;
		        #size-cells = <0>;
			compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
			reg = <0x57226000 0x1000>;
			interrupts = <8>;
			interrupt-parent = <&irqsteer_mipi1>;
			clocks = <&mipi1_i2c0_lpcg_clk 0>,
				 <&mipi1_i2c0_lpcg_ipg_clk 0>;
			clock-names = "per", "ipg";
			assigned-clocks = <&mipi1_i2c0_lpcg_clk 0>;
			assigned-clock-rates = <24000000>;
			power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
			status = "disabled";
		};

		mipi1_csr: csr@57221000 {
			compatible = "syscon";
			reg = <0x57221000 0x240>;
		};

		mipi1_dphy: dphy@57228300 {
			compatible = "fsl,imx8qm-mipi-dphy";
			reg = <0x57228300 0x100>;
			clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>;
			clock-names = "phy_ref";
			#phy-cells = <0>;
			power-domains = <&pd IMX_SC_R_MIPI_1>;
			status = "disabled";
		};

		mipi1_dsi_host: dsi_host@57228000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,imx8qm-nwl-dsi";
			reg = <0x57228000 0x300>;
			clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>,
				 <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>,
				 <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>,
				 <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>,
				 <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>,
				 <&mipi_pll_div2_clk>;
			clock-names = "pixel",
				      "bypass",
				      "phy_ref",
				      "tx_esc",
				      "rx_esc",
				      "phy_parent";
			interrupts = <16>;
			interrupt-parent = <&irqsteer_mipi1>;
			power-domains = <&pd IMX_SC_R_MIPI_1>;
			phys = <&mipi1_dphy>;
			phy-names = "dphy";
			csr = <&mipi1_csr>;
			use-disp-ss;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				mipi1_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <0>;
					mipi1_dsi_in: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&dpu2_disp0_mipi1>;
					};
				};
			};
		};
	};
};