/*
 * Copyright 2019 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&fec1 {
	status = "disabled";
};

&fec2 {
	pinctrl-0 = <&pinctrl_fec2_rmii>;
	clocks = <&enet1_lpcg 4>,
		 <&enet1_lpcg 2>,
		 <&clk IMX_SC_R_ENET_1 IMX_SC_C_DISABLE_50>,
		 <&enet1_lpcg 0>,
		 <&enet1_lpcg 1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy2>;
	/delete-property/ phy-supply;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy2: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <2>;
			tja110x,refclk_in;
		};
	};
};

&iomuxc {
	pinctrl_fec2_rmii: fec2rmiigrp {
		fsl,pins = <
			IMX8QXP_ENET0_MDC_CONN_ENET1_MDC		0x06000020
			IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO		0x06000020
			IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT	0x06000020
			IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000020
			IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000020
			IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER	0x06000020
			IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL	0x06000020
			IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000020
			IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000020
			IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL	0x06000020
		>;
	};
};