// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 NXP
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "NXP i.MX93 11x11 EVK";
	compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		mmc0 = &usdhc1;
		serial1 = &lpuart2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		A55_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0>;
			enable-method = "psci";
			#cooling-cells = <2>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	gic: interrupt-controller@48000000 {
		compatible = "arm,gic-v3";
		reg = <0 0x48000000 0 0x10000>,
		      <0 0x48040000 0 0xc0000>;
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
	};

	clk_dummy: clock-dummy {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "clk_dummy";
	};

	clk_400m: clock-400m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <200000000>;
		clock-output-names = "200m";
	};

	osc_24m: clock-osc-24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc_24m";
	};

	pci@fd700000 {
		compatible = "pci-host-ecam-generic";
		device_type = "pci";
		bus-range = <0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &gic GIC_SPI 227 IRQ_TYPE_EDGE_RISING>,
				<0 0 0 2 &gic GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
				<0 0 0 3 &gic GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
				<0 0 0 4 &gic GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
		reg = <0x0 0xfd700000 0x0 0x100000>;
		ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x80000000>,
			 <0x28000000 0x0 0x28000000 0x10000000>;

		aips1: bus@44000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x44000000 0x800000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			lpuart2: serial@44390000 {
				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
				reg = <0x44390000 0x1000>;
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};
                };

		aips3: bus@42800000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x42800000 0x800000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			usdhc1: mmc@42850000 {
				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
				reg = <0x42850000 0x10000>;
				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				status = "disabled";
			};
                };
	};
};

&lpuart2 {
	clocks = <&osc_24m>;
	clock-names = "ipg";
	status = "okay";
};

&usdhc1 {
	clocks = <&clk_dummy>,
		 <&clk_dummy>,
		 <&clk_400m>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <8>;
	non-removable;
	status = "okay";
};