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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 NXP
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: iMX8MQ Display Controller Subsystem (DCSS)
maintainers:
- Laurentiu Palcu <laurentiu.palcu@nxp.com>
description:
The DCSS (display controller sub system) is used to source up to three
display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
image processing capabilities are included to provide a solution capable of
driving next generation high dynamic range displays.
properties:
compatible:
const: nxp,imx8mq-dcss
reg:
maxItems: 2
interrupts:
maxItems: 3
items:
- description: Context loader completion and error interrupt
- description: DTG interrupt used to signal context loader trigger time
- description: DTG interrupt for Vblank
interrupt-names:
maxItems: 3
items:
- const: ctx_ld
- const: ctxld_kick
- const: vblank
- const: dtrc_ch1
- const: dtrc_ch2
clocks:
maxItems: 5
items:
- description: Display APB clock for all peripheral PIO access interfaces
- description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
- description: RTRAM clock
- description: Pixel clock, can be driver either by HDMI phy clock or MIPI
- description: DTRC clock, needed by video decompressor
- description: PLL source clock, usually VIDEO2_PLL, used when output is HDMI;
- description: PLL PHY reference clock, used when output is HDMI;
clock-names:
items:
- const: apb
- const: axi
- const: rtrm
- const: pix
- const: dtrc
- const: pll_src
- const: pll_phy_ref
port@0:
type: object
description: A port node pointing to a hdmi_in or mipi_in port node.
examples:
- |
dcss: display-controller@32e00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imx8mq-dcss";
reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
interrupts = <6>, <8>, <9>, <16>, <17>;
interrupt-names = "ctx_ld", "ctxld_kick", "vblank", "dtrc_ch1", "dtrc_ch2";
interrupt-parent = <&irqsteer>;
clocks = <&clk 248>, <&clk 247>, <&clk 249>,
<&clk 254>,<&clk 122>, <&clk 266>, <&clk 267>;
clock-names = "apb", "axi", "rtrm", "pix", "dtrc",
"pll_src", "pll_phy_ref";
assigned-clocks = <&clk 107>, <&clk 109>, <&clk 266>;
assigned-clock-parents = <&clk 78>, <&clk 78>, <&clk 3>;
assigned-clock-rates = <800000000>,
<400000000>;
port@0 {
dcss_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
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