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* Freescale Fast Ethernet Controller (FEC)
Required properties:
- compatible : Should be "fsl,<soc>-fec"
- reg : Address and length of the register set for the device
- interrupts : Should contain fec interrupt
- phy-mode : See ethernet.txt file in the same directory
- clock-name: Should be the names of the clocks
- "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing
- "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock
- "ptp"(option), for IEEE1588 timer clock that requires the clock
- "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
RGMII TXC clock or RMII reference clock. It depends on board design,
the clock is required if RGMII TXC and RMII reference clock source from
SOC internal PLL.
- "enet_out"(option), output clock for external device, like supply clock
for PHY. The clock is required if PHY clock source from SOC.
- "enet_2x_txclk"(option), for RGMII sampleing clock which fixed at 250Mhz.
The clock is required if SOC RGMII enable clock delay.
- clocks: Phandles to input clocks.
Optional properties:
- phy-supply : regulator that powers the Ethernet PHY.
- phy-handle : phandle to the PHY device connected to this device.
- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
Use instead of phy-handle.
- fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
hw multi queues. Should specify the tx queue number, otherwise set tx queue
number to 1.
- fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
hw multi queues. Should specify the rx queue number, otherwise set rx queue
number to 1.
- fsl,magic-packet : If present, indicates that the hardware supports waking
up via magic packet.
- fsl,err006687-workaround-present: If present indicates that the system has
the hardware workaround for ERR006687 applied and does not need a software
workaround.
-interrupt-names: names of the interrupts listed in interrupts property in
the same order. The defaults if not specified are
__Number of interrupts__ __Default__
1 "int0"
2 "int0", "pps"
3 "int0", "int1", "int2"
4 "int0", "int1", "int2", "pps"
The order may be changed as long as they correspond to the interrupts
property. Currently, only i.mx7 uses "int1" and "int2". They correspond to
tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts.
For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse
per second interrupt associated with 1588 precision time protocol(PTP).
- fsl,wakeup_irq : The property defines the wakeup irq index in enet irq source.
- stop-mode : If present, indicates soc need to set gpr bit to request stop mode.
- mii-exclusive: If present, each MAC has their exclusive MDIO bus in current board
design, otherwise multiple MACs share one MDIO bus to reduce Pins utilize.
Optional subnodes:
- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
according to phy.txt in the same directory
Deprecated optional properties:
To avoid these, create a phy node according to phy.txt in the same
directory, and point the fec's "phy-handle" property to it. Then use
the phy's reset binding, again described by phy.txt.
- phy-reset-gpios : Should specify the gpio for phy reset
- phy-reset-duration : Reset duration in milliseconds. Should present
only if property "phy-reset-gpios" is available. Missing the property
will have the duration be 1 millisecond. Numbers greater than 1000 are
invalid and 1 millisecond will be used instead.
- phy-reset-active-high : If present then the reset sequence using the GPIO
specified in the "phy-reset-gpios" property is reversed (H=reset state,
L=operation state).
- phy-reset-post-delay : Post reset delay in milliseconds. If present then
a delay of phy-reset-post-delay milliseconds will be observed after the
phy-reset-gpios has been toggled. Can be omitted thus no delay is
observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.
Example:
ethernet@83fec000 {
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; /* GPIO2_14 */
local-mac-address = [00 04 9F 01 1B B9];
phy-supply = <®_fec_supply>;
};
Example with phy specified:
ethernet@83fec000 {
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; /* GPIO2_14 */
local-mac-address = [00 04 9F 01 1B B9];
phy-supply = <®_fec_supply>;
phy-handle = <ðphy>;
mdio {
ethphy: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <6>;
max-speed = <100>;
};
};
};
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