summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/armada-xp-db.dts
blob: f5fc1a3868a2e39e139fc76f900c23fb03457b2a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
/*
 * Device Tree file for Marvell Armada XP evaluation board
 * (DB-78460-BP)
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

/dts-v1/;
/include/ "armada-xp-mv78460.dtsi"

/ {
	model = "Marvell Armada XP Evaluation Board";
	compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk";
	};

	memory {
		device_type = "memory";
		reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
	};

	soc {
		ranges = <0          0 0xd0000000 0x100000	/* Internal registers 1MiB */
			  0xf0000000 0 0xf0000000 0x1000000>;	/* Device Bus, NOR 16MiB   */

		internal-regs {
			serial@12000 {
				clock-frequency = <250000000>;
				status = "okay";
			};
			serial@12100 {
				clock-frequency = <250000000>;
				status = "okay";
			};
			serial@12200 {
				clock-frequency = <250000000>;
				status = "okay";
			};
			serial@12300 {
				clock-frequency = <250000000>;
				status = "okay";
			};

			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			mdio {
				phy0: ethernet-phy@0 {
					reg = <0>;
				};

				phy1: ethernet-phy@1 {
					reg = <1>;
				};

				phy2: ethernet-phy@2 {
					reg = <25>;
				};

				phy3: ethernet-phy@3 {
					reg = <27>;
				};
			};

			ethernet@70000 {
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};
			ethernet@74000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
			};
			ethernet@30000 {
				status = "okay";
				phy = <&phy2>;
				phy-mode = "sgmii";
			};
			ethernet@34000 {
				status = "okay";
				phy = <&phy3>;
				phy-mode = "sgmii";
			};

			mvsdio@d4000 {
				pinctrl-0 = <&sdio_pins>;
				pinctrl-names = "default";
				status = "okay";
				/* No CD or WP GPIOs */
				broken-cd;
			};

			usb@50000 {
				status = "okay";
			};

			usb@51000 {
				status = "okay";
			};

			usb@52000 {
				status = "okay";
			};

			spi0: spi@10600 {
				status = "okay";

				spi-flash@0 {
					#address-cells = <1>;
					#size-cells = <1>;
					compatible = "m25p64";
					reg = <0>; /* Chip select 0 */
					spi-max-frequency = <20000000>;
				};
			};

			pcie-controller {
				status = "okay";

				/*
				 * All 6 slots are physically present as
				 * standard PCIe slots on the board.
				 */
				pcie@1,0 {
					/* Port 0, Lane 0 */
					status = "okay";
				};
				pcie@2,0 {
					/* Port 0, Lane 1 */
					status = "okay";
				};
				pcie@3,0 {
					/* Port 0, Lane 2 */
					status = "okay";
				};
				pcie@4,0 {
					/* Port 0, Lane 3 */
					status = "okay";
				};
				pcie@9,0 {
					/* Port 2, Lane 0 */
					status = "okay";
				};
				pcie@10,0 {
					/* Port 3, Lane 0 */
					status = "okay";
				};
			};

			devbus-bootcs@10400 {
				status = "okay";
				ranges = <0 0xf0000000 0x1000000>;

				/* Device Bus parameters are required */

				/* Read parameters */
				devbus,bus-width    = <8>;
				devbus,turn-off-ps  = <60000>;
				devbus,badr-skew-ps = <0>;
				devbus,acc-first-ps = <124000>;
				devbus,acc-next-ps  = <248000>;
				devbus,rd-setup-ps  = <0>;
				devbus,rd-hold-ps   = <0>;

				/* Write parameters */
				devbus,sync-enable = <0>;
				devbus,wr-high-ps  = <60000>;
				devbus,wr-low-ps   = <60000>;
				devbus,ale-wr-ps   = <60000>;

				/* NOR 16 MiB */
				nor@0 {
					compatible = "cfi-flash";
					reg = <0 0x1000000>;
					bank-width = <2>;
				};
			};
		};
	};
};