summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/bcm63138.dtsi
blob: f3bb2dd6269eed53f69d1e1e0135df764682dfb5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
/*
 * Broadcom BCM63138 DSL SoCs Device Tree
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "skeleton.dtsi"

/ {
	compatible = "brcm,bcm63138";
	model = "Broadcom BCM63138 DSL SoC";
	interrupt-parent = <&gic>;

	aliases {
		uart0 = &serial0;
		uart1 = &serial1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <1>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <500000000>;
		};

		periph_clk: periph_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
			clock-output-names = "periph";
		};
	};

	/* ARM bus */
	axi@80000000 {
		compatible = "simple-bus";
		ranges = <0 0x80000000 0x784000>;
		#address-cells = <1>;
		#size-cells = <1>;

		L2: cache-controller@1d000 {
			compatible = "arm,pl310-cache";
			reg = <0x1d000 0x1000>;
			cache-unified;
			cache-level = <2>;
			cache-sets = <16>;
			cache-size = <0x80000>;
			interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
		};

		scu: scu@1e000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0x1e000 0x100>;
		};

		gic: interrupt-controller@1e100 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x1f000 0x1000
				0x1e100 0x100>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
		};

		global_timer: timer@1e200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x1e200 0x20>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&arm_timer_clk>;
		};

		local_timer: local-timer@1e600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x1e600 0x20>;
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&arm_timer_clk>;
		};

		twd_watchdog: watchdog@1e620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x1e620 0x20>;
			interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	/* Legacy UBUS base */
	ubus@fffe8000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xfffe8000 0x8100>;

		serial0: serial@600 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x600 0x1b>;
			interrupts = <GIC_SPI 32 0>;
			clocks = <&periph_clk>;
			clock-names = "periph";
			status = "disabled";
		};

		serial1: serial@620 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x620 0x1b>;
			interrupts = <GIC_SPI 33 0>;
			clocks = <&periph_clk>;
			clock-names = "periph";
			status = "disabled";
		};
	};
};