summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/dra74x.dtsi
blob: 0a78347e6615651b16bf0b50bff32c50f55103b8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
/*
 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

#include "dra7.dtsi"

/ {
	compatible = "ti,dra742", "ti,dra74", "ti,dra7";

	cpus {
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupt-parent = <&wakeupgen>;
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	};

	ocp {
		dsp2_system: dsp_system@41500000 {
			compatible = "syscon";
			reg = <0x41500000 0x100>;
		};

		omap_dwc3_4: omap_dwc3_4@48940000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss4";
			reg = <0x48940000 0x10000>;
			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <2>;
			ranges;
			status = "disabled";
			usb4: usb@48950000 {
				compatible = "snps,dwc3";
				reg = <0x48950000 0x17000>;
				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "peripheral",
						  "host",
						  "otg";
				maximum-speed = "high-speed";
				dr_mode = "otg";
			};
		};

		mmu0_dsp2: mmu@41501000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x41501000 0x100>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmu0_dsp2";
			#iommu-cells = <0>;
			ti,syscon-mmuconfig = <&dsp2_system 0x0>;
			status = "disabled";
		};

		mmu1_dsp2: mmu@41502000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x41502000 0x100>;
			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mmu1_dsp2";
			#iommu-cells = <0>;
			ti,syscon-mmuconfig = <&dsp2_system 0x1>;
			status = "disabled";
		};
	};
};

&dss {
	reg = <0x58000000 0x80>,
	      <0x58004054 0x4>,
	      <0x58004300 0x20>,
	      <0x58009054 0x4>,
	      <0x58009300 0x20>;
	reg-names = "dss", "pll1_clkctrl", "pll1",
		    "pll2_clkctrl", "pll2";

	clocks = <&dss_dss_clk>,
		 <&dss_video1_clk>,
		 <&dss_video2_clk>;
	clock-names = "fck", "video1_clk", "video2_clk";
};

&mailbox5 {
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		ti,mbox-tx = <6 2 2>;
		ti,mbox-rx = <4 2 2>;
		status = "disabled";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		ti,mbox-tx = <5 2 2>;
		ti,mbox-rx = <1 2 2>;
		status = "disabled";
	};
};

&mailbox6 {
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		ti,mbox-tx = <6 2 2>;
		ti,mbox-rx = <4 2 2>;
		status = "disabled";
	};
	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
		ti,mbox-tx = <5 2 2>;
		ti,mbox-rx = <1 2 2>;
		status = "disabled";
	};
};