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|
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include "imx6.dtsi"
#include "imx6dl-pinfunc.h"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&L2>;
};
};
cpufreq-setpoint {
compatible = "fsl,imx_cpufreq";
setpoint-number = <3>;
clocks = <&clks 170>, <&clks 17>, <&clks 16>, <&clks 6>, <&clks 104>;
clock-names = "pll1_sys", "pll1_sw", "step", "pll2_pfd2_396m", "arm";
396000000 {
compatible = "fsl,396m", "setpoint-table";
pll_rate = <396000000>;
cpu_rate = <396000000>;
cpu_podf = <0>;
pu_voltage = <1175000>;
soc_voltage = <1175000>;
cpu_voltage = <1075000>;
};
792000000 {
compatible = "fsl,792m", "setpoint-table";
pll_rate = <792000000>;
cpu_rate = <792000000>;
cpu_podf = <0>;
pu_voltage = <1175000>;
soc_voltage = <1175000>;
cpu_voltage = <1175000>;
};
996000000 {
compatible = "fsl,996m", "setpoint-table";
pll_rate = <996000000>;
cpu_rate = <996000000>;
cpu_podf = <0>;
pu_voltage = <1175000>;
soc_voltage = <1175000>;
cpu_voltage = <1250000>;
};
};
irq_tuner {
gpu3d {
compatible = "fsl,gpu3d", "irq-threshold";
irq_number = <41>;
up_threshold = <0>;
enabled;
};
gpu2d {
compatible = "fsl,gpu2d", "irq-threshold";
irq_number = <42>;
up_threshold = <40>;
enabled;
};
gpuvg {
compatible = "fsl,gpuvg", "irq-threshold";
irq_number = <43>;
up_threshold = <0>;
enabled;
};
usdhc1 {
compatible = "fsl,usdhc1", "irq-threshold";
irq_number = <54>;
up_threshold = <4>;
enabled;
};
usdhc2 {
compatible = "fsl,usdhc2", "irq-threshold";
irq_number = <55>;
up_threshold = <4>;
enabled;
};
usdhc3 {
compatible = "fsl,usdhc3", "irq-threshold";
irq_number = <56>;
up_threshold = <4>;
enabled;
};
usdhc4 {
compatible = "fsl,usdhc4", "irq-threshold";
irq_number = <57>;
up_threshold = <4>;
enabled;
};
sata {
compatible = "fsl,sata", "irq-threshold";
irq_number = <71>;
up_threshold = <4>;
enabled;
};
otg {
compatible = "fsl,otg", "irq-threshold";
irq_number = <75>;
up_threshold = <10>;
enabled;
};
enet {
compatible = "fsl,enet", "irq-threshold";
irq_number = <150>;
up_threshold = <4>;
enabled;
};
};
busfreq { /* BUSFREQ */
compatible = "fsl,imx_busfreq";
clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
<&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
clock-names = "pll2_bus_clk", "pll2_pfd2_396m_clk", "pll2_198m_clk", "arm_clk", "pll3_usb_otg_clk", "periph_clk",
"periph_pre_clk", "periph_clk2_clk", "periph_clk2_sel_clk", "osc_clk";
iram_data1_base = <0x91c000>;
iram_data1_size = <0x800>;
iram_data2_base = <0x91c800>;
iram_data2_size = <0x800>;
iram_code_base = <0x91d000>;
iram_code_size = <0x2000>;
irq1 = <139>;
irq2 = <144>;
irq3 = <145>;
irq4 = <146>;
};
suspend { /* SUSPEND */
compatible = "fsl,imx_suspend";
iram_code_base = <0x91f000>;
iram_code_size = <0x1000>;
};
soc {
gpu@00130000 {
reg = <0x00130000 0x4000>, <0x00134000 0x4000>, <0x0 0x0>;
reg-names = "iobase_3d", "iobase_2d", "phys_baseaddr";
interrupts = <0 9 0x04>, <0 10 0x04>;
interrupt-names = "irq_3d", "irq_2d";
clocks = <&clks 143>, <&clks 27>, <&clks 121>, <&clks 122>, <&clks 0>;
clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", "gpu2d_clk", "gpu3d_clk", "gpu3d_shader_clk";
};
aips1: aips-bus@02000000 {
vpu@02040000 {
iramsize = <0>;
status = "okay";
};
iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
reg = <0x020e0000 0x4000>;
/* shared pinctrl settings */
audmux {
pinctrl_audmux_2: audmux-2 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
>;
};
pinctrl_audmux_3: audmux-3 {
fsl,pins = <
MX6DL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
MX6DL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
MX6DL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
pinctrl_ecspi1_2: ecspi1cr-1 {
fsl,pins = <
MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
>;
};
};
spdif {
pinctrl_spdif_1: spdifgrp-1 {
fsl,pins = <
MX6DL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
>;
};
pinctrl_spdif_2: spdifgrp-2 {
fsl,pins = <
MX6DL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
MX6DL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
>;
};
};
enet {
pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
>;
};
pinctrl_enet_2: enetgrp-2 {
fsl,pins = <
MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
>;
};
};
flexcan1 {
pinctrl_flexcan1_1: flexcan1grp-1 {
fsl,pins = <
MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
>;
};
pinctrl_flexcan1_2: flexcan1grp-2 {
fsl,pins = <
MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
>;
};
};
flexcan2 {
pinctrl_flexcan2_1: flexcan2grp-1 {
fsl,pins = <
MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
>;
};
};
i2c1 {
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
};
i2c2 {
pinctrl_i2c2_2: i2c2grp-2 {
fsl,pins = <
MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
>;
};
pinctrl_i2c2_3: i2c2grp-3 {
fsl,pins = <
MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
>;
};
};
i2c3 {
pinctrl_i2c3_2: i2c3grp-2 {
fsl,pins = <
MX6DL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6DL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_i2c3_4: i2c3grp-4 {
fsl,pins = <
MX6DL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
};
ipu1 {
pinctrl_ipu1_1: ipu1grp-1 {
fsl,pins = <
MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_ipu1_csi0_1: ipu1csi0grp-1 { /* parallel port */
fsl,pins = <
MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
>;
};
};
epdc {
pinctrl_epdc_0: epdcgrp-1 {
fsl,pins = <
MX6DL_PAD_EIM_A16__EPDC_DATA00 0x80000000
MX6DL_PAD_EIM_DA10__EPDC_DATA01 0x80000000
MX6DL_PAD_EIM_DA12__EPDC_DATA02 0x80000000
MX6DL_PAD_EIM_DA11__EPDC_DATA03 0x80000000
MX6DL_PAD_EIM_LBA__EPDC_DATA04 0x80000000
MX6DL_PAD_EIM_EB2__EPDC_DATA05 0x80000000
MX6DL_PAD_EIM_CS0__EPDC_DATA06 0x80000000
MX6DL_PAD_EIM_RW__EPDC_DATA07 0x80000000
MX6DL_PAD_EIM_A21__EPDC_GDCLK 0x80000000
MX6DL_PAD_EIM_A22__EPDC_GDSP 0x80000000
MX6DL_PAD_EIM_A23__EPDC_GDOE 0x80000000
MX6DL_PAD_EIM_A24__EPDC_GDRL 0x80000000
MX6DL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000
MX6DL_PAD_EIM_D27__EPDC_SDOE 0x80000000
MX6DL_PAD_EIM_DA1__EPDC_SDLE 0x80000000
MX6DL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000
MX6DL_PAD_EIM_DA2__EPDC_BDR0 0x80000000
MX6DL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000
MX6DL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000
MX6DL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000
>;
};
};
mlb {
pinctrl_mlb_1: mlbgrp-1 {
fsl,pins = <
MX6DL_PAD_GPIO_3__MLB_CLK 0x71
MX6DL_PAD_GPIO_6__MLB_SIG 0x71
MX6DL_PAD_GPIO_2__MLB_DATA 0x71
>;
};
pinctrl_mlb_2: mlbgrp-2 {
fsl,pins = <
MX6DL_PAD_ENET_TXD1__MLB_CLK 0x71
MX6DL_PAD_GPIO_6__MLB_SIG 0x71
MX6DL_PAD_GPIO_2__MLB_DATA 0x71
>;
};
};
pwm0 {
pinctrl_pwm0_0: pwm0-1 {
fsl,pins = <
MX6DL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm0_1: pwm0-3 {
fsl,pins = <
MX6DL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
};
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
};
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
usbotg {
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
};
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
MX6DL_PAD_GPIO_18__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_3: usdhc3grp-3 { /* 100Mhz */
fsl,pins = <
MX6DL_PAD_SD3_CMD__SD3_CMD 0x170B9
MX6DL_PAD_SD3_CLK__SD3_CLK 0x100B9
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x170B9
MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x170B9
MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x170B9
MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x170B9
MX6DL_PAD_GPIO_18__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_4: usdhc3grp-4 { /* 200Mhz */
fsl,pins = <
MX6DL_PAD_SD3_CMD__SD3_CMD 0x170F9
MX6DL_PAD_SD3_CLK__SD3_CLK 0x100F9
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x170F9
MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x170F9
MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x170F9
MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x170F9
MX6DL_PAD_GPIO_18__SD3_VSELECT 0x17059
>;
};
};
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
MX6DL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6DL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
};
esai {
pinctrl_esai_1: esaigrp-1 {
fsl,pins = <
MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1B030
MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1B030
MX6DL_PAD_ENET_RXD1__ESAI_TX_FS 0x1B030
MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1B030
MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1B030
MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1B030
MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1B030
MX6DL_PAD_NANDF_CS2__ESAI_TX0 0x1B030
MX6DL_PAD_NANDF_CS3__ESAI_TX1 0x1B030
/* MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1B030 */
/* MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1B030 */
/* MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1B030 */
>;
};
pinctrl_esai_2: esaigrp-2 {
fsl,pins = <
MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1B030
MX6DL_PAD_ENET_RXD1__ESAI_TX_FS 0x1B030
MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1B030
MX6DL_PAD_GPIO_5__ESAI_TX2_RX3 0x1B030
MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1B030
MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1B030
MX6DL_PAD_GPIO_17__ESAI_TX0 0x1B030
MX6DL_PAD_NANDF_CS3__ESAI_TX1 0x1B030
MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1B030
MX6DL_PAD_GPIO_9__ESAI_RX_FS 0x1B030
>;
};
};
weim {
pinctrl_weim_cs0_1: weim_cs0grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_nor_1: weim_norgrp-1 {
fsl,pins = <
MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
/* data */
MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
/* address */
MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
>;
};
};
hdmi_hdcp {
pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
fsl,pins = <
MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
>;
};
pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
fsl,pins = <
MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
>;
};
pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
fsl,pins = <
MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
>;
};
};
hdmi_cec {
pinctrl_hdmi_cec_1: hdmicecgrp-1 {
fsl,pins = <
MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_hdmi_cec_2: hdmicecgrp-2 {
fsl,pins = <
MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
};
};
pxp@020f0000 {
compatible = "fsl,imx6dl-pxp-dma";
reg = <0x020f0000 0x4000>;
interrupts = <0 98 0x04>;
clocks = <&clks 133>;
clock-names = "pxp-axi";
status = "disabled";
};
epdc@020f4000 {
compatible = "fsl,imx6-epdc";
reg = <0x020f4000 0x4000>;
interrupts = <0 97 0x04>;
clocks = <&clks 133>, <&clks 137>;
clock-names = "epdc_axi", "epdc_pix";
};
lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 0x04>;
};
};
aips2: aips-bus@02100000 {
i2c4: i2c@021f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-i2c";
reg = <0x021f8000 0x4000>;
interrupts = <0 35 0x04>;
clocks = <&clks 218>;
status = "disabled";
};
};
};
};
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