summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
blob: 8d5f8dc6ad58cd9e303851261539d03ab740208a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
 * Author: Christian Hemp <c.hemp@phytec.de>
 */

/ {
	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
	compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";

	aliases {
		rtc0 = &i2c_rtc;
		rtc1 = &snvs_rtc;
	};

	reg_sound_1v8: regulator-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "i2s-audio-1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		status = "disabled";
	};

	reg_sound_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "i2s-audio-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		status = "disabled";
	};

	reg_can1_en: regulator-can1 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&princtrl_flexcan1_en>;
		regulator-name = "Can";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		status = "disabled";
	};

	reg_adc1_vref_3v3: regulator-vref-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vref-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	sound: sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,widgets =
			"Line", "Line In",
			"Line", "Line Out",
			"Speaker", "Speaker";
		simple-audio-card,routing =
			"Line Out", "LLOUT",
			"Line Out", "RLOUT",
			"Speaker", "SPOP",
			"Speaker", "SPOM",
			"LINE1L", "Line In",
			"LINE1R", "Line In";
		status = "disabled";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&tlv320>;
			clocks = <&clks IMX6UL_CLK_SAI2>;
		};
	};

};

&adc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc1>;
	vref-supply = <&reg_adc1_vref_3v3>;
	/*
	 * driver can not separate a specific channel so we request 4 channels
	 * here - we need only the fourth channel
	 */
	num-channels = <4>;
	status = "disabled";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can1_en>;
	status = "disabled";
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <786432000>;
};

&ecspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
	status = "disabled";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rmii";
	phy-handle = <&ethphy2>;
	status = "disabled";
};

&i2c1 {
	tlv320: codec@18 {
		compatible = "ti,tlv320aic3007";
		#sound-dai-cells = <0>;
		reg = <0x18>;
		AVDD-supply = <&reg_sound_3v3>;
		IOVDD-supply = <&reg_sound_3v3>;
		DRVDD-supply = <&reg_sound_3v3>;
		DVDD-supply = <&reg_sound_1v8>;
		status = "disabled";
	};

	stmpe: touchscreen@44 {
		compatible = "st,stmpe811";
		reg = <0x44>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		interrupt-parent = <&gpio5>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_stmpe>;
		status = "disabled";

		touchscreen {
			compatible = "st,stmpe-ts";
			st,sample-time = <4>;
			st,mod-12b = <1>;
			st,ref-sel = <0>;
			st,adc-freq = <1>;
			st,ave-ctrl = <1>;
			st,touch-det-delay = <2>;
			st,settling = <2>;
			st,fraction-z = <7>;
			st,i-drive = <1>;
			touchscreen-inverted-x = <1>;
			touchscreen-inverted-y = <1>;
		};
	};

	i2c_rtc: rtc@68 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_rtc_int>;
		compatible = "microcrystal,rv4162";
		reg = <0x68>;
		interrupt-parent = <&gpio5>;
		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
		status = "disabled";
	};
};

&mdio {
	ethphy2: ethernet-phy@2 {
		reg = <2>;
		micrel,led-mode = <1>;
		clocks = <&clks IMX6UL_CLK_ENET2_REF>;
		clock-names = "rmii-ref";
		status = "disabled";
	};
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "disabled";
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
			<&clks IMX6UL_CLK_SAI2>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <0>, <19200000>;
	fsl,sai-mclk-direction-output;
	status = "disabled";
};

&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	uart-has-rtscts;
	status = "disabled";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	dr_mode = "otg";
	status = "disabled";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "disabled";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	status = "disabled";
};

&iomuxc {
	pinctrl_adc1: adc1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
		>;
	};

	pinctrl_ecspi3: ecspi3grp {
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b010
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b010
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b010
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b010
		>;
	};

	pinctrl_flexcan1: flexcan1 {
		fsl,pins = <
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
		>;
	};

	princtrl_flexcan1_en: flexcan1engrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x17059
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO04__PWM3_OUT	0x0b0b0
		>;
	};

	pinctrl_rtc_int: rtcintgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
		>;
	};

	pinctrl_stmpe: stmpegrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x17059
		>;
	};

	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
		>;
	};

	pinctrl_usb_otg1_id: usbotg1idgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
		>;
	};
};