1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
|
/*
* Copyright (C) 2001 Deep Blue Solutions Ltd.
* Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*!
* @file mach-mx3/cpu.c
*
* @brief This file contains the CPU initialization code.
*
* @ingroup MSL_MX31
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/iram_alloc.h>
#include <mach/hardware.h>
#include <asm/hardware/cache-l2x0.h>
/*!
* CPU initialization. It is called by fixup_mxc_board()
*/
void __init mxc_cpu_init(void)
{
/* Setup Peripheral Port Remap register for AVIC */
asm("ldr r0, =0xC0000015 \n\
mcr p15, 0, r0, c15, c2, 4");
if (!system_rev) {
mxc_set_system_rev(0x31, CHIP_REV_2_0);
}
}
/*!
* Post CPU init code
*
* @return 0 always
*/
static int __init post_cpu_init(void)
{
volatile unsigned long aips_reg;
iram_init(MX31_IRAM_BASE_ADDR, MX31_IRAM_SIZE);
/*
* S/W workaround: Clear the off platform peripheral modules
* Supervisor Protect bit for SDMA to access them.
*/
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
aips_reg &= 0x00FFFFFF;
__raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
aips_reg &= 0x00FFFFFF;
__raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
return 0;
}
postcore_initcall(post_cpu_init);
|
