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/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include "board-mx35evb.h"
#include "iomux.h"
/*!
* @file mach-mx35/mx35evb_gpio.c
*
* @brief This file contains all the GPIO setup functions for the board.
*
* @ingroup GPIO_MX35
*/
/*!
* This system-wise GPIO function initializes the pins during system startup.
* All the statically linked device drivers should put the proper GPIO
* initialization code inside this function. It is called by \b fixup_mx31ads()
* during system startup. This function is board specific.
*/
void mx35evb_gpio_init(void)
{
/* config CS4 */
mxc_request_iomux(MX35_PIN_CS4, MUX_CONFIG_FUNC);
}
/*!
* Setup GPIO for a UART port to be active
*
* @param port a UART port
* @param no_irda indicates if the port is used for SIR
*/
void gpio_uart_active(int port, int no_irda)
{
/*
* Configure the IOMUX control registers for the UART signals
*/
switch (port) {
/* UART 1 IOMUX Configs */
case 0:
mxc_request_iomux(MX35_PIN_RXD1, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_TXD1, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_RTS1, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_CTS1, MUX_CONFIG_FUNC);
mxc_iomux_set_pad(MX35_PIN_RXD1,
PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX35_PIN_TXD1,
PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_RTS1,
PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX35_PIN_CTS1,
PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
break;
/* UART 2 IOMUX Configs */
case 1:
mxc_request_iomux(MX35_PIN_TXD2, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_RXD2, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_FUNC);
mxc_iomux_set_pad(MX35_PIN_RXD2,
PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX35_PIN_TXD2,
PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
mxc_iomux_set_pad(MX35_PIN_RTS2,
PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX35_PIN_CTS2,
PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
break;
/* UART 3 IOMUX Configs */
case 2:
mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_ALT2);
mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_ALT2);
mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_ALT2);
mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_ALT2);
mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH2);
mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH3);
break;
default:
break;
}
}
EXPORT_SYMBOL(gpio_uart_active);
/*!
* Setup GPIO for a UART port to be inactive
*
* @param port a UART port
* @param no_irda indicates if the port is used for SIR
*/
void gpio_uart_inactive(int port, int no_irda)
{
switch (port) {
case 0:
gpio_request(IOMUX_TO_GPIO(MX35_PIN_RXD1), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_TXD1), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_RTS1), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_CTS1), NULL);
mxc_free_iomux(MX35_PIN_RXD1, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_TXD1, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_RTS1, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_CTS1, MUX_CONFIG_GPIO);
break;
case 1:
gpio_request(IOMUX_TO_GPIO(MX35_PIN_RXD2), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_TXD2), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_RTS2), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_CTS2), NULL);
mxc_free_iomux(MX35_PIN_RXD2, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_TXD2, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_RTS2, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_CTS2, MUX_CONFIG_GPIO);
break;
case 2:
gpio_request(IOMUX_TO_GPIO(MX35_PIN_FEC_TX_CLK), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_FEC_RX_CLK), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_FEC_COL), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_FEC_RX_DV), NULL);
mxc_free_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_GPIO);
mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH0);
mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH0);
break;
default:
break;
}
}
EXPORT_SYMBOL(gpio_uart_inactive);
/*!
* Configure the IOMUX GPR register to receive shared SDMA UART events
*
* @param port a UART port
*/
void config_uartdma_event(int port)
{
}
EXPORT_SYMBOL(config_uartdma_event);
void gpio_fec_active(void)
{
/*TODO:require the pins related with FEC */
}
EXPORT_SYMBOL(gpio_fec_active);
void gpio_fec_inactive(void)
{
/*TODO:release the pins related with FEC */
}
EXPORT_SYMBOL(gpio_fec_inactive);
/*!
* Setup GPIO for a CSPI device to be active
*
* @param cspi_mod an CSPI device
*/
void gpio_spi_active(int cspi_mod)
{
switch (cspi_mod) {
case 0:
/* SPI1 */
mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_CSPI1_SPI_RDY, MUX_CONFIG_FUNC);
mxc_iomux_set_pad(MX35_PIN_CSPI1_MOSI,
PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD |
PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL);
mxc_iomux_set_pad(MX35_PIN_CSPI1_MISO,
PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD |
PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL);
mxc_iomux_set_pad(MX35_PIN_CSPI1_SS0,
PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD |
PAD_CTL_100K_PU | PAD_CTL_ODE_CMOS |
PAD_CTL_DRV_NORMAL);
mxc_iomux_set_pad(MX35_PIN_CSPI1_SS1,
PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD |
PAD_CTL_100K_PU | PAD_CTL_ODE_CMOS |
PAD_CTL_DRV_NORMAL);
mxc_iomux_set_pad(MX35_PIN_CSPI1_SCLK,
PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD |
PAD_CTL_100K_PD | PAD_CTL_DRV_NORMAL);
mxc_iomux_set_pad(MX35_PIN_CSPI1_SPI_RDY,
PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD |
PAD_CTL_100K_PU | PAD_CTL_DRV_NORMAL);
break;
case 1:
/* SPI2 */
break;
default:
break;
}
}
EXPORT_SYMBOL(gpio_spi_active);
/*!
* Setup GPIO for a CSPI device to be inactive
*
* @param cspi_mod a CSPI device
*/
void gpio_spi_inactive(int cspi_mod)
{
switch (cspi_mod) {
case 0:
/* SPI1 */
gpio_request(IOMUX_TO_GPIO(MX35_PIN_CSPI1_MOSI), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_CSPI1_MISO), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_CSPI1_SS0), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_CSPI1_SS1), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_CSPI1_SCLK), NULL);
gpio_request(IOMUX_TO_GPIO(MX35_PIN_CSPI1_SPI_RDY), NULL);
mxc_free_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_GPIO);
mxc_free_iomux(MX35_PIN_CSPI1_SPI_RDY, MUX_CONFIG_GPIO);
break;
case 1:
/* SPI2 */
break;
default:
break;
}
}
EXPORT_SYMBOL(gpio_spi_inactive);
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