1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
|
/*
* Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*!
* @file mach-mx37/serial.c
*
* @brief This file contains the UART initiliazation.
*
* @ingroup MSL_MX37
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <mach/hardware.h>
#include <mach/mxc_uart.h>
#include "serial.h"
#include "board-mx37_3stack.h"
#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE)
/*!
* This is an array where each element holds information about a UART port,
* like base address of the UART, interrupt numbers etc. This structure is
* passed to the serial_core.c file. Based on which UART is used, the core file
* passes back the appropriate port structure as an argument to the control
* functions.
*/
static uart_mxc_port mxc_ports[] = {
[0] = {
.port = {
.iotype = SERIAL_IO_MEM,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 0,
},
.ints_muxed = UART1_MUX_INTS,
.mode = UART1_MODE,
.ir_mode = UART1_IR,
.enabled = UART1_ENABLED,
.hardware_flow = UART1_HW_FLOW,
.cts_threshold = UART1_UCR4_CTSTL,
.dma_enabled = UART1_DMA_ENABLE,
.dma_rxbuf_size = UART1_DMA_RXBUFSIZE,
.rx_threshold = UART1_UFCR_RXTL,
.tx_threshold = UART1_UFCR_TXTL,
.dma_tx_id = MXC_DMA_UART1_TX,
.dma_rx_id = MXC_DMA_UART1_RX,
.rxd_mux = MXC_UART_RXDMUX,
},
[1] = {
.port = {
.iotype = SERIAL_IO_MEM,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 1,
},
.ints_muxed = UART2_MUX_INTS,
.mode = UART2_MODE,
.ir_mode = UART2_IR,
.enabled = UART2_ENABLED,
.hardware_flow = UART2_HW_FLOW,
.cts_threshold = UART2_UCR4_CTSTL,
.dma_enabled = UART2_DMA_ENABLE,
.dma_rxbuf_size = UART2_DMA_RXBUFSIZE,
.rx_threshold = UART2_UFCR_RXTL,
.tx_threshold = UART2_UFCR_TXTL,
.dma_tx_id = MXC_DMA_UART2_TX,
.dma_rx_id = MXC_DMA_UART2_RX,
.rxd_mux = MXC_UART_RXDMUX,
},
[2] = {
.port = {
.iotype = SERIAL_IO_MEM,
.fifosize = 32,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 2,
},
.ints_muxed = UART3_MUX_INTS,
.mode = UART3_MODE,
.ir_mode = UART3_IR,
.enabled = UART3_ENABLED,
.hardware_flow = UART3_HW_FLOW,
.cts_threshold = UART3_UCR4_CTSTL,
.dma_enabled = UART3_DMA_ENABLE,
.dma_rxbuf_size = UART3_DMA_RXBUFSIZE,
.rx_threshold = UART3_UFCR_RXTL,
.tx_threshold = UART3_UFCR_TXTL,
.dma_tx_id = MXC_DMA_UART3_TX,
.dma_rx_id = MXC_DMA_UART3_RX,
.rxd_mux = MXC_UART_RXDMUX,
},
};
static struct resource mxc_uart_resources1[] = {
{
.start = UART1_BASE_ADDR,
.end = UART1_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM,
},
{
.start = UART1_INT1,
.flags = IORESOURCE_IRQ,
},
{
.start = UART1_INT2,
.flags = IORESOURCE_IRQ,
},
{
.start = UART1_INT3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mxc_uart_device1 = {
.name = "mxcintuart",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_uart_resources1),
.resource = mxc_uart_resources1,
.dev = {
.platform_data = &mxc_ports[0],
},
};
static struct resource mxc_uart_resources2[] = {
{
.start = UART2_BASE_ADDR,
.end = UART2_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM,
},
{
.start = UART2_INT1,
.flags = IORESOURCE_IRQ,
},
{
.start = UART2_INT2,
.flags = IORESOURCE_IRQ,
},
{
.start = UART2_INT3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mxc_uart_device2 = {
.name = "mxcintuart",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_uart_resources2),
.resource = mxc_uart_resources2,
.dev = {
.platform_data = &mxc_ports[1],
},
};
static struct resource mxc_uart_resources3[] = {
{
.start = UART3_BASE_ADDR,
.end = UART3_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM,
},
{
.start = UART3_INT1,
.flags = IORESOURCE_IRQ,
},
{
.start = UART3_INT2,
.flags = IORESOURCE_IRQ,
},
{
.start = UART3_INT3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mxc_uart_device3 = {
.name = "mxcintuart",
.id = 2,
.num_resources = ARRAY_SIZE(mxc_uart_resources3),
.resource = mxc_uart_resources3,
.dev = {
.platform_data = &mxc_ports[2],
},
};
static int __init mxc_init_uart(void)
{
/* Register all the MXC UART platform device structures */
platform_device_register(&mxc_uart_device1);
platform_device_register(&mxc_uart_device2);
#if UART3_ENABLED == 1
platform_device_register(&mxc_uart_device3);
#endif /* UART3_ENABLED */
return 0;
}
#else
static int __init mxc_init_uart(void)
{
return 0;
}
#endif
arch_initcall(mxc_init_uart);
|
