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|
#undef MX6PAD
#undef MX6NAME
#undef MX6
#ifdef FOR_DL_SOLO
#define MX6(a) MX6DL_##a
#define MX6PAD(a) MX6DL_PAD_##a
#define MX6NAME(a) mx6dl_solo_##a
#else
#define MX6(a) MX6Q_##a
#define MX6PAD(a) MX6Q_PAD_##a
#define MX6NAME(a) mx6q_##a
#endif
#define WEAK_PULLUP (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm)
#define WEAK_PULLDN (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm)
#define ISL1208_IRQ_PADCFG (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
#define N6_IRQ_PADCFG (PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define N6_EN_PADCFG (PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
#define PAD_CTL_PIS(pull, impede, speed) (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_##pull | PAD_CTL_SPEED_##speed | \
PAD_CTL_DSE_##impede | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define MX6Q_USDHC_PAD_CTRL_22KPU_34OHM_50MHZ PAD_CTL_PIS(22K_UP, 34ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ PAD_CTL_PIS(22K_UP, 40ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_22KPU_48OHM_50MHZ PAD_CTL_PIS(22K_UP, 48ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_22KPU_60OHM_50MHZ PAD_CTL_PIS(22K_UP, 60ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_22KPU_80OHM_50MHZ PAD_CTL_PIS(22K_UP, 80ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_22KPU_120OHM_50MHZ PAD_CTL_PIS(22K_UP, 120ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_47KPU_34OHM_50MHZ PAD_CTL_PIS(47K_UP, 34ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_47KPU_40OHM_50MHZ PAD_CTL_PIS(47K_UP, 40ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_47KPU_48OHM_50MHZ PAD_CTL_PIS(47K_UP, 48ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_47KPU_60OHM_50MHZ PAD_CTL_PIS(47K_UP, 60ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_47KPU_80OHM_50MHZ PAD_CTL_PIS(47K_UP, 80ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_47KPU_120OHM_50MHZ PAD_CTL_PIS(47K_UP, 120ohm, LOW)
#define MX6Q_USDHC_PAD_CTRL_50MHZ MX6Q_USDHC_PAD_CTRL
#define MX6DL_USDHC_PAD_CTRL_22KPU_34OHM_50MHZ PAD_CTL_PIS(22K_UP, 34ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ PAD_CTL_PIS(22K_UP, 40ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_22KPU_48OHM_50MHZ PAD_CTL_PIS(22K_UP, 48ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_22KPU_60OHM_50MHZ PAD_CTL_PIS(22K_UP, 60ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_22KPU_80OHM_50MHZ PAD_CTL_PIS(22K_UP, 80ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_22KPU_120OHM_50MHZ PAD_CTL_PIS(22K_UP, 120ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_47KPU_34OHM_50MHZ PAD_CTL_PIS(47K_UP, 34ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_47KPU_40OHM_50MHZ PAD_CTL_PIS(47K_UP, 40ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_47KPU_48OHM_50MHZ PAD_CTL_PIS(47K_UP, 48ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_47KPU_60OHM_50MHZ PAD_CTL_PIS(47K_UP, 60ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_47KPU_80OHM_50MHZ PAD_CTL_PIS(47K_UP, 80ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_47KPU_120OHM_50MHZ PAD_CTL_PIS(47K_UP, 120ohm, LOW)
#define MX6DL_USDHC_PAD_CTRL_50MHZ MX6DL_USDHC_PAD_CTRL
#define MX6Q_PAD_SD3_CLK__USDHC3_CLK MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ
#define MX6Q_PAD_SD3_CMD__USDHC3_CMD MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ
#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
#define MX6Q_PAD_SD4_CLK__USDHC4_CLK MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ
#define MX6Q_PAD_SD4_CMD__USDHC4_CMD MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ
#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ
#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ
#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ
#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ
#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ
#define MX6DL_PAD_SD3_CLK__USDHC3_CLK MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ
#define MX6DL_PAD_SD3_CMD__USDHC3_CMD MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ
#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
#define MX6DL_PAD_SD4_CLK__USDHC4_CLK MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ
#define MX6DL_PAD_SD4_CMD__USDHC4_CMD MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ
#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ
#define MX6DL_PAD_SD4_DAT4__USDHC4_DAT4 MX6DL_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ
#define MX6DL_PAD_SD4_DAT5__USDHC4_DAT5 MX6DL_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ
#define MX6DL_PAD_SD4_DAT6__USDHC4_DAT6 MX6DL_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ
#define MX6DL_PAD_SD4_DAT7__USDHC4_DAT7 MX6DL_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ
#define NP(id, pin, pad_ctl) \
NEW_PAD_CTRL(MX6PAD(SD##id##_##pin##__USDHC##id##_##pin), MX6(pad_ctl))
#define SD_PINS(id, pad_ctl) \
NP(id, CLK, pad_ctl), \
NP(id, CMD, pad_ctl), \
NP(id, DAT0, pad_ctl), \
NP(id, DAT1, pad_ctl), \
NP(id, DAT2, pad_ctl), \
NP(id, DAT3, pad_ctl)
#define SD_PINS8(id, pad_ctl) \
SD_PINS(id, pad_ctl), \
NP(id, DAT4, pad_ctl), \
NP(id, DAT5, pad_ctl), \
NP(id, DAT6, pad_ctl), \
NP(id, DAT7, pad_ctl)
static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
/* CCM */
MX6PAD(CSI0_MCLK__CCM_CLKO), /* MIPI camera mclk */
/* ECSPI1 */
MX6PAD(EIM_D17__ECSPI1_MISO),
MX6PAD(EIM_D18__ECSPI1_MOSI),
MX6PAD(EIM_D16__ECSPI1_SCLK),
MX6PAD(EIM_D19__GPIO_3_19), /*SS1*/
/* ECSPI2 */
MX6PAD(CSI0_DAT10__ECSPI2_MISO),
MX6PAD(CSI0_DAT9__ECSPI2_MOSI),
MX6PAD(CSI0_DAT8__ECSPI2_SCLK),
MX6PAD(CSI0_DAT11__GPIO_5_29), /*SS0*/
/* GPIO_KEYS - J4 */
NEW_PAD_CTRL(MX6PAD(EIM_DA0__GPIO_3_0), WEAK_PULLUP), /* pin 1 - back */
NEW_PAD_CTRL(MX6PAD(EIM_DA1__GPIO_3_1), WEAK_PULLUP), /* pin 2 - up */
NEW_PAD_CTRL(MX6PAD(EIM_DA2__GPIO_3_2), WEAK_PULLUP), /* pin 3 - Menu */
NEW_PAD_CTRL(MX6PAD(EIM_DA3__GPIO_3_3), WEAK_PULLUP), /* pin 4 - Left */
NEW_PAD_CTRL(MX6PAD(GPIO_18__GPIO_7_13), WEAK_PULLUP), /* pin 5 - right */
NEW_PAD_CTRL(MX6PAD(GPIO_19__GPIO_4_5), WEAK_PULLUP), /* pin 6 - down */
NEW_PAD_CTRL(MX6PAD(KEY_COL2__GPIO_4_10), WEAK_PULLUP), /* pin 7 - NC */
NEW_PAD_CTRL(MX6PAD(KEY_ROW2__GPIO_4_11), WEAK_PULLUP), /* pin 8 - NC */
NEW_PAD_CTRL(MX6PAD(SD3_DAT4__GPIO_7_1), WEAK_PULLDN), /* pin 9 inverted, Main power off request */
NEW_PAD_CTRL(MX6PAD(NANDF_CS0__GPIO_6_11), WEAK_PULLUP), /* pin 10 - NC */
NEW_PAD_CTRL(MX6PAD(SD1_DAT1__GPIO_1_17), WEAK_PULLUP), /* pin 11 - NC */
/* PWM4: Audio buzzer*/
MX6PAD(SD1_CMD__PWM4_PWMO), /* GPIO1[18] */
/* GPIO1 */
MX6PAD(SD1_DAT0__GPIO_1_16), /* Main power enable */
/* GPIO2 */
MX6PAD(NANDF_D1__GPIO_2_1), /* Power 5.4V enable */
MX6PAD(NANDF_D2__GPIO_2_2), /* DC_STAT, low DC, High battery */
MX6PAD(NANDF_D7__GPIO_2_7), /* J3 - GP */
MX6PAD(EIM_RW__GPIO_2_26), /* J6 - GP */
/* GPIO3 */
NEW_PAD_CTRL(MX6PAD(EIM_DA4__GPIO_3_4), WEAK_PULLUP), /* FXAS21000, int2 */
NEW_PAD_CTRL(MX6PAD(EIM_DA5__GPIO_3_5), WEAK_PULLUP), /* FXAS21000, int1 */
MX6PAD(EIM_D20__GPIO_3_20), /* J6 - GP */
MX6PAD(EIM_D29__GPIO_3_29), /* J6 - GP */
/* GPIO6 */
NEW_PAD_CTRL(MX6PAD(NANDF_CLE__GPIO_6_7), ISL1208_IRQ_PADCFG), /* RTC ISL1208 irq*/
/* I2C1, SGTL5000 */
MX6PAD(EIM_D21__I2C1_SCL), /* GPIO3[21] */
MX6PAD(EIM_D28__I2C1_SDA), /* GPIO3[28] */
/* I2C2 Camera, MIPI */
MX6PAD(KEY_COL3__I2C2_SCL), /* GPIO4[12] */
MX6PAD(KEY_ROW3__I2C2_SDA), /* GPIO4[13] */
NEW_PAD_CTRL(MX6PAD(GPIO_9__GPIO_1_9), WEAK_PULLUP), /* I2C Touch IRQ */
MX6PAD(NANDF_D3__GPIO_2_3), /* Touch wake */
MX6PAD(NANDF_D4__GPIO_2_4), /* Touch reset */
/* I2C3 */
MX6PAD(GPIO_5__I2C3_SCL), /* GPIO1[5] - J7 - Display card */
MX6PAD(GPIO_16__I2C3_SDA), /* GPIO7[11] - J15 - RGB connector */
/* PWM1 */
MX6PAD(SD1_DAT3__PWM1_PWMO), /* GPIO1[21] */
/* PWM2 */
MX6PAD(SD1_DAT2__PWM2_PWMO), /* GPIO1[19] */
/* UART1 */
MX6PAD(SD3_DAT7__UART1_TXD),
MX6PAD(SD3_DAT6__UART1_RXD),
/* UART2 for debug */
MX6PAD(EIM_D26__UART2_TXD),
MX6PAD(EIM_D27__UART2_RXD),
/* UART3 for wl1271 */
MX6PAD(EIM_D24__UART3_TXD),
MX6PAD(EIM_D25__UART3_RXD),
MX6PAD(EIM_D23__UART3_CTS),
MX6PAD(EIM_D31__UART3_RTS),
/* USB H1 */
MX6PAD(EIM_D30__USBOH3_USBH1_OC),
/* USBOTG ID pin */
MX6PAD(GPIO_1__USBOTG_ID),
MX6PAD(KEY_COL4__USBOH3_USBOTG_OC),
NEW_PAD_CTRL(MX6PAD(EIM_D22__GPIO_3_22), WEAK_PULLUP),
/* USDHC2 (WiFi) */
SD_PINS(2, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ),
MX6PAD(SD1_CLK__OSC32K_32K_OUT), /* wl1271 clock */
NEW_PAD_CTRL(MX6PAD(NANDF_CS1__GPIO_6_14), N6_IRQ_PADCFG), /* wl1271 wl_irq */
NEW_PAD_CTRL(MX6PAD(NANDF_CS2__GPIO_6_15), N6_EN_PADCFG), /* wl1271 wl_en */
NEW_PAD_CTRL(MX6PAD(NANDF_CS3__GPIO_6_16), N6_EN_PADCFG), /* wl1271 bt_en */
/* USDHC3 */
SD_PINS(3, USDHC_PAD_CTRL_50MHZ),
MX6PAD(SD3_DAT5__GPIO_7_0), /* SD3_CD */
/* USDHC4 (eMMC) */
SD_PINS8(4, USDHC_PAD_CTRL_50MHZ),
MX6PAD(EIM_CS0__GPIO_2_23), /* eMMC reset */
0
};
static iomux_v3_cfg_t MX6NAME(lcd_pads_enable)[] = {
MX6PAD(DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
MX6PAD(DI0_PIN15__IPU1_DI0_PIN15), /* DE */
MX6PAD(DI0_PIN2__IPU1_DI0_PIN2), /* HSync */
MX6PAD(DI0_PIN3__IPU1_DI0_PIN3), /* VSync */
MX6PAD(DISP0_DAT0__IPU1_DISP0_DAT_0),
MX6PAD(DISP0_DAT1__IPU1_DISP0_DAT_1),
MX6PAD(DISP0_DAT2__IPU1_DISP0_DAT_2),
MX6PAD(DISP0_DAT3__IPU1_DISP0_DAT_3),
MX6PAD(DISP0_DAT4__IPU1_DISP0_DAT_4),
MX6PAD(DISP0_DAT5__IPU1_DISP0_DAT_5),
MX6PAD(DISP0_DAT6__IPU1_DISP0_DAT_6),
MX6PAD(DISP0_DAT7__IPU1_DISP0_DAT_7),
MX6PAD(DISP0_DAT8__IPU1_DISP0_DAT_8),
MX6PAD(DISP0_DAT9__IPU1_DISP0_DAT_9),
MX6PAD(DISP0_DAT10__IPU1_DISP0_DAT_10),
MX6PAD(DISP0_DAT11__IPU1_DISP0_DAT_11),
MX6PAD(DISP0_DAT12__IPU1_DISP0_DAT_12),
MX6PAD(DISP0_DAT13__IPU1_DISP0_DAT_13),
MX6PAD(DISP0_DAT14__IPU1_DISP0_DAT_14),
MX6PAD(DISP0_DAT15__IPU1_DISP0_DAT_15),
MX6PAD(DISP0_DAT16__IPU1_DISP0_DAT_16),
MX6PAD(DISP0_DAT17__IPU1_DISP0_DAT_17),
MX6PAD(DISP0_DAT18__IPU1_DISP0_DAT_18),
MX6PAD(DISP0_DAT19__IPU1_DISP0_DAT_19),
MX6PAD(DISP0_DAT20__IPU1_DISP0_DAT_20),
MX6PAD(DISP0_DAT21__IPU1_DISP0_DAT_21),
MX6PAD(DISP0_DAT22__IPU1_DISP0_DAT_22),
MX6PAD(DISP0_DAT23__IPU1_DISP0_DAT_23),
0
};
static iomux_v3_cfg_t MX6NAME(lcd_pads_disable)[] = {
MX6PAD(DI0_DISP_CLK__GPIO_4_16),
MX6PAD(DI0_PIN15__GPIO_4_17), /* DE */
MX6PAD(DI0_PIN2__GPIO_4_18), /* HSync */
MX6PAD(DI0_PIN3__GPIO_4_19), /* VSync */
MX6PAD(DISP0_DAT0__GPIO_4_21),
MX6PAD(DISP0_DAT1__GPIO_4_22),
MX6PAD(DISP0_DAT2__GPIO_4_23),
MX6PAD(DISP0_DAT3__GPIO_4_24),
MX6PAD(DISP0_DAT4__GPIO_4_25),
MX6PAD(DISP0_DAT5__GPIO_4_26),
MX6PAD(DISP0_DAT6__GPIO_4_27),
MX6PAD(DISP0_DAT7__GPIO_4_28),
MX6PAD(DISP0_DAT8__GPIO_4_29),
MX6PAD(DISP0_DAT9__GPIO_4_30),
MX6PAD(DISP0_DAT10__GPIO_4_31),
MX6PAD(DISP0_DAT11__GPIO_5_5),
MX6PAD(DISP0_DAT12__GPIO_5_6),
MX6PAD(DISP0_DAT13__GPIO_5_7),
MX6PAD(DISP0_DAT14__GPIO_5_8),
MX6PAD(DISP0_DAT15__GPIO_5_9),
MX6PAD(DISP0_DAT16__GPIO_5_10),
MX6PAD(DISP0_DAT17__GPIO_5_11),
MX6PAD(DISP0_DAT18__GPIO_5_12),
MX6PAD(DISP0_DAT19__GPIO_5_13),
MX6PAD(DISP0_DAT20__GPIO_5_14),
MX6PAD(DISP0_DAT21__GPIO_5_15),
MX6PAD(DISP0_DAT22__GPIO_5_16),
MX6PAD(DISP0_DAT23__GPIO_5_17),
0
};
static iomux_v3_cfg_t MX6NAME(mipi_pads)[] = {
MX6PAD(CSI0_DATA_EN__GPIO_5_20), /* Mipi Camera Reset */
MX6PAD(CSI0_VSYNC__GPIO_5_21), /* Mipi Powerdown */
0
};
static iomux_v3_cfg_t MX6NAME(hdmi_ddc_pads)[] = {
MX6PAD(KEY_COL3__HDMI_TX_DDC_SCL), /* HDMI DDC SCL */
MX6PAD(KEY_ROW3__HDMI_TX_DDC_SDA), /* HDMI DDC SDA */
0
};
static iomux_v3_cfg_t MX6NAME(i2c2_pads)[] = {
MX6PAD(KEY_COL3__I2C2_SCL), /* I2C2 SCL */
MX6PAD(KEY_ROW3__I2C2_SDA), /* I2C2 SDA */
0
};
#define MX6_USDHC_PAD_SETTING(id, speed, pad_ctl) \
MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS(id, pad_ctl), 0 }
#define MX6_USDHC_PAD_SETTING8(id, speed, pad_ctl) \
MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS8(id, pad_ctl), 0 }
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 50, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 100, USDHC_PAD_CTRL_100MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 200, USDHC_PAD_CTRL_200MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 50, USDHC_PAD_CTRL_50MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 100, USDHC_PAD_CTRL_100MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 200, USDHC_PAD_CTRL_200MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING8(4, 50, USDHC_PAD_CTRL_50MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING8(4, 100, USDHC_PAD_CTRL_100MHZ);
static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING8(4, 200, USDHC_PAD_CTRL_200MHZ);
#define _50MHZ 0
#define _100MHZ 1
#define _200MHZ 2
#define SD_SPEED_CNT 3
static iomux_v3_cfg_t * MX6NAME(sd_pads)[] =
{
MX6NAME(sd2_50mhz),
MX6NAME(sd2_100mhz),
MX6NAME(sd2_200mhz),
MX6NAME(sd3_50mhz),
MX6NAME(sd3_100mhz),
MX6NAME(sd3_200mhz),
MX6NAME(sd4_50mhz),
MX6NAME(sd4_100mhz),
MX6NAME(sd4_200mhz),
};
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