1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
|
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <mach/arc_otg.h>
#include <mach/hardware.h>
#include "devices-imx6q.h"
#include "regs-anadig.h"
#include "usb.h"
static struct clk *usb_oh3_clk;
extern int clk_get_usecount(struct clk *clk);
static struct fsl_usb2_platform_data usbh1_config;
static void usbh1_internal_phy_clock_gate(bool on)
{
void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY1_BASE_ADDR);
if (on) {
__raw_writel(BM_USBPHY_CTRL_CLKGATE, phy_reg + HW_USBPHY_CTRL_CLR);
} else {
__raw_writel(BM_USBPHY_CTRL_CLKGATE, phy_reg + HW_USBPHY_CTRL_SET);
}
}
static int usb_phy_enable(struct fsl_usb2_platform_data *pdata)
{
u32 tmp;
void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY1_BASE_ADDR);
void __iomem *phy_ctrl;
/* Stop then Reset */
UH1_USBCMD &= ~UCMD_RUN_STOP;
while (UH1_USBCMD & UCMD_RUN_STOP)
;
UH1_USBCMD |= UCMD_RESET;
while ((UH1_USBCMD) & (UCMD_RESET))
;
/* Reset USBPHY module */
phy_ctrl = phy_reg + HW_USBPHY_CTRL;
tmp = __raw_readl(phy_ctrl);
tmp |= BM_USBPHY_CTRL_SFTRST;
__raw_writel(tmp, phy_ctrl);
udelay(10);
/* Remove CLKGATE and SFTRST */
tmp = __raw_readl(phy_ctrl);
tmp &= ~(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST);
__raw_writel(tmp, phy_ctrl);
udelay(10);
/* Power up the PHY */
__raw_writel(0, phy_reg + HW_USBPHY_PWD);
/* enable FS/LS device */
tmp = __raw_readl(phy_reg + HW_USBPHY_CTRL);
tmp |= (BM_USBPHY_CTRL_ENUTMILEVEL2 | BM_USBPHY_CTRL_ENUTMILEVEL3);
__raw_writel(tmp, phy_reg + HW_USBPHY_CTRL);
return 0;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret;
struct clk *usb_clk;
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
return ret;
}
usbh1_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
return 0;
}
static void fsl_usb_host_uninit_ext(struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
fsl_usb_host_uninit(pdata);
clk_disable(usb_oh3_clk);
clk_put(usb_oh3_clk);
}
static void usbh1_clock_gate(bool on)
{
pr_debug("%s: on is %d\n", __func__, on);
if (on) {
clk_enable(usb_oh3_clk);
} else {
clk_disable(usb_oh3_clk);
}
}
void mx6_set_host1_vbus_func(driver_vbus_func driver_vbus)
{
usbh1_config.platform_driver_vbus = driver_vbus;
}
static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable)
{
void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY1_BASE_ADDR);
pr_debug("host1, %s, enable is %d\n", __func__, enable);
if (enable) {
__raw_writel(BM_USBPHY_CTRL_ENIDCHG_WKUP | BM_USBPHY_CTRL_ENVBUSCHG_WKUP
| BM_USBPHY_CTRL_ENDPDMCHG_WKUP
| BM_USBPHY_CTRL_ENAUTOSET_USBCLKS
| BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD
| BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE
| BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE
| BM_USBPHY_CTRL_ENAUTO_PWRON_PLL , phy_reg + HW_USBPHY_CTRL_SET);
USB_H1_CTRL |= (UCTRL_OWIE);
} else {
USB_H1_CTRL &= ~(UCTRL_OWIE);
/* The interrupt must be disabled for at least 3
* cycles of the standby clock(32k Hz) , that is 0.094 ms*/
udelay(100);
}
}
static void usbh1_platform_suspend(struct fsl_usb2_platform_data *pdata)
{
void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY1_BASE_ADDR);
u32 tmp;
tmp = (BM_USBPHY_PWD_TXPWDFS
| BM_USBPHY_PWD_TXPWDIBIAS
| BM_USBPHY_PWD_TXPWDV2I
| BM_USBPHY_PWD_RXPWDENV
| BM_USBPHY_PWD_RXPWD1PT1
| BM_USBPHY_PWD_RXPWDDIFF
| BM_USBPHY_PWD_RXPWDRX);
__raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET);
}
static void usbh1_platform_resume(struct fsl_usb2_platform_data *pdata)
{
void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY1_BASE_ADDR);
u32 tmp;
tmp = (BM_USBPHY_PWD_TXPWDFS
| BM_USBPHY_PWD_TXPWDIBIAS
| BM_USBPHY_PWD_TXPWDV2I
| BM_USBPHY_PWD_RXPWDENV
| BM_USBPHY_PWD_RXPWD1PT1
| BM_USBPHY_PWD_RXPWDDIFF
| BM_USBPHY_PWD_RXPWDRX);
__raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR);
}
static void _phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
{
u32 tmp;
void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY1_BASE_ADDR);
pr_debug("host1, %s, enable is %d\n", __func__, enable);
if (enable) {
UH1_PORTSC1 |= PORTSC_PHCD;
pr_debug("%s, Poweroff UTMI \n", __func__);
tmp = (BM_USBPHY_PWD_TXPWDFS
| BM_USBPHY_PWD_TXPWDIBIAS
| BM_USBPHY_PWD_TXPWDV2I
| BM_USBPHY_PWD_RXPWDENV
| BM_USBPHY_PWD_RXPWD1PT1
| BM_USBPHY_PWD_RXPWDDIFF
| BM_USBPHY_PWD_RXPWDRX);
__raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET);
usbh1_internal_phy_clock_gate(false);
} else {
if (UH1_PORTSC1 & PORTSC_PHCD) {
UH1_PORTSC1 &= ~PORTSC_PHCD;
mdelay(1);
}
usbh1_internal_phy_clock_gate(true);
tmp = (BM_USBPHY_PWD_TXPWDFS
| BM_USBPHY_PWD_TXPWDIBIAS
| BM_USBPHY_PWD_TXPWDV2I
| BM_USBPHY_PWD_RXPWDENV
| BM_USBPHY_PWD_RXPWD1PT1
| BM_USBPHY_PWD_RXPWDDIFF
| BM_USBPHY_PWD_RXPWDRX);
__raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR);
}
}
static enum usb_wakeup_event _is_usbh1_wakeup(struct fsl_usb2_platform_data *pdata)
{
u32 wakeup_req = USB_H1_CTRL & UCTRL_OWIR;
if (wakeup_req)
return !WAKEUP_EVENT_INVALID;
pr_err("host1, %s, invalid wake up\n", __func__);
return WAKEUP_EVENT_INVALID;
}
static void h1_wakeup_handler(struct fsl_usb2_platform_data *pdata)
{
_wake_up_enable(pdata, false);
_phy_lowpower_suspend(pdata, false);
pdata->wakeup_event = 1;
}
static void usbh1_wakeup_event_clear(void)
{
void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY1_BASE_ADDR);
u32 wakeup_irq_bits;
wakeup_irq_bits = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ;
if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && wakeup_irq_bits) {
/* clear the wakeup interrupt status */
__raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR);
}
}
static struct fsl_usb2_platform_data usbh1_config = {
.name = "Host 1",
.init = fsl_usb_host_init_ext,
.exit = fsl_usb_host_uninit_ext,
.operating_mode = FSL_USB2_MPH_HOST,
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
.power_budget = 500, /* 500 mA max power */
.wake_up_enable = _wake_up_enable,
.usb_clock_for_pm = usbh1_clock_gate,
.platform_suspend = usbh1_platform_suspend,
.platform_resume = usbh1_platform_resume,
.phy_lowpower_suspend = _phy_lowpower_suspend,
.is_wakeup_event = _is_usbh1_wakeup,
.wakeup_handler = h1_wakeup_handler,
.transceiver = "utmi",
.phy_regs = USB_PHY1_BASE_ADDR,
};
static struct fsl_usb2_wakeup_platform_data usbh1_wakeup_config = {
.name = "USBH1 wakeup",
.usb_clock_for_pm = usbh1_clock_gate,
.usb_pdata = {&usbh1_config, NULL, NULL},
.usb_wakeup_exhandle = usbh1_wakeup_event_clear,
};
void __init mx6_usb_h1_init(void)
{
struct platform_device *pdev, *pdev_wakeup;
static void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
usbh1_config.wakeup_pdata = &usbh1_wakeup_config;
pdev = imx6q_add_fsl_ehci_hs(1, &usbh1_config);
usbh1_wakeup_config.usb_pdata[0] = pdev->dev.platform_data;
pdev_wakeup = imx6q_add_fsl_usb2_hs_wakeup(1, &usbh1_wakeup_config);
((struct fsl_usb2_platform_data *)(pdev->dev.platform_data))->wakeup_pdata =
(struct fsl_usb2_wakeup_platform_data *)(pdev_wakeup->dev.platform_data);
/* Some phy and power's special controls for host1
* 1. The external charger detector needs to be disabled
* or the signal at DP will be poor
* 2. The PLL's power and output to usb for host 1
* is totally controlled by IC, so the Software only needs
* to enable them at initializtion.
*/
__raw_writel(BM_ANADIG_USB2_CHRG_DETECT_EN_B \
| BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, \
anatop_base_addr + HW_ANADIG_USB2_CHRG_DETECT);
__raw_writel(BM_ANADIG_USB2_PLL_480_CTRL_BYPASS,
anatop_base_addr + HW_ANADIG_USB2_PLL_480_CTRL_CLR);
__raw_writel(BM_ANADIG_USB2_PLL_480_CTRL_ENABLE \
| BM_ANADIG_USB2_PLL_480_CTRL_POWER \
| BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, \
anatop_base_addr + HW_ANADIG_USB2_PLL_480_CTRL_SET);
}
|
