1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
|
/*
* arch/arm/mach-tegra/pci.c
*
* PCIe host controller driver for TEGRA(2) SOCs
*
* Copyright (c) 2008-2009, NVIDIA Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <asm/mach/pci.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
static int __init pcie_tegra_init(void);
static void __init pci_tegra_preinit(void);
static int __init pci_tegra_setup(int nr, struct pci_sys_data *data);
static struct pci_bus __init *pci_tegra_scan_bus(int nr,
struct pci_sys_data *sys);
static int pci_tegra_read_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 *val);
static int pci_tegra_read_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 *val);
static int __init pcie_tegra_init(void);
unsigned long pci_tegra_get_base(char *aperture)
{
if (!strcmp(aperture, "mem"))
return 0x90000000;
else if (!strcmp(aperture, "io"))
return 0x82000000;
else
return (unsigned long)-1;
}
static int pci_tegra_read_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 *val)
{
int i;
for (i=0; i<size; i++)
((__u8 *)val)[i] = 0xff;
return PCIBIOS_SUCCESSFUL;
}
static int pci_tegra_write_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops pci_tegra_ops = {
.read = pci_tegra_read_conf,
.write = pci_tegra_write_conf,
};
static void __init pci_tegra_preinit(void)
{
}
static int __init pci_tegra_setup(int nr, struct pci_sys_data *data)
{
return (nr == 0);
}
static struct pci_bus __init *pci_tegra_scan_bus(int nr,
struct pci_sys_data *sys)
{
if (nr == 0)
return pci_scan_bus(sys->busnr, &pci_tegra_ops, sys);
return NULL;
}
static struct hw_pci pci_tegra_data __initdata = {
.nr_controllers = 2,
.preinit = pci_tegra_preinit,
.setup = pci_tegra_setup,
.scan = pci_tegra_scan_bus,
.swizzle = pci_std_swizzle,
};
late_initcall(pcie_tegra_init);
static int __init pcie_tegra_init(void)
{
pci_common_init(&pci_tegra_data);
return 0;
}
|
