1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
|
/*
* arch/arm/mach-tegra/include/mach/pm.h
*
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010-2011 NVIDIA Corporation
*
* Author:
* Colin Cross <ccross@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _MACH_TEGRA_PM_H_
#define _MACH_TEGRA_PM_H_
#include <linux/mutex.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/clkdev.h>
#include <mach/iomap.h>
enum tegra_suspend_mode {
TEGRA_SUSPEND_NONE = 0,
TEGRA_SUSPEND_LP2, /* CPU voltage off */
TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
TEGRA_MAX_SUSPEND_MODE,
};
enum suspend_stage {
TEGRA_SUSPEND_BEFORE_PERIPHERAL,
TEGRA_SUSPEND_BEFORE_CPU,
};
enum resume_stage {
TEGRA_RESUME_AFTER_PERIPHERAL,
TEGRA_RESUME_AFTER_CPU,
};
struct tegra_suspend_platform_data {
unsigned long cpu_timer; /* CPU power good time in us, LP2/LP1 */
unsigned long cpu_off_timer; /* CPU power off time us, LP2/LP1 */
unsigned long core_timer; /* core power good time in ticks, LP0 */
unsigned long core_off_timer; /* core power off time ticks, LP0 */
bool corereq_high; /* Core power request active-high */
bool sysclkreq_high; /* System clock request is active-high */
enum tegra_suspend_mode suspend_mode;
unsigned long cpu_lp2_min_residency; /* Min LP2 state residency in us */
void (*board_suspend)(int lp_state, enum suspend_stage stg);
/* lp_state = 0 for LP0 state, 1 for LP1 state, 2 for LP2 state */
void (*board_resume)(int lp_state, enum resume_stage stg);
};
unsigned long tegra_cpu_power_good_time(void);
unsigned long tegra_cpu_power_off_time(void);
unsigned long tegra_cpu_lp2_min_residency(void);
void tegra_clear_cpu_in_lp2(int cpu);
bool tegra_set_cpu_in_lp2(int cpu);
int tegra_suspend_dram(enum tegra_suspend_mode mode);
#define FLOW_CTRL_CLUSTER_CONTROL \
(IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x2c)
#define FLOW_CTRL_CPU_CSR_IMMEDIATE_WAKE (1<<3)
#define FLOW_CTRL_CPU_CSR_SWITCH_CLUSTER (1<<2)
#define FUSE_SKU_DIRECT_CONFIG \
(IO_ADDRESS(TEGRA_FUSE_BASE) + 0x1F4)
#define FUSE_SKU_DISABLE_ALL_CPUS (1<<5)
#define FUSE_SKU_NUM_DISABLED_CPUS(x) (((x) >> 3) & 3)
void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat);
u64 tegra_rtc_read_ms(void);
/*
* Callbacks for platform drivers to implement.
*/
extern void (*tegra_deep_sleep)(int);
unsigned int tegra_idle_lp2_last(unsigned int us, unsigned int flags);
#if defined(CONFIG_PM_SLEEP) && !defined(CONFIG_ARCH_TEGRA_2x_SOC)
#define INSTRUMENT_CLUSTER_SWITCH 1 /* Should be zero for shipping code */
#define DEBUG_CLUSTER_SWITCH 0 /* Should be zero for shipping code */
#define PARAMETERIZE_CLUSTER_SWITCH 1 /* Should be zero for shipping code */
int tegra_cluster_control(unsigned int us, unsigned int flags);
void tegra_cluster_switch_prolog(unsigned int flags);
void tegra_cluster_switch_epilog(unsigned int flags);
void tegra_lp0_suspend_mc(void);
void tegra_lp0_resume_mc(void);
void tegra_lp0_cpu_mode(bool enter);
#else
static inline int tegra_cluster_control(unsigned int us, unsigned int flags)
#define INSTRUMENT_CLUSTER_SWITCH 0 /* Must be zero for ARCH_TEGRA_2x_SOC */
#define DEBUG_CLUSTER_SWITCH 0 /* Must be zero for ARCH_TEGRA_2x_SOC */
#define PARAMETERIZE_CLUSTER_SWITCH 0 /* Must be zero for ARCH_TEGRA_2x_SOC */
{
return -EPERM;
}
static inline void tegra_cluster_switch_prolog(unsigned int flags) {}
static inline void tegra_cluster_switch_epilog(unsigned int flags) {}
static inline void tegra_lp0_suspend_mc(void) {}
static inline void tegra_lp0_resume_mc(void) {}
static inline void tegra_lp0_cpu_mode(bool enter) {}
#endif
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
static inline bool is_g_cluster_present(void) { return true; }
static inline unsigned int is_lp_cluster(void) { return 0; }
void tegra2_lp0_suspend_init(void);
#else
static inline bool is_g_cluster_present(void)
{
u32 fuse_sku = readl(FUSE_SKU_DIRECT_CONFIG);
if (fuse_sku & FUSE_SKU_DISABLE_ALL_CPUS)
return false;
return true;
}
static inline unsigned int is_lp_cluster(void)
{
unsigned int reg;
reg = readl(FLOW_CTRL_CLUSTER_CONTROL);
return (reg & 1); /* 0 == G, 1 == LP*/
}
#endif
static inline void tegra_lp0_suspend_init(void)
{
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
tegra2_lp0_suspend_init();
#endif
}
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
void tegra2_lp2_set_trigger(unsigned long cycles);
unsigned long tegra2_lp2_timer_remain(void);
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
void tegra3_lp2_set_trigger(unsigned long cycles);
unsigned long tegra3_lp2_timer_remain(void);
#endif
static inline void tegra_lp2_set_trigger(unsigned long cycles)
{
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
tegra2_lp2_set_trigger(cycles);
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
tegra3_lp2_set_trigger(cycles);
#endif
}
static inline unsigned long tegra_lp2_timer_remain(void)
{
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
return tegra2_lp2_timer_remain();
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
return tegra3_lp2_timer_remain();
#endif
}
#if DEBUG_CLUSTER_SWITCH && 0 /* !!!FIXME!!! THIS IS BROKEN */
extern unsigned int tegra_cluster_debug;
#define DEBUG_CLUSTER(x) do { if (tegra_cluster_debug) printk x; } while (0)
#else
#define DEBUG_CLUSTER(x) do { } while (0)
#endif
#if PARAMETERIZE_CLUSTER_SWITCH
void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags);
#else
static inline void tegra_cluster_switch_set_parameters(
unsigned int us, unsigned int flags)
{ }
#endif
#ifdef CONFIG_SMP
extern bool tegra_all_cpus_booted __read_mostly;
#else
#define tegra_all_cpus_booted (true)
#endif
/* The debug channel uart base physical address */
extern unsigned long debug_uart_port_base;
extern struct clk *debug_uart_clk;
void tegra_console_uart_suspend(void);
void tegra_console_uart_resume(void);
#endif /* _MACH_TEGRA_PM_H_ */
|
