path: root/arch/arm/plat-mxc/include/mach/mvf.h

/*
 * based on arch/arm/plat-mxc/include/mach/mx6.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.

 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#ifndef __ASM_ARCH_MXC_MVF_H__
#define __ASM_ARCH_MXC_MVF_H__

#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif

/*!
 * @file arch-mxc/mvf.h
 * @brief This file contains register definitions.
 *
 * @ingroup MSL_MVF
 */

/*!
 * Register an interrupt handler for the SMN as well as the SCC.  In some
 * implementations, the SMN is not connected at all, and in others, it is
 * on the same interrupt line as the SCM. Comment this line out accordingly
 */
#define USE_SMN_INTERRUPT

/*!
 * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
 * Certain platforms need this bit to be set in order to receive Irda data.
 */
#define MXC_UART_IR_RXDMUX		0x0004
/*!
 * This option is used to set or clear the RXDMUXSEL bit in control reg 3.
 * Certain platforms need this bit to be set in order to receive UART data.
 */
#define MXC_UART_RXDMUX			0x0004

/*!
 * The maximum frequency that the pixel clock can be at so as to
 * activate DVFS-PER.
 */
#define DVFS_MAX_PIX_CLK		54000000

/* IROM
 */
#define IROM_BASE_ADDR			0x0
//#define IROM_SIZE			SZ_8M
#define IROM_SIZE			(SZ_32 * 3)

/* External Serial Flash 0
 */
#define MVF_EXT_S_FLASH0_BASE_ADDR	0x20000000
#define MVF_EXT_S_FLASH0_SIZE	(SZ_256M)

/* FlexBus
 */
#define MVF_FLEX_BUS_BASE_ADDR		0x30000000
#define MVF_FLEX_BUS_SIZE		(SZ_16M * 15)

/* IRAM
 * sysRAM0:	0x3F000000-0x3F03FFFF
 * susRAM1:	0x3F040000-0x3F07FFFF
 * gfxRAM:	0x3F400000-0x3F4FFFFF 
 */
#define MVF_IRAM0_BASE_ADDR		0x3F000000
/* The last 4K is for cpu hotplug to workaround wdog issue*/
//#define MVF_IRAM0_SIZE		(SZ_256K)
#define MVF_IRAM0_SIZE			(SZ_256K - SZ_4K)
#define MVF_IRAM1_BASE_ADDR		0x3F040000
#define MVF_IRAM1_SIZE			(SZ_256K)
#define MVF_IRAMGFX_BASE_ADDR		0x3F400000
#define MVF_IRAMGFX_SIZE		(SZ_1M)

/* AIPS 0
 */
#define MVF_AIPS0_BASE_ADDR		0x40000000
#define MVF_AIPS0_SIZE			(SZ_64K * 7)

/* Secure RAM
 */
#define MVF_SC_RAM_BASE_ADDR		0x40070000
#define MVF_SC_RAM_SIZE			(SZ_64K)

/* AIPS 1
 */
#define MVF_AIPS1_BASE_ADDR		0x40080000
#define MVF_AIPS1_SIZE			(SZ_4K * 127)

/* GPIOC
 */
#define MVF_GPIOC_BASE_ADDR		0x400FF000
#define MVF_GPIOC_SIZE			(SZ_4K)
#define GPIO0_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0000)
#define GPIO1_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0040)
#define GPIO2_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0080)
#define GPIO3_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x00c0)
#define GPIO4_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0100)


/* External Serial Flash 1
 */
#define MVF_EXT_S_FLASH1_BASE_ADDR	0x50000000
#define MVF_EXT_S_FLASH1_SIZE		(SZ_256M)

/* RLE
 */
#define MVF_RLE_BASE_ADDR		0x78000000
#define MVF_RLE_SIZE			(SZ_32M)

/* QSPI1 Rx Buffer
 */
#define MVF_QSPI1_BUF_BASE_ADDR		0x7A000000
#define MVF_QSPI1_BUF_SIZE		(SZ_32M)

/* QSPI0 Rx Buffer
 */
#define MVF_QSPI0_BUF_BASE_ADDR		0x7C000000
#define MVF_QSPI0_BUF_SIZE		(SZ_32M)

/* gfxRAM-RGB565 view
 */
#define MVF_GFX_RAM_RGB565_BASE_ADDR	0x7E000000
#define MVF_GFX_RAM_RGB565_SIZE		(SZ_8M)

/* gfxRAM-ARGB1555 view
 */
#define MVF_GFX_RAM_RGB1555_BASE_ADDR	0x7E800000
#define MVF_GFX_RAM_RGB1555_SIZE	(SZ_8M)

/* gfxRAM-ARGB4444 view
 */
#define MVF_GFX_RAM_ARGB4444_BASE_ADDR	0x7F000000
#define MVF_GFX_RAM_ARGB4444_SIZE	(SZ_8M)

/* Legacy Defines */
#define CSD0_DDR_BASE_ADDR		0x80000000
#define CSD1_DDR_BASE_ADDR		0xE0000000

/* AIPS#0- On Platform */
#define AIPS0_ON_BASE_ADDR		(MVF_AIPS0_BASE_ADDR + 0x0000)

#define MVF_MSCM_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x1000)
#define MVF_CA5_SCU_GIC_BASE_ADDR	(AIPS0_ON_BASE_ADDR + 0x2000)
#define MVF_CA5_INTD_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x3000)
#define MVF_CA5_L2C_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x6000)
#define MVF_NIC0_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x8000)
#define MVF_NIC1_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x9000)
#define MVF_NIC2_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0xA000)
#define MVF_NIC3_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0xB000)
#define MVF_NIC4_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0xC000)
#define MVF_NIC5_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0xD000)
#define MVF_NIC6_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0xE000)
#define MVF_NIC7_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0xF000)
#define MVF_AHBTZASC_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x10000)
#define MVF_TZASC_OCRAM_SYS0_BASE_ADDR	(AIPS0_ON_BASE_ADDR + 0x11000)
#define MVF_TZASC_OCRAM_SYS1_BASE_ADDR	(AIPS0_ON_BASE_ADDR + 0x12000)
#define MVF_TZASC_OCRAM_GFX_BASE_ADDR	(AIPS0_ON_BASE_ADDR + 0x13000)
#define MVF_TZASC_DDR0_BASE_ADDR	(AIPS0_ON_BASE_ADDR + 0x14000)
#define MVF_TZASC_DDR1_BASE_ADDR	(AIPS0_ON_BASE_ADDR + 0x15000)
#define MVF_CSU_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x17000)
#define MVF_DMA0_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x18000)
#define MVF_DMA0_TCD_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x19000)
#define MVF_SEMA4_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x1D000)
#define MVF_FLEXBUS_BASE_ADDR		(AIPS0_ON_BASE_ADDR + 0x1E000)

/* AIPS#0- Off Platform */
#define AIPS0_OFF_BASE_ADDR		(MVF_AIPS0_BASE_ADDR + 0x20000)

#define MVF_FLEX_CAN0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x0000)
#define MVF_DMAMUX0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x4000)
#define MVF_DMAMUX1_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x5000)
#define MVF_UART0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x7000)
#define MVF_UART1_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x8000)
#define MVF_UART2_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x9000)
#define MVF_UART3_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0xA000)
#define MVF_SPI0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0xC000)
#define MVF_SPI1_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0xD000)
#define MVF_SAI0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0xF000)
#define MVF_SAI1_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x10000)
#define MVF_SAI2_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x11000)
#define MVF_SAI3_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x12000)
#define MVF_CRC_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x13000)
#define MVF_USBC0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x14000)
#define MVF_PDB_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x16000)
#define MVF_PIT_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x17000)
#define MVF_FTM0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x18000)
#define MVF_FTM1_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x19000)
#define MVF_ADC0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x1B000)
#define MVF_TCON0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x1D000)
#define MVF_WDOC_A5_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x1E000)
#define MVF_WDOC_M4_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x1F000)
#define MVF_LPTMR_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x20000)
#define MVF_RLE_DEC_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x22000)
#define MVF_QSPI0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x24000)
#define MVF_IOMUXC_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x28000)
#define MVF_PORT_0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x29000)
#define MVF_PORT_1_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2A000)
#define MVF_PORT_2_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2B000)
#define MVF_PORT_3_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2C000)
#define MVF_PORT_4_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2D000)
#define MVF_ANADIG_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x30000)
#define MVF_SCSC_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x32000)
#define MVF_DCU0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x38000)
#define MVF_ASRC_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x40000)
#define MVF_SPDIF_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x41000)
#define MVF_ESAI_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x42000)
#define MVF_ESAI_BIFIFO_BASE_ADDR	(AIPS0_OFF_BASE_ADDR + 0x43000)
#define MVF_EWM_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x45000)
#define MVF_I2C0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x46000)
#define MVF_I2C1_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x47000)
#define MVF_WKUP_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x4A000)
#define MVF_CCM_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x4B000)
#define MVF_GPC_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x4C000)
#define MVF_VREG_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x4D000)
#define MVF_SRC_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x4E000)
#define MVF_CMU_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x4F000)

/* ATZ#1- On Platform */
#define AIPS1_ON_BASE_ADDR		(MVF_AIPS1_BASE_ADDR + 0x0000)

#define MVF_DAP_ROM_TBL_BASE_ADDR	(AIPS1_ON_BASE_ADDR + 0x7000)
#define MVF_CA5_DBG_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0x8000)
#define MVF_CA5_PMU_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0x9000)
#define MVF_CA5_ETM_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0xA000)
#define MVF_CA5_ROM_TBL_BASE_ADDR	(AIPS1_ON_BASE_ADDR + 0xC000)
#define MVF_CA5_CTI_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0xE000)
#define MVF_CA5_ITM_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0x10000)
#define MVF_CA5_ETB_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0x11000)
#define MVF_CA5_FUNNEL_BASE_ADDR	(AIPS1_ON_BASE_ADDR + 0x12000)
#define MVF_PLTF_TCTL_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0x13000)
#define MVF_PLTF_TPIU_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0x14000)
#define MVF_PLTF_FUNNEL_BASE_ADDR	(AIPS1_ON_BASE_ADDR + 0x15000)
#define MVF_PLTF_SWO_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0x16000)
#define MVF_DMA1_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0x18000)
#define MVF_DMA1_TCD_BASE_ADDR		(AIPS1_ON_BASE_ADDR + 0x19000)

/* ATZ#1- Off Platform */
#define AIPS1_OFF_BASE_ADDR		(MVF_AIPS1_BASE_ADDR + 0x20000)

#define MVF_DMAMUX2_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x1000)
#define MVF_DMAMUX3_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x2000)
#define MVF_OTP_CTRL_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x5000)
#define MVF_SNVS_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x7000)
#define MVF_WDOC_SNVS_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x8000)
#define MVF_UART4_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x9000)
#define MVF_UART5_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0xA000)
#define MVF_SPI2_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0xC000)
#define MVF_DDRMC_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0xE000)
#define MVF_SDHC0_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x11000)
#define MVF_SDHC1_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x11000)
#define MVF_USB_OTG1_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x14000)
#define MVF_FTM2_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x18000)
#define MVF_FTM3_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x19000)
#define MVF_ADC1_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x1B000)
#define MVF_TCON1_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x1D000)
#define MVF_SGMNT_LCD_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x1E000)
#define MVF_QSPI1_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x24000)
#define MVF_VIDEO_ADC_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x27000)
#define MVF_VIDEO_DEC_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x28000)
#define MVF_VIU3_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x29000)
#define MVF_DAC0_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x2C000)
#define MVF_DAC1_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x2D000)
#define MVF_OPEN_VG_GPU_BASE_ADDR	(AIPS1_OFF_BASE_ADDR + 0x2F000)
#define MVF_ENET0_IEEE1588_BASE_ADDR	(AIPS1_OFF_BASE_ADDR + 0x30000)
#define MVF_ENET1_IEEE1588_BASE_ADDR	(AIPS1_OFF_BASE_ADDR + 0x31000)
#define MVF_FLEX_CAN1_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x34000)
#define MVF_DCU1_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x38000)
#define MVF_NFC_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x40000)
#define MVF_I2C2_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x46000)
#define MVF_I2C3_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x47000)
#define MVF_ETH_L2_SW_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x48000)
#define MVF_CAAM_BASE_ADDR		(AIPS1_OFF_BASE_ADDR + 0x50000)

#define VF6XX_UART0_BASE_ADDR		MVF_UART0_BASE_ADDR
#define VF6XX_UART1_BASE_ADDR		MVF_UART1_BASE_ADDR
#define VF6XX_UART2_BASE_ADDR		MVF_UART2_BASE_ADDR
#define VF6XX_UART3_BASE_ADDR		MVF_UART3_BASE_ADDR
#define VF6XX_UART4_BASE_ADDR		MVF_UART4_BASE_ADDR
#define VF6XX_UART5_BASE_ADDR		MVF_UART5_BASE_ADDR
#define VF6XX_FEC_BASE_ADDR		MVF_ENET0_IEEE1588_BASE_ADDR
#define VF6XX_SNVS_BASE_ADDR		MVF_SNVS_BASE_ADDR

#define MVF_IO_P2V(x)			IMX_IO_P2V(x)
#define MVF_IO_ADDRESS(x)		IOMEM(MVF_IO_P2V(x))

/* GPC offsets */
//FIXME
//#define MXC_GPC_CNTR_OFFSET		0x0

/*
 * Interrupt numbers
 */
#define MXC_INT_START			32
#define MXC_INT_CPU2CPU_0		32
#define MXC_INT_CPU2CPU_1		33
#define MXC_INT_CPU2CPU_2		34
#define MXC_INT_CPU2CPU_3		35
#define MXC_INT_SEMA4			36
#define MXC_INT_DBG			37
#define MXC_INT_L2CC			38
#define MXC_INT_PMU			39
#define MXC_INT_DMA0			40
#define MXC_INT_DMA0_ERROR		41
#define MXC_INT_DMA1			42
#define MXC_INT_DMA1_ERROR		43
#define MXC_INT_MSCM_ECC0		46
#define MXC_INT_MSCM_ECC1		47
#define MXC_INT_CSU_ALARM		48
#define MXC_INT_MSCM_ACTZS		50
#define MXC_INT_WDOG_A5			52
#define MXC_INT_WDOG_M4			53
#define MXC_INT_WDOG_SNVS		54
#define MXC_INT_CP1_BOOT_FAIL		55
#define MXC_INT_QSPI0			56
#define MXC_INT_QSPI1			57
#define MXC_INT_DDRMC			58
#define MXC_INT_SDHC0			59
#define MXC_INT_SDHC1			60
#define MVF_INT_DCU0			62
#define MVF_INT_DCU1			63
#define MXC_INT_VIU			64
#define MXC_INT_GPU			66
#define MXC_INT_RLE			67
#define MXC_INT_SEG_LCD			68
#define MXC_INT_PIT			71
#define MXC_INT_LP_TIMER0		72
#define MXC_INT_FTM0			74
#define MXC_INT_FTM1			75
#define MXC_INT_FTM2			76
#define MXC_INT_FTM3			77
#define MXC_INT_ANADIG			81
#define MXC_INT_ANADIG_USBPHY0		82
#define MXC_INT_ANADIG_USBPHY1		83
#define MXC_INT_ADC0			85
#define MXC_INT_ADC1			86
#define MXC_INT_DAC0			87
#define MXC_INT_DAC1			88
#define MXC_INT_FLEX_CAN0		90
#define MXC_INT_FLEX_CAN1		91
#define MXC_INT_UART0			93
#define MXC_INT_UART1			94
#define MXC_INT_UART2			95
#define MXC_INT_UART3			96
#define MXC_INT_UART4			97
#define MXC_INT_UART5			98
#define MXC_INT_SPI0			99
#define MXC_INT_SPI1			100
#define MXC_INT_SPI2			101
#define MXC_INT_SPI3			102
#define MXC_INT_I2C0			103
#define MXC_INT_I2C1			104
#define MXC_INT_I2C2			105
#define MXC_INT_I2C3			106
#define MXC_INT_USBC0			107
#define MXC_INT_USBC1			108
#define MXC_INT_ENET_MAC0		110
#define MXC_INT_ENET_MAC1		111
#define MXC_INT_1588_TIMER0		112
#define MXC_INT_1588_TIMER1		113
#define MXC_INT_ENET_SWITCH		114
#define MXC_INT_NFC			115
#define MXC_INT_SAI0			116
#define MXC_INT_SAI1			117
#define MXC_INT_SAI2			118
#define MXC_INT_SAI3			119
#define MXC_INT_ESAI_BIFIFO		120
#define MXC_INT_SPDIF			121
#define MXC_INT_ASRC			122
#define MXC_INT_CMU			123
#define MXC_INT_WKUP0			124
#define MXC_INT_CCM1			126
#define MXC_INT_CCM2			127
#define MXC_INT_SRC			128
#define MXC_INT_PDB			129
#define MXC_INT_EWM			130
#define MXC_INT_SNVS_FUNCTIONAL		132
#define MXC_INT_SNVS_SECURITY		133
#define MXC_INT_CAAM			134
#define MXC_INT_GPIOA			139
#define MXC_INT_GPIOB			140
#define MXC_INT_GPIOC			141
#define MXC_INT_GPIOD			142
#define MXC_INT_GPIOE			143
#define MXC_INT_END			143

#define MVF_INT_UART0			MXC_INT_UART0
#define MVF_INT_UART1			MXC_INT_UART1
#define MVF_INT_UART2			MXC_INT_UART2
#define MVF_INT_UART3			MXC_INT_UART3
#define MVF_INT_UART4			MXC_INT_UART4
#define MVF_INT_UART5			MXC_INT_UART5
#define VF6XX_INT_FEC			MXC_INT_ENET_MAC0
#define VF6XX_INT_SNVS			MXC_INT_SNVS_FUNCTIONAL

#define IRQ_GLOBALTIMER			27
#define IRQ_LOCALTIMER			29

/*
 * EDMA request number
 */
/* EDMA0-MUX0/EDMA1-NUX3 */
#define MVF_DMA_REQ_UART0_RX		2
#define MVF_DMA_REQ_UART0_TX		3
#define MVF_DMA_REQ_UART1_RX		4
#define MVF_DMA_REQ_UART1_TX		5
#define MVF_DMA_REQ_UART2_RX		6
#define MVF_DMA_REQ_UART2_TX		7
#define MVF_DMA_REQ_UART3_RX		8
#define MVF_DMA_REQ_UART3_TX		9
#define MVF_DMA_REQ_SPI0_RX		12
#define MVF_DMA_REQ_SPI0_TX		13
#define MVF_DMA_REQ_SPI1_RX		14
#define MVF_DMA_REQ_SPI1_TX		15
#define MVF_DMA_REQ_SAI0_RX		16
#define MVF_DMA_REQ_SAI0_TX		17
#define MVF_DMA_REQ_SAI1_RX		18
#define MVF_DMA_REQ_SAI1_TX		19
#define MVF_DMA_REQ_SAI2_RX		20
#define MVF_DMA_REQ_SAI2_TX		21
#define MVF_DMA_REQ_PDB			22
#define MVF_DMA_REQ_FTM0_CH0		24
#define MVF_DMA_REQ_FTM0_CH1		25
#define MVF_DMA_REQ_FTM0_CH2		26
#define MVF_DMA_REQ_FTM0_CH3		27
#define MVF_DMA_REQ_FTM0_CH4		28
#define MVF_DMA_REQ_FTM0_CH5		29
#define MVF_DMA_REQ_FTM0_CH6		30
#define MVF_DMA_REQ_FTM0_CH7		31
#define MVF_DMA_REQ_FTM1_CH0		32
#define MVF_DMA_REQ_FTM1_CH1		33
#define MVF_DMA_REQ_ADC0		34
#define MVF_DMA_REQ_QSPI0		36
#define MVF_DMA_REQ_PORT_A		38
#define MVF_DMA_REQ_PORT_B		39
#define MVF_DMA_REQ_PORT_C		40
#define MVF_DMA_REQ_PORT_D		41
#define MVF_DMA_REQ_PORT_E		42
#define MVF_DMA_REQ_RLE_RX		45
#define MVF_DMA_REQ_RLE_TX		46
#define MVF_DMA_REQ_SPDIF_RX		47
#define MVF_DMA_REQ_SPDIF_TX		48
#define MVF_DMA_REQ_I2C0_RX		50
#define MVF_DMA_REQ_I2C0_TX		51
#define MVF_DMA_REQ_I2C1_RX		52
#define MVF_DMA_REQ_I2C1_TX		53
/* EDMA1-MUX2/EDMA0-NUX1 */
#define MVF_DMA_REQ_UART4_RX		2
#define MVF_DMA_REQ_UART4_TX		3
#define MVF_DMA_REQ_UART5_RX		4
#define MVF_DMA_REQ_UART5_TX		5
#define MVF_DMA_REQ_SAI3_RX		8
#define MVF_DMA_REQ_SAI3_TX		9
#define MVF_DMA_REQ_SPI2_RX		10
#define MVF_DMA_REQ_SPI2_TX		11
#define MVF_DMA_REQ_SPI3_RX		12
#define MVF_DMA_REQ_SPI3_TX		13
#define MVF_DMA_REQ_FTM2_CH0		16
#define MVF_DMA_REQ_FTM2_CH1		17
#define MVF_DMA_REQ_FTM3_CH0		18
#define MVF_DMA_REQ_FTM3_CH1		19
#define MVF_DMA_REQ_FTM3_CH2		20
#define MVF_DMA_REQ_FTM3_CH3		21
#define MVF_DMA_REQ_FTM3_CH4		22
#define MVF_DMA_REQ_FTM3_CH5		23
#define MVF_DMA_REQ_FTM3_CH6		24
#define MVF_DMA_REQ_FTM3_CH7		25
#define MVF_DMA_REQ_ADC1		26
#define MVF_DMA_REQ_QSPI1		27
#define MVF_DMA_REQ_DAC0		32
#define MVF_DMA_REQ_DAC1		33
#define MVF_DMA_REQ_ESAI_BIFIFO_TX	34
#define MVF_DMA_REQ_ESAI_BIFIFO_RX	35
#define MVF_DMA_REQ_I2C2_RX		36
#define MVF_DMA_REQ_I2C2_TX		37
#define MVF_DMA_REQ_I2C3_RX		38
#define MVF_DMA_REQ_I2C3_TX		39
#define MVF_DMA_REQ_ASRC0_TX		40
#define MVF_DMA_REQ_ASRC0_RX		41
#define MVF_DMA_REQ_ASRC1_TX		42
#define MVF_DMA_REQ_ASRC1_RX		43
#define MVF_DMA_REQ_PIT_TIMER0		44
#define MVF_DMA_REQ_PIT_TIMER1		45
#define MVF_DMA_REQ_PIT_TIMER2		46
#define MVF_DMA_REQ_PIT_TIMER3		47
#define MVF_DMA_REQ_PIT_TIMER4		48
#define MVF_DMA_REQ_PIT_TIMER5		49
#define MVF_DMA_REQ_PIT_TIMER6		50
#define MVF_DMA_REQ_PIT_TIMER7		51
#define MVF_DMA_REQ_ASRC2_TX		52
#define MVF_DMA_REQ_ASRC2_RX		53
/* each EDMA MUX */
#define MVF_DMA_REQ_DMAMUX_54		54
#define MVF_DMA_REQ_DMAMUX_55		55
#define MVF_DMA_REQ_DMAMUX_56		56
#define MVF_DMA_REQ_DMAMUX_57		57
#define MVF_DMA_REQ_DMAMUX_58		58
#define MVF_DMA_REQ_DMAMUX_59		59
#define MVF_DMA_REQ_DMAMUX_60		60
#define MVF_DMA_REQ_DMAMUX_61		61
#define MVF_DMA_REQ_DMAMUX_62		62
#define MVF_DMA_REQ_DMAMUX_63		63

#endif				/*  __ASM_ARCH_MXC_MVF_H__ */