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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Freescale LS2080a QDS Board.
*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*
*/
/dts-v1/;
#include "fsl-ls2080a.dtsi"
#include "fsl-ls208xa-qds.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
chosen {
stdout-path = "serial0:115200n8";
};
};
/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
&dpmac9 {
phy-handle = <&mdio0_phy12>;
phy-connection-type = "sgmii";
};
&dpmac10 {
phy-handle = <&mdio0_phy13>;
phy-connection-type = "sgmii";
};
&dpmac11 {
phy-handle = <&mdio0_phy14>;
phy-connection-type = "sgmii";
};
&dpmac12 {
phy-handle = <&mdio0_phy15>;
phy-connection-type = "sgmii";
};
&ifc {
boardctrl: board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-mfd";
reg = <3 0 0x300>; /* TODO check address */
ranges = <0 3 0 0x300>;
mdio_mux_emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&emdio1>;
reg = <0x54 1>; /* BRDCFG4 */
mux-mask = <0xe0>; /* EMI1_MDIO */
#address-cells=<1>;
#size-cells = <0>;
/* Child MDIO buses, one for each riser card:
* reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
* VSC8234 PHYs on the riser cards.
*/
mdio_mux3: mdio@60 {
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
mdio0_phy12: mdio_phy0@1c {
reg = <0x1c>;
};
mdio0_phy13: mdio_phy1@1d {
reg = <0x1d>;
};
mdio0_phy14: mdio_phy2@1e {
reg = <0x1e>;
};
mdio0_phy15: mdio_phy3@1f {
reg = <0x1f>;
};
};
};
};
};
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