1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
conn_subsys: bus@5b000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
conn_axi_clk: clock-conn-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <333333333>;
clock-output-names = "conn_axi_clk";
};
conn_ahb_clk: clock-conn-ahb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <166666666>;
clock-output-names = "conn_ahb_clk";
};
conn_ipg_clk: clock-conn-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <83333333>;
clock-output-names = "conn_ipg_clk";
};
usdhc1: mmc@5b010000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_0>;
status = "disabled";
};
usdhc2: mmc@5b020000 {
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b020000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
usdhc3: mmc@5b030000 {
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b030000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>;
clock-names = "ipg", "ahb", "per";
power-domains = <&pd IMX_SC_R_SDHC_2>;
status = "disabled";
};
fec1: ethernet@5b040000 {
reg = <0x5b040000 0x10000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
status = "disabled";
};
fec2: ethernet@5b050000 {
reg = <0x5b050000 0x10000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_1>;
status = "disabled";
};
/* LPCG clocks */
conn_lpcg: clock-controller-legacy@5b200000 {
reg = <0x5b200000 0xb0000>;
#clock-cells = <1>;
};
sdhc0_lpcg: clock-controller@5b200000 {
reg = <0x5b200000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_CONN_SDHC0_CLK>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "sdhc0_lpcg_per_clk",
"sdhc0_lpcg_ipg_clk",
"sdhc0_lpcg_ahb_clk";
power-domains = <&pd IMX_SC_R_SDHC_0>;
};
sdhc1_lpcg: clock-controller@5b210000 {
reg = <0x5b210000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_CONN_SDHC1_CLK>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "sdhc1_lpcg_per_clk",
"sdhc1_lpcg_ipg_clk",
"sdhc1_lpcg_ahb_clk";
power-domains = <&pd IMX_SC_R_SDHC_1>;
};
sdhc2_lpcg: clock-controller@5b220000 {
reg = <0x5b220000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_CONN_SDHC2_CLK>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "sdhc2_lpcg_per_clk",
"sdhc2_lpcg_ipg_clk",
"sdhc2_lpcg_ahb_clk";
power-domains = <&pd IMX_SC_R_SDHC_2>;
};
enet0_lpcg: clock-controller@5b230000 {
reg = <0x5b230000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
<&clk IMX_CONN_ENET0_ROOT_CLK>,
<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "enet0_ipg_root_clk",
"enet0_tx_clk",
"enet0_ahb_clk",
"enet0_ipg_clk",
"enet0_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_0>;
};
enet1_lpcg: clock-controller@5b240000 {
reg = <0x5b240000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
<&clk IMX_CONN_ENET1_ROOT_CLK>,
<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "enet1_ipg_root_clk",
"enet1_tx_clk",
"enet1_ahb_clk",
"enet1_ipg_clk",
"enet1_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_1>;
};
};
|
