path: root/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>

dma_subsys: bus@5a000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;

	dma_ipg_clk: clock-dma-ipg {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <120000000>;
		clock-output-names = "dma_ipg_clk";
	};

	lpuart0: serial@5a060000 {
		reg = <0x5a060000 0x1000>;
		interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart0_lpcg 1>, <&uart0_lpcg 0>;
		clock-names = "ipg", "baud";
		assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd IMX_SC_R_UART_0>;
		status = "disabled";
	};

	lpuart1: serial@5a070000 {
		reg = <0x5a070000 0x1000>;
		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart1_lpcg 1>, <&uart1_lpcg 0>;
		clock-names = "ipg", "baud";
		assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd IMX_SC_R_UART_1>;
		power-domain-names = "uart";
		dma-names = "tx","rx";
		dmas = <&edma2 11 0 0>,
			<&edma2 10 0 1>;
		status = "disabled";
	};

	lpuart2: serial@5a080000 {
		reg = <0x5a080000 0x1000>;
		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart2_lpcg 1>, <&uart2_lpcg 0>;
		clock-names = "ipg", "baud";
		assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd IMX_SC_R_UART_2>;
		power-domain-names = "uart";
		dma-names = "tx","rx";
		dmas = <&edma2 13 0 0>,
			<&edma2 12 0 1>;
		status = "disabled";
	};

	lpuart3: serial@5a090000 {
		reg = <0x5a090000 0x1000>;
		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart3_lpcg 1>, <&uart3_lpcg 0>;
		clock-names = "ipg", "baud";
		assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <80000000>;
		power-domains = <&pd IMX_SC_R_UART_3>;
		power-domain-names = "uart";
		dma-names = "tx","rx";
		dmas = <&edma2 15 0 0>,
			<&edma2 14 0 1>;
		status = "disabled";
	};

	emvsim0: sim0@5a0d0000 {
		compatible = "fsl,imx8-emvsim";
		reg = <0x5a0d0000 0x10000>;
		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&emvsim0_lpcg 0>,
			 <&emvsim0_lpcg 1>;
		clock-names = "sim", "ipg";
		assigned-clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_EMVSIM_0>, <&pd IMX_SC_R_BOARD_R2>;
		power-domain-names = "sim_pd", "sim_aux_pd";
		status = "disabled";
	};

	spi0_lpcg: clock-controller@5a400000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a400000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "spi0_lpcg_clk",
				     "spi0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SPI_0>;
	};

	spi1_lpcg: clock-controller@5a410000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a410000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "spi1_lpcg_clk",
				     "spi1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SPI_1>;
	};

	spi2_lpcg: clock-controller@5a420000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a420000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "spi2_lpcg_clk",
				     "spi2_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SPI_2>;
	};

	spi3_lpcg: clock-controller@5a430000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a430000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "spi3_lpcg_clk",
				     "spi3_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SPI_3>;
	};

	uart0_lpcg: clock-controller@5a460000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a460000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "uart0_lpcg_baud_clk",
				     "uart0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_0>;
	};

	uart1_lpcg: clock-controller@5a470000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a470000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "uart1_lpcg_baud_clk",
				     "uart1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_1>;
	};

	uart2_lpcg: clock-controller@5a480000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a480000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "uart2_lpcg_baud_clk",
				     "uart2_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_2>;
	};

	uart3_lpcg: clock-controller@5a490000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a490000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "uart3_lpcg_baud_clk",
				     "uart3_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_3>;
	};

	emvsim0_lpcg: clock-controller@5a4d0000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a4d0000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_EMVSIM_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "emvsim0_lpcg_clk",
				     "emvsim0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_EMVSIM_0>;
	};

	adc0: adc@5a880000 {
		compatible = "fsl,imx8qxp-adc";
		#io-channel-cells = <1>;
		reg = <0x5a880000 0x10000>;
		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&adc0_lpcg 0>,
			 <&adc0_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_ADC_0>;
		status = "disabled";
	 };

	adc1: adc@5a890000 {
		compatible = "fsl,imx8qxp-adc";
		#io-channel-cells = <1>;
		reg = <0x5a890000 0x10000>;
		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&adc1_lpcg 0>,
			 <&adc1_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_ADC_1>;
		status = "disabled";
	};


	i2c0: i2c@5a800000 {
		reg = <0x5a800000 0x4000>;
		interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c0_lpcg 0>,
			 <&i2c0_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_0>;
		status = "disabled";
	};

	i2c1: i2c@5a810000 {
		reg = <0x5a810000 0x4000>;
		interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c1_lpcg 0>,
			 <&i2c1_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_1>;
		status = "disabled";
	};

	i2c2: i2c@5a820000 {
		reg = <0x5a820000 0x4000>;
		interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c2_lpcg 0>,
			 <&i2c2_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_2>;
		status = "disabled";
	};

	i2c3: i2c@5a830000 {
		reg = <0x5a830000 0x4000>;
		interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2c3_lpcg 0>,
			 <&i2c3_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_3>;
		status = "disabled";
	};

	i2c0_lpcg: clock-controller@5ac00000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac00000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "i2c0_lpcg_clk",
				     "i2c0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_0>;
	};

	i2c1_lpcg: clock-controller@5ac10000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac10000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "i2c1_lpcg_clk",
				     "i2c1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_1>;
	};

	i2c2_lpcg: clock-controller@5ac20000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac20000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "i2c2_lpcg_clk",
				     "i2c2_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_2>;
	};

	i2c3_lpcg: clock-controller@5ac30000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac30000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "i2c3_lpcg_clk",
				     "i2c3_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_I2C_3>;
	};

	edma2: dma-controller@5a1f0000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x5a1f0000 0x10000>,
		      <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */
		      <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */
		      <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */
		      <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */
		      <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */
		      <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */
		      <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */
		      <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */
		      <0x5a280000 0x10000>, /* channel8 UART0 rx */
		      <0x5a290000 0x10000>, /* channel9 UART0 tx */
		      <0x5a2a0000 0x10000>, /* channel10 UART1 rx */
		      <0x5a2b0000 0x10000>, /* channel11 UART1 tx */
		      <0x5a2c0000 0x10000>, /* channel12 UART2 rx */
		      <0x5a2d0000 0x10000>, /* channel13 UART2 tx */
		      <0x5a2e0000 0x10000>, /* channel14 UART3 rx */
		      <0x5a2f0000 0x10000>; /* channel15 UART3 tx */
		#dma-cells = <3>;
		dma-channels = <16>;
		interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma2-chan0-rx", "edma2-chan1-tx",
				  "edma2-chan2-rx", "edma2-chan3-tx",
				  "edma2-chan4-rx", "edma2-chan5-tx",
				  "edma2-chan6-rx", "edma2-chan7-tx",
				  "edma2-chan8-rx", "edma2-chan9-tx",
				  "edma2-chan10-rx", "edma2-chan11-tx",
				  "edma2-chan12-rx", "edma2-chan13-tx",
				  "edma2-chan14-rx", "edma2-chan15-tx";
		power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
				<&pd IMX_SC_R_DMA_2_CH1>,
				<&pd IMX_SC_R_DMA_2_CH2>,
				<&pd IMX_SC_R_DMA_2_CH3>,
				<&pd IMX_SC_R_DMA_2_CH4>,
				<&pd IMX_SC_R_DMA_2_CH5>,
				<&pd IMX_SC_R_DMA_2_CH6>,
				<&pd IMX_SC_R_DMA_2_CH7>,
				<&pd IMX_SC_R_DMA_2_CH8>,
				<&pd IMX_SC_R_DMA_2_CH9>,
				<&pd IMX_SC_R_DMA_2_CH10>,
				<&pd IMX_SC_R_DMA_2_CH11>,
				<&pd IMX_SC_R_DMA_2_CH12>,
				<&pd IMX_SC_R_DMA_2_CH13>,
				<&pd IMX_SC_R_DMA_2_CH14>,
				<&pd IMX_SC_R_DMA_2_CH15>;
		power-domain-names = "edma2-chan0", "edma2-chan1",
				     "edma2-chan2", "edma2-chan3",
				     "edma2-chan4", "edma2-chan5",
				     "edma2-chan6", "edma2-chan7",
				     "edma2-chan8", "edma2-chan9",
				     "edma2-chan10", "edma2-chan11",
				     "edma2-chan12", "edma2-chan13",
				     "edma2-chan14", "edma2-chan15";
		status = "disabled";
	};

	flexcan1: can@5a8d0000 {
		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
		reg = <0x5a8d0000 0x10000>;
		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&can0_lpcg 1>,
			 <&can0_lpcg 0>;
		clock-names = "ipg", "per";
		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <40000000>;
		power-domains = <&pd IMX_SC_R_CAN_0>;
		/* SLSlice[4] */
		fsl,clk-source = /bits/ 8 <0>;
		fsl,scu-index = /bits/ 8 <0>;
		status = "disabled";
	};

	flexcan2: can@5a8e0000 {
		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
		reg = <0x5a8e0000 0x10000>;
		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		/* CAN0 clock and PD is shared among all CAN instances as
		 * CAN1 shares CAN0's clock and to enable CAN0's clock it
		 * has to be powered on.
		 */
		clocks = <&can0_lpcg 1>,
			 <&can0_lpcg 0>;
		clock-names = "ipg", "per";
		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <40000000>;
		power-domains = <&pd IMX_SC_R_CAN_1>;
		/* SLSlice[4] */
		fsl,clk-source = /bits/ 8 <0>;
		fsl,scu-index = /bits/ 8 <1>;
		status = "disabled";
	};

	flexcan3: can@5a8f0000 {
		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
		reg = <0x5a8f0000 0x10000>;
		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		/* CAN0 clock and PD is shared among all CAN instances as
		 * CAN2 shares CAN0's clock and to enable CAN0's clock it
		 * has to be powered on.
		 */
		clocks = <&can0_lpcg 1>,
			 <&can0_lpcg 0>;
		clock-names = "ipg", "per";
		assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <40000000>;
		power-domains = <&pd IMX_SC_R_CAN_2>;
		/* SLSlice[4] */
		fsl,clk-source = /bits/ 8 <0>;
		fsl,scu-index = /bits/ 8 <2>;
		status = "disabled";
	};

	adc0_lpcg: clock-controller@5ac80000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac80000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "adc0_lpcg_clk",
				     "adc0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_ADC_0>;
	};

	adc1_lpcg: clock-controller@5ac90000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5ac90000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "adc1_lpcg_clk",
				     "adc1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_ADC_1>;
	};

	lpspi0: spi@5a000000 {
		compatible = "fsl,imx7ulp-spi";
		reg = <0x5a000000 0x10000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&spi0_lpcg 0>,
			 <&spi0_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <60000000>;
		power-domains = <&pd IMX_SC_R_SPI_0>;
		dma-names = "tx","rx";
		dmas = <&edma2 1 0 0>, <&edma2 0 0 1>;
		status = "disabled";
	};

	lpspi1: spi@5a010000 {
		compatible = "fsl,imx7ulp-spi";
		reg = <0x5a010000 0x10000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&spi1_lpcg 0>,
			 <&spi1_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <60000000>;
		power-domains = <&pd IMX_SC_R_SPI_1>;
		dma-names = "tx","rx";
		dmas = <&edma2 3 0 0>, <&edma2 2 0 1>;
		status = "disabled";
	};

	lpspi2: spi@5a020000 {
		compatible = "fsl,imx7ulp-spi";
		reg = <0x5a020000 0x10000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&spi2_lpcg 0>,
			 <&spi2_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <60000000>;
		power-domains = <&pd IMX_SC_R_SPI_2>;
		dma-names = "tx","rx";
		dmas = <&edma2 5 0 0>, <&edma2 4 0 1>;
		status = "disabled";
	};

	lpspi3: spi@5a030000 {
		compatible = "fsl,imx7ulp-spi";
		reg = <0x5a030000 0x10000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		clocks = <&spi3_lpcg 0>,
			 <&spi3_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <60000000>;
		power-domains = <&pd IMX_SC_R_SPI_3>;
		dma-names = "tx","rx";
		dmas = <&edma2 7 0 0>, <&edma2 6 0 1>;
		status = "disabled";
	};

	can0_lpcg: clock-controller@5acd0000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5acd0000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>, <&dma_ipg_clk>;
		bit-offset = <0 16 20>;
		clock-output-names = "can0_lpcg_pe_clk",
				     "can0_lpcg_ipg_clk",
				     "can0_lpcg_chi_clk";
		power-domains = <&pd IMX_SC_R_CAN_0>;
	};

	i2c_rpbus_0: i2c-rpbus-0 {
		compatible = "fsl,i2c-rpbus";
		status = "disabled";
	};

	i2c_rpbus_1: i2c-rpbus-1 {
		compatible = "fsl,i2c-rpbus";
		status = "disabled";
	};

	i2c_rpbus_5: i2c-rpbus-5 {
		compatible = "fsl,i2c-rpbus";
		status = "disabled";
	};

	i2c_rpbus_12: i2c-rpbus-12 {
		compatible = "fsl,i2c-rpbus";
		status = "disabled";
	};

	i2c_rpbus_13: i2c-rpbus-13 {
		compatible = "fsl,i2c-rpbus";
		status = "disabled";
	};

	i2c_rpbus_14: i2c-rpbus-14 {
		compatible = "fsl,i2c-rpbus";
		status = "disabled";
	};

	i2c_rpbus_15: i2c-rpbus-15 {
		compatible = "fsl,i2c-rpbus";
		status = "disabled";
	};

	adma_pwm: pwm@5a190000 {
		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
		reg = <0x5a190000 0x1000>;
		clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <2>;
		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
	};

	adma_pwm_lpcg: clock-controller@5a590000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a590000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "adma_pwm_lpcg_clk",
				     "adma_pwm_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
	};
};