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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 NXP.
*/
#include "imx8mq-evk.dts"
/delete-node/&hdmi;
&irqsteer {
status = "okay";
};
&lcdif {
status = "disabled";
};
&dcss {
status = "okay";
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_CLK_DC_PIXEL>,
<&clk IMX8MQ_CLK_DISP_DTRC>;
clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
<&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_CLK_DISP_AXI>,
<&clk IMX8MQ_CLK_DISP_RTRM>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_VIDEO_PLL1>,
<&clk IMX8MQ_CLK_27M>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
assigned-clock-rates = <600000000>, <0>, <0>,
<800000000>,
<400000000>;
port@0 {
dcss_out: endpoint {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_dsi {
status = "okay";
fsl,clock-drop-level = <2>;
panel@0 {
compatible = "raydium,rm67191";
reg = <0>;
pinctrl-0 = <&pinctrl_mipi_dsi_en>;
pinctrl-names = "default";
reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
dsi-lanes = <4>;
video-mode = <2>;
width-mm = <68>;
height-mm = <121>;
port {
panel_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mipi_dsi_in: endpoint {
remote-endpoint = <&dcss_out>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&dphy {
status = "okay";
};
&iomuxc {
pinctrl_mipi_dsi_en: mipi_dsi_en {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
>;
};
};
&synaptics_dsx_ts {
status = "okay";
};
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