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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
#include "imx8mq-evk.dts"
/ {
interrupt-parent = <&gic>;
};
&CPU_SLEEP {
/* We are not using GPC for now, need set 0 to avoid hang */
arm,psci-suspend-param = <0x0>;
};
&clk {
init-on-array = <IMX8MQ_CLK_UART2_ROOT
IMX8MQ_CLK_UART2
IMX8MQ_CLK_USDHC1_ROOT
IMX8MQ_CLK_NAND_USDHC_BUS>;
};
&iomuxc {
/*
* Used for the 2nd Linux.
* TODO: M4 may use these pins.
*/
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
>;
};
};
&{/busfreq} {
/* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */
status = "disabled";
};
&resmem {
jh_reserved: jh@fdc00000 {
no-map;
reg = <0 0xfdc00000 0x0 0x400000>;
};
inmate_reserved: inmate@c0000000 {
no-map;
reg = <0 0xc0000000 0x0 0x3dc00000>;
};
loader_reserved: loader@bff00000 {
no-map;
reg = <0 0xbff00000 0x0 0x00100000>;
};
ivshmem_reserved: ivshmem@bfe00000 {
no-map;
reg = <0 0xbfe00000 0x0 0x00100000>;
};
ivshmem2_reserved: ivshmem2@bfd00000 {
no-map;
reg = <0 0xbfd00000 0x0 0x00100000>;
};
pci_reserved: pci@bfc00000 {
no-map;
reg = <0 0xbfb00000 0x0 0x00200000>;
};
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x30000000>;
alloc-ranges = <0 0x80000000 0 0x30000000>;
linux,cma-default;
};
};
&uart1 {
/* uart2 is used by the 2nd OS, so configure pin and clk */
pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>,
<&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_CLK_25M>;
};
&usdhc1 {
status = "disabled";
};
&usdhc2 {
/* sdhc1 is used by 2nd linux, configure the pin */
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_200mhz>;
};
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