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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Richard Zhu <hongxing.zhu@nxp.com>
*/
&hsio_subsys {
phyx1_lpcg: clock-controller@5f090000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f090000 0x10000>;
#clock-cells = <1>;
clocks = <&hsio_refb_clk>, <&hsio_per_clk>,
<&hsio_per_clk>, <&hsio_per_clk>;
bit-offset = <0 4 8 16>;
clock-output-names = "hsio_phyx1_pclk",
"hsio_phyx1_epcs_tx_clk",
"hsio_phyx1_epcs_rx_clk",
"hsio_phyx1_apb_clk";
power-domains = <&pd IMX_SC_R_SERDES_1>;
};
};
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