summaryrefslogtreecommitdiff
path: root/drivers/net/wireless/ath/ath9k/reg.h
blob: 456f3ec20fef94235ccb724c66419b6a7012d260 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef REG_H
#define REG_H

#include "../reg.h"

#define AR_CR                0x0008
#define AR_CR_RXE            (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
#define AR_CR_RXD            0x00000020
#define AR_CR_SWI            0x00000040

#define AR_RXDP              0x000C

#define AR_CFG               0x0014
#define AR_CFG_SWTD          0x00000001
#define AR_CFG_SWTB          0x00000002
#define AR_CFG_SWRD          0x00000004
#define AR_CFG_SWRB          0x00000008
#define AR_CFG_SWRG          0x00000010
#define AR_CFG_AP_ADHOC_INDICATION 0x00000020
#define AR_CFG_PHOK          0x00000100
#define AR_CFG_CLK_GATE_DIS  0x00000400
#define AR_CFG_EEBS          0x00000200
#define AR_CFG_PCI_MASTER_REQ_Q_THRESH         0x00060000
#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S       17

#define AR_RXBP_THRESH       0x0018
#define AR_RXBP_THRESH_HP    0x0000000f
#define AR_RXBP_THRESH_HP_S  0
#define AR_RXBP_THRESH_LP    0x00003f00
#define AR_RXBP_THRESH_LP_S  8

#define AR_MIRT              0x0020
#define AR_MIRT_VAL          0x0000ffff
#define AR_MIRT_VAL_S        16

#define AR_IER               0x0024
#define AR_IER_ENABLE        0x00000001
#define AR_IER_DISABLE       0x00000000

#define AR_TIMT              0x0028
#define AR_TIMT_LAST         0x0000ffff
#define AR_TIMT_LAST_S       0
#define AR_TIMT_FIRST        0xffff0000
#define AR_TIMT_FIRST_S      16

#define AR_RIMT              0x002C
#define AR_RIMT_LAST         0x0000ffff
#define AR_RIMT_LAST_S       0
#define AR_RIMT_FIRST        0xffff0000
#define AR_RIMT_FIRST_S      16

#define AR_DMASIZE_4B        0x00000000
#define AR_DMASIZE_8B        0x00000001
#define AR_DMASIZE_16B       0x00000002
#define AR_DMASIZE_32B       0x00000003
#define AR_DMASIZE_64B       0x00000004
#define AR_DMASIZE_128B      0x00000005
#define AR_DMASIZE_256B      0x00000006
#define AR_DMASIZE_512B      0x00000007

#define AR_TXCFG             0x0030
#define AR_TXCFG_DMASZ_MASK  0x00000007
#define AR_TXCFG_DMASZ_4B    0
#define AR_TXCFG_DMASZ_8B    1
#define AR_TXCFG_DMASZ_16B   2
#define AR_TXCFG_DMASZ_32B   3
#define AR_TXCFG_DMASZ_64B   4
#define AR_TXCFG_DMASZ_128B  5
#define AR_TXCFG_DMASZ_256B  6
#define AR_TXCFG_DMASZ_512B  7
#define AR_FTRIG             0x000003F0
#define AR_FTRIG_S           4
#define AR_FTRIG_IMMED       0x00000000
#define AR_FTRIG_64B         0x00000010
#define AR_FTRIG_128B        0x00000020
#define AR_FTRIG_192B        0x00000030
#define AR_FTRIG_256B        0x00000040
#define AR_FTRIG_512B        0x00000080
#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800

#define AR_RXCFG             0x0034
#define AR_RXCFG_CHIRP       0x00000008
#define AR_RXCFG_ZLFDMA      0x00000010
#define AR_RXCFG_DMASZ_MASK  0x00000007
#define AR_RXCFG_DMASZ_4B    0
#define AR_RXCFG_DMASZ_8B    1
#define AR_RXCFG_DMASZ_16B   2
#define AR_RXCFG_DMASZ_32B   3
#define AR_RXCFG_DMASZ_64B   4
#define AR_RXCFG_DMASZ_128B  5
#define AR_RXCFG_DMASZ_256B  6
#define AR_RXCFG_DMASZ_512B  7

#define AR_TOPS              0x0044
#define AR_TOPS_MASK         0x0000FFFF

#define AR_RXNPTO            0x0048
#define AR_RXNPTO_MASK       0x000003FF

#define AR_TXNPTO            0x004C
#define AR_TXNPTO_MASK       0x000003FF
#define AR_TXNPTO_QCU_MASK   0x000FFC00

#define AR_RPGTO             0x0050
#define AR_RPGTO_MASK        0x000003FF

#define AR_RPCNT             0x0054
#define AR_RPCNT_MASK        0x0000001F

#define AR_MACMISC           0x0058
#define AR_MACMISC_PCI_EXT_FORCE        0x00000010
#define AR_MACMISC_DMA_OBS              0x000001E0
#define AR_MACMISC_DMA_OBS_S            5
#define AR_MACMISC_DMA_OBS_LINE_0       0
#define AR_MACMISC_DMA_OBS_LINE_1       1
#define AR_MACMISC_DMA_OBS_LINE_2       2
#define AR_MACMISC_DMA_OBS_LINE_3       3
#define AR_MACMISC_DMA_OBS_LINE_4       4
#define AR_MACMISC_DMA_OBS_LINE_5       5
#define AR_MACMISC_DMA_OBS_LINE_6       6
#define AR_MACMISC_DMA_OBS_LINE_7       7
#define AR_MACMISC_DMA_OBS_LINE_8       8
#define AR_MACMISC_MISC_OBS             0x00000E00
#define AR_MACMISC_MISC_OBS_S           9
#define AR_MACMISC_MISC_OBS_BUS_LSB     0x00007000
#define AR_MACMISC_MISC_OBS_BUS_LSB_S   12
#define AR_MACMISC_MISC_OBS_BUS_MSB     0x00038000
#define AR_MACMISC_MISC_OBS_BUS_MSB_S   15
#define AR_MACMISC_MISC_OBS_BUS_1       1

#define AR_DATABUF_SIZE		0x0060
#define AR_DATABUF_SIZE_MASK	0x00000FFF

#define AR_GTXTO    0x0064
#define AR_GTXTO_TIMEOUT_COUNTER    0x0000FFFF
#define AR_GTXTO_TIMEOUT_LIMIT      0xFFFF0000
#define AR_GTXTO_TIMEOUT_LIMIT_S    16

#define AR_GTTM     0x0068
#define AR_GTTM_USEC          0x00000001
#define AR_GTTM_IGNORE_IDLE   0x00000002
#define AR_GTTM_RESET_IDLE    0x00000004
#define AR_GTTM_CST_USEC      0x00000008

#define AR_CST         0x006C
#define AR_CST_TIMEOUT_COUNTER    0x0000FFFF
#define AR_CST_TIMEOUT_LIMIT      0xFFFF0000
#define AR_CST_TIMEOUT_LIMIT_S    16

#define AR_HP_RXDP 0x0074
#define AR_LP_RXDP 0x0078

#define AR_ISR               0x0080
#define AR_ISR_RXOK          0x00000001
#define AR_ISR_RXDESC        0x00000002
#define AR_ISR_HP_RXOK	     0x00000001
#define AR_ISR_LP_RXOK	     0x00000002
#define AR_ISR_RXERR         0x00000004
#define AR_ISR_RXNOPKT       0x00000008
#define AR_ISR_RXEOL         0x00000010
#define AR_ISR_RXORN         0x00000020
#define AR_ISR_TXOK          0x00000040
#define AR_ISR_TXDESC        0x00000080
#define AR_ISR_TXERR         0x00000100
#define AR_ISR_TXNOPKT       0x00000200
#define AR_ISR_TXEOL         0x00000400
#define AR_ISR_TXURN         0x00000800
#define AR_ISR_MIB           0x00001000
#define AR_ISR_SWI           0x00002000
#define AR_ISR_RXPHY         0x00004000
#define AR_ISR_RXKCM         0x00008000
#define AR_ISR_SWBA          0x00010000
#define AR_ISR_BRSSI         0x00020000
#define AR_ISR_BMISS         0x00040000
#define AR_ISR_BNR           0x00100000
#define AR_ISR_RXCHIRP       0x00200000
#define AR_ISR_BCNMISC       0x00800000
#define AR_ISR_TIM           0x00800000
#define AR_ISR_QCBROVF       0x02000000
#define AR_ISR_QCBRURN       0x04000000
#define AR_ISR_QTRIG         0x08000000
#define AR_ISR_GENTMR        0x10000000

#define AR_ISR_TXMINTR       0x00080000
#define AR_ISR_RXMINTR       0x01000000
#define AR_ISR_TXINTM        0x40000000
#define AR_ISR_RXINTM        0x80000000

#define AR_ISR_S0               0x0084
#define AR_ISR_S0_QCU_TXOK      0x000003FF
#define AR_ISR_S0_QCU_TXOK_S    0
#define AR_ISR_S0_QCU_TXDESC    0x03FF0000
#define AR_ISR_S0_QCU_TXDESC_S  16

#define AR_ISR_S1              0x0088
#define AR_ISR_S1_QCU_TXERR    0x000003FF
#define AR_ISR_S1_QCU_TXERR_S  0
#define AR_ISR_S1_QCU_TXEOL    0x03FF0000
#define AR_ISR_S1_QCU_TXEOL_S  16

#define AR_ISR_S2              0x008c
#define AR_ISR_S2_QCU_TXURN    0x000003FF
#define AR_ISR_S2_BB_WATCHDOG  0x00010000
#define AR_ISR_S2_CST          0x00400000
#define AR_ISR_S2_GTT          0x00800000
#define AR_ISR_S2_TIM          0x01000000
#define AR_ISR_S2_CABEND       0x02000000
#define AR_ISR_S2_DTIMSYNC     0x04000000
#define AR_ISR_S2_BCNTO        0x08000000
#define AR_ISR_S2_CABTO        0x10000000
#define AR_ISR_S2_DTIM         0x20000000
#define AR_ISR_S2_TSFOOR       0x40000000
#define AR_ISR_S2_TBTT_TIME    0x80000000

#define AR_ISR_S3             0x0090
#define AR_ISR_S3_QCU_QCBROVF    0x000003FF
#define AR_ISR_S3_QCU_QCBRURN    0x03FF0000

#define AR_ISR_S4              0x0094
#define AR_ISR_S4_QCU_QTRIG    0x000003FF
#define AR_ISR_S4_RESV0        0xFFFFFC00

#define AR_ISR_S5                   0x0098
#define AR_ISR_S5_TIMER_TRIG        0x000000FF
#define AR_ISR_S5_TIMER_THRESH      0x0007FE00
#define AR_ISR_S5_TIM_TIMER         0x00000010
#define AR_ISR_S5_DTIM_TIMER        0x00000020
#define AR_IMR_S5                   0x00b8
#define AR_IMR_S5_TIM_TIMER         0x00000010
#define AR_IMR_S5_DTIM_TIMER        0x00000020
#define AR_ISR_S5_GENTIMER_TRIG     0x0000FF80
#define AR_ISR_S5_GENTIMER_TRIG_S   0
#define AR_ISR_S5_GENTIMER_THRESH   0xFF800000
#define AR_ISR_S5_GENTIMER_THRESH_S 16
#define AR_IMR_S5_GENTIMER_TRIG     0x0000FF80
#define AR_IMR_S5_GENTIMER_TRIG_S   0
#define AR_IMR_S5_GENTIMER_THRESH   0xFF800000
#define AR_IMR_S5_GENTIMER_THRESH_S 16

#define AR_IMR               0x00a0
#define AR_IMR_RXOK          0x00000001
#define AR_IMR_RXDESC        0x00000002
#define AR_IMR_RXOK_HP	     0x00000001
#define AR_IMR_RXOK_LP	     0x00000002
#define AR_IMR_RXERR         0x00000004
#define AR_IMR_RXNOPKT       0x00000008
#define AR_IMR_RXEOL         0x00000010
#define AR_IMR_RXORN         0x00000020
#define AR_IMR_TXOK          0x00000040
#define AR_IMR_TXDESC        0x00000080
#define AR_IMR_TXERR         0x00000100
#define AR_IMR_TXNOPKT       0x00000200
#define AR_IMR_TXEOL         0x00000400
#define AR_IMR_TXURN         0x00000800
#define AR_IMR_MIB           0x00001000
#define AR_IMR_SWI           0x00002000
#define AR_IMR_RXPHY         0x00004000
#define AR_IMR_RXKCM         0x00008000
#define AR_IMR_SWBA          0x00010000
#define AR_IMR_BRSSI         0x00020000
#define AR_IMR_BMISS         0x00040000
#define AR_IMR_BNR           0x00100000
#define AR_IMR_RXCHIRP       0x00200000
#define AR_IMR_BCNMISC       0x00800000
#define AR_IMR_TIM           0x00800000
#define AR_IMR_QCBROVF       0x02000000
#define AR_IMR_QCBRURN       0x04000000
#define AR_IMR_QTRIG         0x08000000
#define AR_IMR_GENTMR        0x10000000

#define AR_IMR_TXMINTR       0x00080000
#define AR_IMR_RXMINTR       0x01000000
#define AR_IMR_TXINTM        0x40000000
#define AR_IMR_RXINTM        0x80000000

#define AR_IMR_S0               0x00a4
#define AR_IMR_S0_QCU_TXOK      0x000003FF
#define AR_IMR_S0_QCU_TXOK_S    0
#define AR_IMR_S0_QCU_TXDESC    0x03FF0000
#define AR_IMR_S0_QCU_TXDESC_S  16

#define AR_IMR_S1              0x00a8
#define AR_IMR_S1_QCU_TXERR    0x000003FF
#define AR_IMR_S1_QCU_TXERR_S  0
#define AR_IMR_S1_QCU_TXEOL    0x03FF0000
#define AR_IMR_S1_QCU_TXEOL_S  16

#define AR_IMR_S2              0x00ac
#define AR_IMR_S2_QCU_TXURN    0x000003FF
#define AR_IMR_S2_QCU_TXURN_S  0
#define AR_IMR_S2_CST          0x00400000
#define AR_IMR_S2_GTT          0x00800000
#define AR_IMR_S2_TIM          0x01000000
#define AR_IMR_S2_CABEND       0x02000000
#define AR_IMR_S2_DTIMSYNC     0x04000000
#define AR_IMR_S2_BCNTO        0x08000000
#define AR_IMR_S2_CABTO        0x10000000
#define AR_IMR_S2_DTIM         0x20000000
#define AR_IMR_S2_TSFOOR       0x40000000

#define AR_IMR_S3                0x00b0
#define AR_IMR_S3_QCU_QCBROVF    0x000003FF
#define AR_IMR_S3_QCU_QCBRURN    0x03FF0000
#define AR_IMR_S3_QCU_QCBRURN_S  16

#define AR_IMR_S4              0x00b4
#define AR_IMR_S4_QCU_QTRIG    0x000003FF
#define AR_IMR_S4_RESV0        0xFFFFFC00

#define AR_IMR_S5              0x00b8
#define AR_IMR_S5_TIMER_TRIG        0x000000FF
#define AR_IMR_S5_TIMER_THRESH      0x0000FF00


#define AR_ISR_RAC            0x00c0
#define AR_ISR_S0_S           0x00c4
#define AR_ISR_S0_QCU_TXOK      0x000003FF
#define AR_ISR_S0_QCU_TXOK_S    0
#define AR_ISR_S0_QCU_TXDESC    0x03FF0000
#define AR_ISR_S0_QCU_TXDESC_S  16

#define AR_ISR_S1_S           0x00c8
#define AR_ISR_S1_QCU_TXERR    0x000003FF
#define AR_ISR_S1_QCU_TXERR_S  0
#define AR_ISR_S1_QCU_TXEOL    0x03FF0000
#define AR_ISR_S1_QCU_TXEOL_S  16

#define AR_ISR_S2_S           (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)
#define AR_ISR_S3_S           (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)
#define AR_ISR_S4_S           (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)
#define AR_ISR_S5_S           (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)
#define AR_DMADBG_0           0x00e0
#define AR_DMADBG_1           0x00e4
#define AR_DMADBG_2           0x00e8
#define AR_DMADBG_3           0x00ec
#define AR_DMADBG_4           0x00f0
#define AR_DMADBG_5           0x00f4
#define AR_DMADBG_6           0x00f8
#define AR_DMADBG_7           0x00fc

#define AR_NUM_QCU      10
#define AR_QCU_0        0x0001
#define AR_QCU_1        0x0002
#define AR_QCU_2        0x0004
#define AR_QCU_3        0x0008
#define AR_QCU_4        0x0010
#define AR_QCU_5        0x0020
#define AR_QCU_6        0x0040
#define AR_QCU_7        0x0080
#define AR_QCU_8        0x0100
#define AR_QCU_9        0x0200

#define AR_Q0_TXDP           0x0800
#define AR_Q1_TXDP           0x0804
#define AR_Q2_TXDP           0x0808
#define AR_Q3_TXDP           0x080c
#define AR_Q4_TXDP           0x0810
#define AR_Q5_TXDP           0x0814
#define AR_Q6_TXDP           0x0818
#define AR_Q7_TXDP           0x081c
#define AR_Q8_TXDP           0x0820
#define AR_Q9_TXDP           0x0824
#define AR_QTXDP(_i)    (AR_Q0_TXDP + ((_i)<<2))

#define AR_Q_STATUS_RING_START	0x830
#define AR_Q_STATUS_RING_END	0x834

#define AR_Q_TXE             0x0840
#define AR_Q_TXE_M           0x000003FF

#define AR_Q_TXD             0x0880
#define AR_Q_TXD_M           0x000003FF

#define AR_Q0_CBRCFG         0x08c0
#define AR_Q1_CBRCFG         0x08c4
#define AR_Q2_CBRCFG         0x08c8
#define AR_Q3_CBRCFG         0x08cc
#define AR_Q4_CBRCFG         0x08d0
#define AR_Q5_CBRCFG         0x08d4
#define AR_Q6_CBRCFG         0x08d8
#define AR_Q7_CBRCFG         0x08dc
#define AR_Q8_CBRCFG         0x08e0
#define AR_Q9_CBRCFG         0x08e4
#define AR_QCBRCFG(_i)      (AR_Q0_CBRCFG + ((_i)<<2))
#define AR_Q_CBRCFG_INTERVAL     0x00FFFFFF
#define AR_Q_CBRCFG_INTERVAL_S   0
#define AR_Q_CBRCFG_OVF_THRESH   0xFF000000
#define AR_Q_CBRCFG_OVF_THRESH_S 24

#define AR_Q0_RDYTIMECFG         0x0900
#define AR_Q1_RDYTIMECFG         0x0904
#define AR_Q2_RDYTIMECFG         0x0908
#define AR_Q3_RDYTIMECFG         0x090c
#define AR_Q4_RDYTIMECFG         0x0910
#define AR_Q5_RDYTIMECFG         0x0914
#define AR_Q6_RDYTIMECFG         0x0918
#define AR_Q7_RDYTIMECFG         0x091c
#define AR_Q8_RDYTIMECFG         0x0920
#define AR_Q9_RDYTIMECFG         0x0924
#define AR_QRDYTIMECFG(_i)       (AR_Q0_RDYTIMECFG + ((_i)<<2))
#define AR_Q_RDYTIMECFG_DURATION   0x00FFFFFF
#define AR_Q_RDYTIMECFG_DURATION_S 0
#define AR_Q_RDYTIMECFG_EN         0x01000000

#define AR_Q_ONESHOTARM_SC       0x0940
#define AR_Q_ONESHOTARM_SC_M     0x000003FF
#define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00

#define AR_Q_ONESHOTARM_CC       0x0980
#define AR_Q_ONESHOTARM_CC_M     0x000003FF
#define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00

#define AR_Q0_MISC         0x09c0
#define AR_Q1_MISC         0x09c4
#define AR_Q2_MISC         0x09c8
#define AR_Q3_MISC         0x09cc
#define AR_Q4_MISC         0x09d0
#define AR_Q5_MISC         0x09d4
#define AR_Q6_MISC         0x09d8
#define AR_Q7_MISC         0x09dc
#define AR_Q8_MISC         0x09e0
#define AR_Q9_MISC         0x09e4
#define AR_QMISC(_i)       (AR_Q0_MISC + ((_i)<<2))
#define AR_Q_MISC_FSP                     0x0000000F
#define AR_Q_MISC_FSP_ASAP                0
#define AR_Q_MISC_FSP_CBR                 1
#define AR_Q_MISC_FSP_DBA_GATED           2
#define AR_Q_MISC_FSP_TIM_GATED           3
#define AR_Q_MISC_FSP_BEACON_SENT_GATED   4
#define AR_Q_MISC_FSP_BEACON_RCVD_GATED   5
#define AR_Q_MISC_ONE_SHOT_EN             0x00000010
#define AR_Q_MISC_CBR_INCR_DIS1           0x00000020
#define AR_Q_MISC_CBR_INCR_DIS0           0x00000040
#define AR_Q_MISC_BEACON_USE              0x00000080
#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN   0x00000100
#define AR_Q_MISC_RDYTIME_EXP_POLICY      0x00000200
#define AR_Q_MISC_RESET_CBR_EXP_CTR       0x00000400
#define AR_Q_MISC_DCU_EARLY_TERM_REQ      0x00000800
#define AR_Q_MISC_RESV0                   0xFFFFF000

#define AR_Q0_STS         0x0a00
#define AR_Q1_STS         0x0a04
#define AR_Q2_STS         0x0a08
#define AR_Q3_STS         0x0a0c
#define AR_Q4_STS         0x0a10
#define AR_Q5_STS         0x0a14
#define AR_Q6_STS         0x0a18
#define AR_Q7_STS         0x0a1c
#define AR_Q8_STS         0x0a20
#define AR_Q9_STS         0x0a24
#define AR_QSTS(_i)       (AR_Q0_STS + ((_i)<<2))
#define AR_Q_STS_PEND_FR_CNT          0x00000003
#define AR_Q_STS_RESV0                0x000000FC
#define AR_Q_STS_CBR_EXP_CNT          0x0000FF00
#define AR_Q_STS_RESV1                0xFFFF0000

#define AR_Q_RDYTIMESHDN    0x0a40
#define AR_Q_RDYTIMESHDN_M  0x000003FF

/* MAC Descriptor CRC check */
#define AR_Q_DESC_CRCCHK    0xa44
/* Enable CRC check on the descriptor fetched from host */
#define AR_Q_DESC_CRCCHK_EN 1

#define AR_NUM_DCU      10
#define AR_DCU_0        0x0001
#define AR_DCU_1        0x0002
#define AR_DCU_2        0x0004
#define AR_DCU_3        0x0008
#define AR_DCU_4        0x0010
#define AR_DCU_5        0x0020
#define AR_DCU_6        0x0040
#define AR_DCU_7        0x0080
#define AR_DCU_8        0x0100
#define AR_DCU_9        0x0200

#define AR_D0_QCUMASK     0x1000
#define AR_D1_QCUMASK     0x1004
#define AR_D2_QCUMASK     0x1008
#define AR_D3_QCUMASK     0x100c
#define AR_D4_QCUMASK     0x1010
#define AR_D5_QCUMASK     0x1014
#define AR_D6_QCUMASK     0x1018
#define AR_D7_QCUMASK     0x101c
#define AR_D8_QCUMASK     0x1020
#define AR_D9_QCUMASK     0x1024
#define AR_DQCUMASK(_i)   (AR_D0_QCUMASK + ((_i)<<2))
#define AR_D_QCUMASK         0x000003FF
#define AR_D_QCUMASK_RESV0   0xFFFFFC00

#define AR_D_TXBLK_CMD  0x1038
#define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i))

#define AR_D0_LCL_IFS     0x1040
#define AR_D1_LCL_IFS     0x1044
#define AR_D2_LCL_IFS     0x1048
#define AR_D3_LCL_IFS     0x104c
#define AR_D4_LCL_IFS     0x1050
#define AR_D5_LCL_IFS     0x1054
#define AR_D6_LCL_IFS     0x1058
#define AR_D7_LCL_IFS     0x105c
#define AR_D8_LCL_IFS     0x1060
#define AR_D9_LCL_IFS     0x1064
#define AR_DLCL_IFS(_i)   (AR_D0_LCL_IFS + ((_i)<<2))
#define AR_D_LCL_IFS_CWMIN       0x000003FF
#define AR_D_LCL_IFS_CWMIN_S     0
#define AR_D_LCL_IFS_CWMAX       0x000FFC00
#define AR_D_LCL_IFS_CWMAX_S     10
#define AR_D_LCL_IFS_AIFS        0x0FF00000
#define AR_D_LCL_IFS_AIFS_S      20

#define AR_D_LCL_IFS_RESV0    0xF0000000

#define AR_D0_RETRY_LIMIT     0x1080
#define AR_D1_RETRY_LIMIT     0x1084
#define AR_D2_RETRY_LIMIT     0x1088
#define AR_D3_RETRY_LIMIT     0x108c
#define AR_D4_RETRY_LIMIT     0x1090
#define AR_D5_RETRY_LIMIT     0x1094
#define AR_D6_RETRY_LIMIT     0x1098
#define AR_D7_RETRY_LIMIT     0x109c
#define AR_D8_RETRY_LIMIT     0x10a0
#define AR_D9_RETRY_LIMIT     0x10a4
#define AR_DRETRY_LIMIT(_i)   (AR_D0_RETRY_LIMIT + ((_i)<<2))
#define AR_D_RETRY_LIMIT_FR_SH       0x0000000F
#define AR_D_RETRY_LIMIT_FR_SH_S     0
#define AR_D_RETRY_LIMIT_STA_SH      0x00003F00
#define AR_D_RETRY_LIMIT_STA_SH_S    8
#define AR_D_RETRY_LIMIT_STA_LG      0x000FC000
#define AR_D_RETRY_LIMIT_STA_LG_S    14
#define AR_D_RETRY_LIMIT_RESV0       0xFFF00000

#define AR_D0_CHNTIME     0x10c0
#define AR_D1_CHNTIME     0x10c4
#define AR_D2_CHNTIME     0x10c8
#define AR_D3_CHNTIME     0x10cc
#define AR_D4_CHNTIME     0x10d0
#define AR_D5_CHNTIME     0x10d4
#define AR_D6_CHNTIME     0x10d8
#define AR_D7_CHNTIME     0x10dc
#define AR_D8_CHNTIME     0x10e0
#define AR_D9_CHNTIME     0x10e4
#define AR_DCHNTIME(_i)   (AR_D0_CHNTIME + ((_i)<<2))
#define AR_D_CHNTIME_DUR         0x000FFFFF
#define AR_D_CHNTIME_DUR_S       0
#define AR_D_CHNTIME_EN          0x00100000
#define AR_D_CHNTIME_RESV0       0xFFE00000

#define AR_D0_MISC        0x1100
#define AR_D1_MISC        0x1104
#define AR_D2_MISC        0x1108
#define AR_D3_MISC        0x110c
#define AR_D4_MISC        0x1110
#define AR_D5_MISC        0x1114
#define AR_D6_MISC        0x1118
#define AR_D7_MISC        0x111c
#define AR_D8_MISC        0x1120
#define AR_D9_MISC        0x1124
#define AR_DMISC(_i)      (AR_D0_MISC + ((_i)<<2))
#define AR_D_MISC_BKOFF_THRESH        0x0000003F
#define AR_D_MISC_RETRY_CNT_RESET_EN  0x00000040
#define AR_D_MISC_CW_RESET_EN         0x00000080
#define AR_D_MISC_FRAG_WAIT_EN        0x00000100
#define AR_D_MISC_FRAG_BKOFF_EN       0x00000200
#define AR_D_MISC_CW_BKOFF_EN         0x00001000
#define AR_D_MISC_VIR_COL_HANDLING    0x0000C000
#define AR_D_MISC_VIR_COL_HANDLING_S  14
#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0
#define AR_D_MISC_VIR_COL_HANDLING_IGNORE  1
#define AR_D_MISC_BEACON_USE          0x00010000
#define AR_D_MISC_ARB_LOCKOUT_CNTRL   0x00060000
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE     0
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1
#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL   2
#define AR_D_MISC_ARB_LOCKOUT_IGNORE  0x00080000
#define AR_D_MISC_SEQ_NUM_INCR_DIS    0x00100000
#define AR_D_MISC_POST_FR_BKOFF_DIS   0x00200000
#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000
#define AR_D_MISC_BLOWN_IFS_RETRY_EN  0x00800000
#define AR_D_MISC_RESV0               0xFF000000

#define AR_D_SEQNUM      0x1140

#define AR_D_GBL_IFS_SIFS         0x1030
#define AR_D_GBL_IFS_SIFS_M       0x0000FFFF
#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB
#define AR_D_GBL_IFS_SIFS_RESV0   0xFFFFFFFF

#define AR_D_TXBLK_BASE            0x1038
#define AR_D_TXBLK_WRITE_BITMASK    0x0000FFFF
#define AR_D_TXBLK_WRITE_BITMASK_S  0
#define AR_D_TXBLK_WRITE_SLICE      0x000F0000
#define AR_D_TXBLK_WRITE_SLICE_S    16
#define AR_D_TXBLK_WRITE_DCU        0x00F00000
#define AR_D_TXBLK_WRITE_DCU_S      20
#define AR_D_TXBLK_WRITE_COMMAND    0x0F000000
#define AR_D_TXBLK_WRITE_COMMAND_S      24

#define AR_D_GBL_IFS_SLOT         0x1070
#define AR_D_GBL_IFS_SLOT_M       0x0000FFFF
#define AR_D_GBL_IFS_SLOT_RESV0   0xFFFF0000
#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR   0x00000420

#define AR_D_GBL_IFS_EIFS         0x10b0
#define AR_D_GBL_IFS_EIFS_M       0x0000FFFF
#define AR_D_GBL_IFS_EIFS_RESV0   0xFFFF0000
#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR   0x0000A5EB

#define AR_D_GBL_IFS_MISC        0x10f0
#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL        0x00000007
#define AR_D_GBL_IFS_MISC_TURBO_MODE            0x00000008
#define AR_D_GBL_IFS_MISC_USEC_DURATION         0x000FFC00
#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY       0x00300000
#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000
#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN    0x06000000
#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000
#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF        0x10000000

#define AR_D_FPCTL                  0x1230
#define AR_D_FPCTL_DCU              0x0000000F
#define AR_D_FPCTL_DCU_S            0
#define AR_D_FPCTL_PREFETCH_EN      0x00000010
#define AR_D_FPCTL_BURST_PREFETCH   0x00007FE0
#define AR_D_FPCTL_BURST_PREFETCH_S 5

#define AR_D_TXPSE                 0x1270
#define AR_D_TXPSE_CTRL            0x000003FF
#define AR_D_TXPSE_RESV0           0x0000FC00
#define AR_D_TXPSE_STATUS          0x00010000
#define AR_D_TXPSE_RESV1           0xFFFE0000

#define AR_D_TXSLOTMASK            0x12f0
#define AR_D_TXSLOTMASK_NUM        0x0000000F

#define AR_CFG_LED                     0x1f04
#define AR_CFG_SCLK_RATE_IND           0x00000003
#define AR_CFG_SCLK_RATE_IND_S         0
#define AR_CFG_SCLK_32MHZ              0x00000000
#define AR_CFG_SCLK_4MHZ               0x00000001
#define AR_CFG_SCLK_1MHZ               0x00000002
#define AR_CFG_SCLK_32KHZ              0x00000003
#define AR_CFG_LED_BLINK_SLOW          0x00000008
#define AR_CFG_LED_BLINK_THRESH_SEL    0x00000070
#define AR_CFG_LED_MODE_SEL            0x00000380
#define AR_CFG_LED_MODE_SEL_S          7
#define AR_CFG_LED_POWER               0x00000280
#define AR_CFG_LED_POWER_S             7
#define AR_CFG_LED_NETWORK             0x00000300
#define AR_CFG_LED_NETWORK_S           7
#define AR_CFG_LED_MODE_PROP           0x0
#define AR_CFG_LED_MODE_RPROP          0x1
#define AR_CFG_LED_MODE_SPLIT          0x2
#define AR_CFG_LED_MODE_RAND           0x3
#define AR_CFG_LED_MODE_POWER_OFF      0x4
#define AR_CFG_LED_MODE_POWER_ON       0x5
#define AR_CFG_LED_MODE_NETWORK_OFF    0x4
#define AR_CFG_LED_MODE_NETWORK_ON     0x6
#define AR_CFG_LED_ASSOC_CTL           0x00000c00
#define AR_CFG_LED_ASSOC_CTL_S         10
#define AR_CFG_LED_ASSOC_NONE          0x0
#define AR_CFG_LED_ASSOC_ACTIVE        0x1
#define AR_CFG_LED_ASSOC_PENDING       0x2

#define AR_CFG_LED_BLINK_SLOW          0x00000008
#define AR_CFG_LED_BLINK_SLOW_S        3

#define AR_CFG_LED_BLINK_THRESH_SEL    0x00000070
#define AR_CFG_LED_BLINK_THRESH_SEL_S  4

#define AR_MAC_SLEEP                0x1f00
#define AR_MAC_SLEEP_MAC_AWAKE      0x00000000
#define AR_MAC_SLEEP_MAC_ASLEEP     0x00000001

#define AR_RC                0x4000
#define AR_RC_AHB            0x00000001
#define AR_RC_APB            0x00000002
#define AR_RC_HOSTIF         0x00000100

#define AR_WA			(AR_SREV_9340(ah) ? 0x40c4 : 0x4004)
#define AR_WA_BIT6			(1 << 6)
#define AR_WA_BIT7			(1 << 7)
#define AR_WA_BIT23			(1 << 23)
#define AR_WA_D3_L1_DISABLE		(1 << 14)
#define AR_WA_D3_TO_L1_DISABLE_REAL     (1 << 16)
#define AR_WA_ASPM_TIMER_BASED_DISABLE  (1 << 17)
#define AR_WA_RESET_EN                  (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */
#define AR_WA_ANALOG_SHIFT              (1 << 20)
#define AR_WA_POR_SHORT                 (1 << 21) /* PCI-E Phy reset control */
#define AR_WA_BIT22			(1 << 22)
#define AR9285_WA_DEFAULT		0x004a050b
#define AR9280_WA_DEFAULT           	0x0040073b
#define AR_WA_DEFAULT               	0x0000073f


#define AR_PM_STATE                 0x4008
#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000

#define AR_HOST_TIMEOUT             (AR_SREV_9340(ah) ? 0x4008 : 0x4018)
#define AR_HOST_TIMEOUT_APB_CNTR    0x0000FFFF
#define AR_HOST_TIMEOUT_APB_CNTR_S  0
#define AR_HOST_TIMEOUT_LCL_CNTR    0xFFFF0000
#define AR_HOST_TIMEOUT_LCL_CNTR_S  16

#define AR_EEPROM                0x401c
#define AR_EEPROM_ABSENT         0x00000100
#define AR_EEPROM_CORRUPT        0x00000200
#define AR_EEPROM_PROT_MASK      0x03FFFC00
#define AR_EEPROM_PROT_MASK_S    10

#define EEPROM_PROTECT_RP_0_31        0x0001
#define EEPROM_PROTECT_WP_0_31        0x0002
#define EEPROM_PROTECT_RP_32_63       0x0004
#define EEPROM_PROTECT_WP_32_63       0x0008
#define EEPROM_PROTECT_RP_64_127      0x0010
#define EEPROM_PROTECT_WP_64_127      0x0020
#define EEPROM_PROTECT_RP_128_191     0x0040
#define EEPROM_PROTECT_WP_128_191     0x0080
#define EEPROM_PROTECT_RP_192_255     0x0100
#define EEPROM_PROTECT_WP_192_255     0x0200
#define EEPROM_PROTECT_RP_256_511     0x0400
#define EEPROM_PROTECT_WP_256_511     0x0800
#define EEPROM_PROTECT_RP_512_1023    0x1000
#define EEPROM_PROTECT_WP_512_1023    0x2000
#define EEPROM_PROTECT_RP_1024_2047   0x4000
#define EEPROM_PROTECT_WP_1024_2047   0x8000

#define AR_SREV \
	((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \
					? 0x400c : 0x4020))

#define AR_SREV_ID \
	((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
#define AR_SREV_VERSION                       0x000000F0
#define AR_SREV_VERSION_S                     4
#define AR_SREV_REVISION                      0x00000007

#define AR_SREV_ID2                           0xFFFFFFFF
#define AR_SREV_VERSION2        	      0xFFFC0000
#define AR_SREV_VERSION2_S                    18
#define AR_SREV_TYPE2        	      	      0x0003F000
#define AR_SREV_TYPE2_S                       12
#define AR_SREV_TYPE2_CHAIN		      0x00001000
#define AR_SREV_TYPE2_HOST_MODE		      0x00002000
#define AR_SREV_REVISION2        	      0x00000F00
#define AR_SREV_REVISION2_S     	      8

#define AR_SREV_VERSION_5416_PCI	0xD
#define AR_SREV_VERSION_5416_PCIE	0xC
#define AR_SREV_REVISION_5416_10	0
#define AR_SREV_REVISION_5416_20	1
#define AR_SREV_REVISION_5416_22	2
#define AR_SREV_VERSION_9100		0x14
#define AR_SREV_VERSION_9160		0x40
#define AR_SREV_REVISION_9160_10	0
#define AR_SREV_REVISION_9160_11	1
#define AR_SREV_VERSION_9280		0x80
#define AR_SREV_REVISION_9280_10	0
#define AR_SREV_REVISION_9280_20	1
#define AR_SREV_REVISION_9280_21	2
#define AR_SREV_VERSION_9285		0xC0
#define AR_SREV_REVISION_9285_10	0
#define AR_SREV_REVISION_9285_11	1
#define AR_SREV_REVISION_9285_12	2
#define AR_SREV_VERSION_9287		0x180
#define AR_SREV_REVISION_9287_10	0
#define AR_SREV_REVISION_9287_11	1
#define AR_SREV_REVISION_9287_12	2
#define AR_SREV_REVISION_9287_13	3
#define AR_SREV_VERSION_9271		0x140
#define AR_SREV_REVISION_9271_10	0
#define AR_SREV_REVISION_9271_11	1
#define AR_SREV_VERSION_9300		0x1c0
#define AR_SREV_REVISION_9300_20	2 /* 2.0 and 2.1 */
#define AR_SREV_VERSION_9485		0x240
#define AR_SREV_REVISION_9485_10	0
#define AR_SREV_REVISION_9485_11        1
#define AR_SREV_VERSION_9340		0x300

#define AR_SREV_5416(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
	 ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE))
#define AR_SREV_5416_20_OR_LATER(_ah) \
	(((AR_SREV_5416(_ah)) && \
	 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_20)) || \
	 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))
#define AR_SREV_5416_22_OR_LATER(_ah) \
	(((AR_SREV_5416(_ah)) && \
	 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \
	 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))

#define AR_SREV_9100(ah) \
	((ah->hw_version.macVersion) == AR_SREV_VERSION_9100)
#define AR_SREV_9100_OR_LATER(_ah) \
	(((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))

#define AR_SREV_9160(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160))
#define AR_SREV_9160_10_OR_LATER(_ah) \
	(((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160))
#define AR_SREV_9160_11(_ah) \
	(AR_SREV_9160(_ah) && \
	 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11))
#define AR_SREV_9280(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
#define AR_SREV_9280_20_OR_LATER(_ah) \
	(((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280))
#define AR_SREV_9280_20(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))

#define AR_SREV_9285(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285))
#define AR_SREV_9285_12_OR_LATER(_ah) \
	(((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))

#define AR_SREV_9287(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287))
#define AR_SREV_9287_11_OR_LATER(_ah) \
	(((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287))
#define AR_SREV_9287_11(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
	 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11))
#define AR_SREV_9287_12(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
	 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12))
#define AR_SREV_9287_12_OR_LATER(_ah) \
	(((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
	 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
	  ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12)))
#define AR_SREV_9287_13_OR_LATER(_ah) \
	(((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
	 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
	  ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13)))

#define AR_SREV_9271(_ah) \
    (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271)
#define AR_SREV_9271_10(_ah) \
    (AR_SREV_9271(_ah) && \
     ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10))
#define AR_SREV_9271_11(_ah) \
    (AR_SREV_9271(_ah) && \
     ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))

#define AR_SREV_9300(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
#define AR_SREV_9300_20_OR_LATER(_ah) \
	((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)

#define AR_SREV_9485(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))
#define AR_SREV_9485_10(_ah) \
	(AR_SREV_9485(_ah) && \
	 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10))
#define AR_SREV_9485_11(_ah) \
	(AR_SREV_9485(_ah) && \
	 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11))
#define AR_SREV_9485_OR_LATER(_ah) \
	(((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))

#define AR_SREV_9340(_ah) \
	(((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))

#define AR_SREV_9285E_20(_ah) \
    (AR_SREV_9285_12_OR_LATER(_ah) && \
     ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))

enum ath_usb_dev {
	AR9280_USB = 1, /* AR7010 + AR9280, UB94 */
	AR9287_USB = 2, /* AR7010 + AR9287, UB95 */
	STORAGE_DEVICE = 3,
};

#define AR_DEVID_7010(_ah) \
	(((_ah)->hw_version.usbdev == AR9280_USB) || \
	 ((_ah)->hw_version.usbdev == AR9287_USB))

#define AR_RADIO_SREV_MAJOR                   0xf0
#define AR_RAD5133_SREV_MAJOR                 0xc0
#define AR_RAD2133_SREV_MAJOR                 0xd0
#define AR_RAD5122_SREV_MAJOR                 0xe0
#define AR_RAD2122_SREV_MAJOR                 0xf0

#define AR_AHB_MODE                           0x4024
#define AR_AHB_EXACT_WR_EN                    0x00000000
#define AR_AHB_BUF_WR_EN                      0x00000001
#define AR_AHB_EXACT_RD_EN                    0x00000000
#define AR_AHB_CACHELINE_RD_EN                0x00000002
#define AR_AHB_PREFETCH_RD_EN                 0x00000004
#define AR_AHB_PAGE_SIZE_1K                   0x00000000
#define AR_AHB_PAGE_SIZE_2K                   0x00000008
#define AR_AHB_PAGE_SIZE_4K                   0x00000010
#define AR_AHB_CUSTOM_BURST_EN                0x000000C0
#define AR_AHB_CUSTOM_BURST_EN_S              6
#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL    3

#define AR_INTR_RTC_IRQ                       0x00000001
#define AR_INTR_MAC_IRQ                       0x00000002
#define AR_INTR_EEP_PROT_ACCESS               0x00000004
#define AR_INTR_MAC_AWAKE                     0x00020000
#define AR_INTR_MAC_ASLEEP                    0x00040000
#define AR_INTR_SPURIOUS                      0xFFFFFFFF


#define AR_INTR_SYNC_CAUSE                    (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
#define AR_INTR_SYNC_CAUSE_CLR                (AR_SREV_9340(ah) ? 0x4010 : 0x4028)


#define AR_INTR_SYNC_ENABLE                   (AR_SREV_9340(ah) ? 0x4014 : 0x402c)
#define AR_INTR_SYNC_ENABLE_GPIO              0xFFFC0000
#define AR_INTR_SYNC_ENABLE_GPIO_S            18

enum {
	AR_INTR_SYNC_RTC_IRQ = 0x00000001,
	AR_INTR_SYNC_MAC_IRQ = 0x00000002,
	AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004,
	AR_INTR_SYNC_APB_TIMEOUT = 0x00000008,
	AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010,
	AR_INTR_SYNC_HOST1_FATAL = 0x00000020,
	AR_INTR_SYNC_HOST1_PERR = 0x00000040,
	AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080,
	AR_INTR_SYNC_RADM_CPL_EP = 0x00000100,
	AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200,
	AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400,
	AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800,
	AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000,
	AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000,
	AR_INTR_SYNC_PM_ACCESS = 0x00004000,
	AR_INTR_SYNC_MAC_AWAKE = 0x00008000,
	AR_INTR_SYNC_MAC_ASLEEP = 0x00010000,
	AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000,
	AR_INTR_SYNC_ALL = 0x0003FFFF,


	AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL |
				AR_INTR_SYNC_HOST1_PERR |
				AR_INTR_SYNC_RADM_CPL_EP |
				AR_INTR_SYNC_RADM_CPL_DLLP_ABORT |
				AR_INTR_SYNC_RADM_CPL_TLP_ABORT |
				AR_INTR_SYNC_RADM_CPL_ECRC_ERR |
				AR_INTR_SYNC_RADM_CPL_TIMEOUT |
				AR_INTR_SYNC_LOCAL_TIMEOUT |
				AR_INTR_SYNC_MAC_SLEEP_ACCESS),

	AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF,

};

#define AR_INTR_ASYNC_MASK                       (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
#define AR_INTR_ASYNC_MASK_GPIO                  0xFFFC0000
#define AR_INTR_ASYNC_MASK_GPIO_S                18

#define AR_INTR_SYNC_MASK                        (AR_SREV_9340(ah) ? 0x401c : 0x4034)
#define AR_INTR_SYNC_MASK_GPIO                   0xFFFC0000
#define AR_INTR_SYNC_MASK_GPIO_S                 18

#define AR_INTR_ASYNC_CAUSE_CLR                  (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
#define AR_INTR_ASYNC_CAUSE                      (AR_SREV_9340(ah) ? 0x4020 : 0x4038)

#define AR_INTR_ASYNC_ENABLE                     (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
#define AR_INTR_ASYNC_ENABLE_GPIO                0xFFFC0000
#define AR_INTR_ASYNC_ENABLE_GPIO_S              18

#define AR_PCIE_SERDES                           0x4040
#define AR_PCIE_SERDES2                          0x4044
#define AR_PCIE_PM_CTRL                          (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
#define AR_PCIE_PM_CTRL_ENA                      0x00080000

#define AR_NUM_GPIO                              14
#define AR928X_NUM_GPIO                          10
#define AR9285_NUM_GPIO                          12
#define AR9287_NUM_GPIO                          11
#define AR9271_NUM_GPIO                          16
#define AR9300_NUM_GPIO                          17
#define AR7010_NUM_GPIO                          16

#define AR_GPIO_IN_OUT                           (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
#define AR_GPIO_IN_VAL                           0x0FFFC000
#define AR_GPIO_IN_VAL_S                         14
#define AR928X_GPIO_IN_VAL                       0x000FFC00
#define AR928X_GPIO_IN_VAL_S                     10
#define AR9285_GPIO_IN_VAL                       0x00FFF000
#define AR9285_GPIO_IN_VAL_S                     12
#define AR9287_GPIO_IN_VAL                       0x003FF800
#define AR9287_GPIO_IN_VAL_S                     11
#define AR9271_GPIO_IN_VAL                       0xFFFF0000
#define AR9271_GPIO_IN_VAL_S                     16
#define AR7010_GPIO_IN_VAL                       0x0000FFFF
#define AR7010_GPIO_IN_VAL_S                     0

#define AR_GPIO_IN				 (AR_SREV_9340(ah) ? 0x402c : 0x404c)
#define AR9300_GPIO_IN_VAL                       0x0001FFFF
#define AR9300_GPIO_IN_VAL_S                     0

#define AR_GPIO_OE_OUT                           (AR_SREV_9340(ah) ? 0x4030 : \
						  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c))
#define AR_GPIO_OE_OUT_DRV                       0x3
#define AR_GPIO_OE_OUT_DRV_NO                    0x0
#define AR_GPIO_OE_OUT_DRV_LOW                   0x1
#define AR_GPIO_OE_OUT_DRV_HI                    0x2
#define AR_GPIO_OE_OUT_DRV_ALL                   0x3

#define AR7010_GPIO_OE                           0x52000
#define AR7010_GPIO_OE_MASK                      0x1
#define AR7010_GPIO_OE_AS_OUTPUT                 0x0
#define AR7010_GPIO_OE_AS_INPUT                  0x1
#define AR7010_GPIO_IN                           0x52004
#define AR7010_GPIO_OUT                          0x52008
#define AR7010_GPIO_SET                          0x5200C
#define AR7010_GPIO_CLEAR                        0x52010
#define AR7010_GPIO_INT                          0x52014
#define AR7010_GPIO_INT_TYPE                     0x52018
#define AR7010_GPIO_INT_POLARITY                 0x5201C
#define AR7010_GPIO_PENDING                      0x52020
#define AR7010_GPIO_INT_MASK                     0x52024
#define AR7010_GPIO_FUNCTION                     0x52028

#define AR_GPIO_INTR_POL                         (AR_SREV_9340(ah) ? 0x4038 : \
						  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050))
#define AR_GPIO_INTR_POL_VAL                     0x0001FFFF
#define AR_GPIO_INTR_POL_VAL_S                   0

#define AR_GPIO_INPUT_EN_VAL                     (AR_SREV_9340(ah) ? 0x403c : \
						  (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054))
#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF     0x00000004
#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S       2
#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF    0x00000008
#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S      3
#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF       0x00000010
#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S         4
#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF        0x00000080
#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S      7
#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB      0x00000400
#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S    10
#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB        0x00001000
#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S      12
#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB         0x00008000
#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S       15
#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE        0x00010000
#define AR_GPIO_JTAG_DISABLE                     0x00020000

#define AR_GPIO_INPUT_MUX1                       (AR_SREV_9340(ah) ? 0x4040 : \
						  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058))
#define AR_GPIO_INPUT_MUX1_BT_ACTIVE             0x000f0000
#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S           16
#define AR_GPIO_INPUT_MUX1_BT_PRIORITY           0x00000f00
#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S         8

#define AR_GPIO_INPUT_MUX2                       (AR_SREV_9340(ah) ? 0x4044 : \
						  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c))
#define AR_GPIO_INPUT_MUX2_CLK25                 0x0000000f
#define AR_GPIO_INPUT_MUX2_CLK25_S               0
#define AR_GPIO_INPUT_MUX2_RFSILENT              0x000000f0
#define AR_GPIO_INPUT_MUX2_RFSILENT_S            4
#define AR_GPIO_INPUT_MUX2_RTC_RESET             0x00000f00
#define AR_GPIO_INPUT_MUX2_RTC_RESET_S           8

#define AR_GPIO_OUTPUT_MUX1                      (AR_SREV_9340(ah) ? 0x4048 : \
						  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060))
#define AR_GPIO_OUTPUT_MUX2                      (AR_SREV_9340(ah) ? 0x404c : \
						  (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064))
#define AR_GPIO_OUTPUT_MUX3                      (AR_SREV_9340(ah) ? 0x4050 : \
						  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068))

#define AR_INPUT_STATE                           (AR_SREV_9340(ah) ? 0x4054 : \
						  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c))

#define AR_EEPROM_STATUS_DATA                    (AR_SREV_9340(ah) ? 0x40c8 : \
						  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c))
#define AR_EEPROM_STATUS_DATA_VAL                0x0000ffff
#define AR_EEPROM_STATUS_DATA_VAL_S              0
#define AR_EEPROM_STATUS_DATA_BUSY               0x00010000
#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS        0x00020000
#define AR_EEPROM_STATUS_DATA_PROT_ACCESS        0x00040000
#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS      0x00080000

#define AR_OBS                  (AR_SREV_9340(ah) ? 0x405c : \
				 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080))

#define AR_GPIO_PDPU                             (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)

#define AR_PCIE_MSI                             (AR_SREV_9340(ah) ? 0x40d8 : \
						 (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094))
#define AR_PCIE_MSI_ENABLE                       0x00000001

#define AR_INTR_PRIO_SYNC_ENABLE  (AR_SREV_9340(ah) ? 0x4088 : 0x40c4)
#define AR_INTR_PRIO_ASYNC_MASK   (AR_SREV_9340(ah) ? 0x408c : 0x40c8)
#define AR_INTR_PRIO_SYNC_MASK    (AR_SREV_9340(ah) ? 0x4090 : 0x40cc)
#define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
#define AR_ENT_OTP		  0x40d8
#define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000
#define AR_ENT_OTP_MPSD		0x00800000

#define AR_CH0_BB_DPLL1		 0x16180
#define AR_CH0_BB_DPLL1_REFDIV	 0xF8000000
#define AR_CH0_BB_DPLL1_REFDIV_S 27
#define AR_CH0_BB_DPLL1_NINI	 0x07FC0000
#define AR_CH0_BB_DPLL1_NINI_S	 18
#define AR_CH0_BB_DPLL1_NFRAC	 0x0003FFFF
#define AR_CH0_BB_DPLL1_NFRAC_S	 0

#define AR_CH0_BB_DPLL2		     0x16184
#define AR_CH0_BB_DPLL2_LOCAL_PLL       0x40000000
#define AR_CH0_BB_DPLL2_LOCAL_PLL_S     30
#define AR_CH0_DPLL2_KI              0x3C000000
#define AR_CH0_DPLL2_KI_S            26
#define AR_CH0_DPLL2_KD              0x03F80000
#define AR_CH0_DPLL2_KD_S            19
#define AR_CH0_BB_DPLL2_EN_NEGTRIG   0x00040000
#define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18
#define AR_CH0_BB_DPLL2_PLL_PWD	     0x00010000
#define AR_CH0_BB_DPLL2_PLL_PWD_S    16
#define AR_CH0_BB_DPLL2_OUTDIV	     0x0000E000
#define AR_CH0_BB_DPLL2_OUTDIV_S     13

#define AR_CH0_BB_DPLL3          0x16188
#define AR_CH0_BB_DPLL3_PHASE_SHIFT	0x3F800000
#define AR_CH0_BB_DPLL3_PHASE_SHIFT_S	23

#define AR_CH0_DDR_DPLL2         0x16244
#define AR_CH0_DDR_DPLL3         0x16248
#define AR_CH0_DPLL3_PHASE_SHIFT     0x3F800000
#define AR_CH0_DPLL3_PHASE_SHIFT_S   23
#define AR_PHY_CCA_NOM_VAL_2GHZ      -118

#define AR_RTC_9300_PLL_DIV          0x000003ff
#define AR_RTC_9300_PLL_DIV_S        0
#define AR_RTC_9300_PLL_REFDIV       0x00003C00
#define AR_RTC_9300_PLL_REFDIV_S     10
#define AR_RTC_9300_PLL_CLKSEL       0x0000C000
#define AR_RTC_9300_PLL_CLKSEL_S     14

#define AR_RTC_9160_PLL_DIV	0x000003ff
#define AR_RTC_9160_PLL_DIV_S   0
#define AR_RTC_9160_PLL_REFDIV  0x00003C00
#define AR_RTC_9160_PLL_REFDIV_S 10
#define AR_RTC_9160_PLL_CLKSEL	0x0000C000
#define AR_RTC_9160_PLL_CLKSEL_S 14

#define AR_RTC_BASE             0x00020000
#define AR_RTC_RC \
	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000)
#define AR_RTC_RC_M		0x00000003
#define AR_RTC_RC_MAC_WARM      0x00000001
#define AR_RTC_RC_MAC_COLD      0x00000002
#define AR_RTC_RC_COLD_RESET    0x00000004
#define AR_RTC_RC_WARM_RESET    0x00000008

/* Crystal Control */
#define AR_RTC_XTAL_CONTROL     0x7004

/* Reg Control 0 */
#define AR_RTC_REG_CONTROL0     0x7008

/* Reg Control 1 */
#define AR_RTC_REG_CONTROL1     0x700c
#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM       0x00000001

#define AR_RTC_PLL_CONTROL \
	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)

#define AR_RTC_PLL_CONTROL2	0x703c

#define AR_RTC_PLL_DIV          0x0000001f
#define AR_RTC_PLL_DIV_S        0
#define AR_RTC_PLL_DIV2         0x00000020
#define AR_RTC_PLL_REFDIV_5     0x000000c0
#define AR_RTC_PLL_CLKSEL       0x00000300
#define AR_RTC_PLL_CLKSEL_S     8
#define AR_RTC_PLL_BYPASS	0x00010000

#define PLL3 0x16188
#define PLL3_DO_MEAS_MASK 0x40000000
#define PLL4 0x1618c
#define PLL4_MEAS_DONE    0x8
#define SQSUM_DVC_MASK 0x007ffff8

#define AR_RTC_RESET \
	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
#define AR_RTC_RESET_EN		(0x00000001)

#define AR_RTC_STATUS \
	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)

#define AR_RTC_STATUS_M \
	((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f)

#define AR_RTC_PM_STATUS_M      0x0000000f

#define AR_RTC_STATUS_SHUTDOWN  0x00000001
#define AR_RTC_STATUS_ON        0x00000002
#define AR_RTC_STATUS_SLEEP     0x00000004
#define AR_RTC_STATUS_WAKEUP    0x00000008

#define AR_RTC_SLEEP_CLK \
	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
#define AR_RTC_FORCE_DERIVED_CLK    0x2
#define AR_RTC_FORCE_SWREG_PRD      0x00000004

#define AR_RTC_FORCE_WAKE \
	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
#define AR_RTC_FORCE_WAKE_EN        0x00000001
#define AR_RTC_FORCE_WAKE_ON_INT    0x00000002


#define AR_RTC_INTR_CAUSE \
	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050)

#define AR_RTC_INTR_ENABLE \
	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054)

#define AR_RTC_INTR_MASK \
	((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)

/* RTC_DERIVED_* - only for AR9100 */

#define AR_RTC_DERIVED_CLK \
	(AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)
#define AR_RTC_DERIVED_CLK_PERIOD    0x0000fffe
#define AR_RTC_DERIVED_CLK_PERIOD_S  1

#define	AR_SEQ_MASK	0x8060

#define AR_AN_RF2G1_CH0         0x7810
#define AR_AN_RF2G1_CH0_OB      0x03800000
#define AR_AN_RF2G1_CH0_OB_S    23
#define AR_AN_RF2G1_CH0_DB      0x1C000000
#define AR_AN_RF2G1_CH0_DB_S    26

#define AR_AN_RF5G1_CH0         0x7818
#define AR_AN_RF5G1_CH0_OB5     0x00070000
#define AR_AN_RF5G1_CH0_OB5_S   16
#define AR_AN_RF5G1_CH0_DB5     0x00380000
#define AR_AN_RF5G1_CH0_DB5_S   19

#define AR_AN_RF2G1_CH1         0x7834
#define AR_AN_RF2G1_CH1_OB      0x03800000
#define AR_AN_RF2G1_CH1_OB_S    23
#define AR_AN_RF2G1_CH1_DB      0x1C000000
#define AR_AN_RF2G1_CH1_DB_S    26

#define AR_AN_RF5G1_CH1         0x783C
#define AR_AN_RF5G1_CH1_OB5     0x00070000
#define AR_AN_RF5G1_CH1_OB5_S   16
#define AR_AN_RF5G1_CH1_DB5     0x00380000
#define AR_AN_RF5G1_CH1_DB5_S   19

#define AR_AN_TOP1                  0x7890
#define AR_AN_TOP1_DACIPMODE	    0x00040000
#define AR_AN_TOP1_DACIPMODE_S	    18

#define AR_AN_TOP2                  0x7894
#define AR_AN_TOP2_XPABIAS_LVL      0xC0000000
#define AR_AN_TOP2_XPABIAS_LVL_S    30
#define AR_AN_TOP2_LOCALBIAS        0x00200000
#define AR_AN_TOP2_LOCALBIAS_S      21
#define AR_AN_TOP2_PWDCLKIND        0x00400000
#define AR_AN_TOP2_PWDCLKIND_S      22

#define AR_AN_SYNTH9            0x7868
#define AR_AN_SYNTH9_REFDIVA    0xf8000000
#define AR_AN_SYNTH9_REFDIVA_S  27

#define AR9285_AN_RF2G1              0x7820
#define AR9285_AN_RF2G1_ENPACAL      0x00000800
#define AR9285_AN_RF2G1_ENPACAL_S    11
#define AR9285_AN_RF2G1_PDPADRV1     0x02000000
#define AR9285_AN_RF2G1_PDPADRV1_S   25
#define AR9285_AN_RF2G1_PDPADRV2     0x01000000
#define AR9285_AN_RF2G1_PDPADRV2_S   24
#define AR9285_AN_RF2G1_PDPAOUT      0x00800000
#define AR9285_AN_RF2G1_PDPAOUT_S    23


#define AR9285_AN_RF2G2              0x7824
#define AR9285_AN_RF2G2_OFFCAL       0x00001000
#define AR9285_AN_RF2G2_OFFCAL_S     12

#define AR9285_AN_RF2G3             0x7828
#define AR9285_AN_RF2G3_PDVCCOMP    0x02000000
#define AR9285_AN_RF2G3_PDVCCOMP_S  25
#define AR9285_AN_RF2G3_OB_0    0x00E00000
#define AR9285_AN_RF2G3_OB_0_S    21
#define AR9285_AN_RF2G3_OB_1    0x001C0000
#define AR9285_AN_RF2G3_OB_1_S    18
#define AR9285_AN_RF2G3_OB_2    0x00038000
#define AR9285_AN_RF2G3_OB_2_S    15
#define AR9285_AN_RF2G3_OB_3    0x00007000
#define AR9285_AN_RF2G3_OB_3_S    12
#define AR9285_AN_RF2G3_OB_4    0x00000E00
#define AR9285_AN_RF2G3_OB_4_S    9

#define AR9285_AN_RF2G3_DB1_0    0x000001C0
#define AR9285_AN_RF2G3_DB1_0_S    6
#define AR9285_AN_RF2G3_DB1_1    0x00000038
#define AR9285_AN_RF2G3_DB1_1_S    3
#define AR9285_AN_RF2G3_DB1_2    0x00000007
#define AR9285_AN_RF2G3_DB1_2_S    0
#define AR9285_AN_RF2G4         0x782C
#define AR9285_AN_RF2G4_DB1_3    0xE0000000
#define AR9285_AN_RF2G4_DB1_3_S    29
#define AR9285_AN_RF2G4_DB1_4    0x1C000000
#define AR9285_AN_RF2G4_DB1_4_S    26

#define AR9285_AN_RF2G4_DB2_0    0x03800000
#define AR9285_AN_RF2G4_DB2_0_S    23
#define AR9285_AN_RF2G4_DB2_1    0x00700000
#define AR9285_AN_RF2G4_DB2_1_S    20
#define AR9285_AN_RF2G4_DB2_2    0x000E0000
#define AR9285_AN_RF2G4_DB2_2_S    17
#define AR9285_AN_RF2G4_DB2_3    0x0001C000
#define AR9285_AN_RF2G4_DB2_3_S    14
#define AR9285_AN_RF2G4_DB2_4    0x00003800
#define AR9285_AN_RF2G4_DB2_4_S    11

#define AR9285_RF2G5			0x7830
#define AR9285_RF2G5_IC50TX		0xfffff8ff
#define AR9285_RF2G5_IC50TX_SET		0x00000400
#define AR9285_RF2G5_IC50TX_XE_SET	0x00000500
#define AR9285_RF2G5_IC50TX_CLEAR	0x00000700
#define AR9285_RF2G5_IC50TX_CLEAR_S	8

/* AR9271 : 0x7828, 0x782c different setting from AR9285 */
#define AR9271_AN_RF2G3_OB_cck		0x001C0000
#define AR9271_AN_RF2G3_OB_cck_S	18
#define AR9271_AN_RF2G3_OB_psk		0x00038000
#define AR9271_AN_RF2G3_OB_psk_S	15
#define AR9271_AN_RF2G3_OB_qam		0x00007000
#define AR9271_AN_RF2G3_OB_qam_S	12

#define AR9271_AN_RF2G3_DB_1		0x00E00000
#define AR9271_AN_RF2G3_DB_1_S		21

#define AR9271_AN_RF2G3_CCOMP		0xFFF
#define AR9271_AN_RF2G3_CCOMP_S		0

#define AR9271_AN_RF2G4_DB_2		0xE0000000
#define AR9271_AN_RF2G4_DB_2_S		29

#define AR9285_AN_RF2G6                 0x7834
#define AR9285_AN_RF2G6_CCOMP           0x00007800
#define AR9285_AN_RF2G6_CCOMP_S         11
#define AR9285_AN_RF2G6_OFFS            0x03f00000
#define AR9285_AN_RF2G6_OFFS_S          20

#define AR9271_AN_RF2G6_OFFS            0x07f00000
#define AR9271_AN_RF2G6_OFFS_S            20

#define AR9285_AN_RF2G7                 0x7838
#define AR9285_AN_RF2G7_PWDDB           0x00000002
#define AR9285_AN_RF2G7_PWDDB_S         1
#define AR9285_AN_RF2G7_PADRVGN2TAB0    0xE0000000
#define AR9285_AN_RF2G7_PADRVGN2TAB0_S  29

#define AR9285_AN_RF2G8                  0x783C
#define AR9285_AN_RF2G8_PADRVGN2TAB0     0x0001C000
#define AR9285_AN_RF2G8_PADRVGN2TAB0_S   14


#define AR9285_AN_RF2G9          0x7840
#define AR9285_AN_RXTXBB1              0x7854
#define AR9285_AN_RXTXBB1_PDRXTXBB1    0x00000020
#define AR9285_AN_RXTXBB1_PDRXTXBB1_S  5
#define AR9285_AN_RXTXBB1_PDV2I        0x00000080
#define AR9285_AN_RXTXBB1_PDV2I_S      7
#define AR9285_AN_RXTXBB1_PDDACIF      0x00000100
#define AR9285_AN_RXTXBB1_PDDACIF_S    8
#define AR9285_AN_RXTXBB1_SPARE9       0x00000001
#define AR9285_AN_RXTXBB1_SPARE9_S     0

#define AR9285_AN_TOP2           0x7868

#define AR9285_AN_TOP3                  0x786c
#define AR9285_AN_TOP3_XPABIAS_LVL      0x0000000C
#define AR9285_AN_TOP3_XPABIAS_LVL_S    2
#define AR9285_AN_TOP3_PWDDAC           0x00800000
#define AR9285_AN_TOP3_PWDDAC_S    23

#define AR9285_AN_TOP4           0x7870
#define AR9285_AN_TOP4_DEFAULT   0x10142c00

#define AR9287_AN_RF2G3_CH0             0x7808
#define AR9287_AN_RF2G3_CH1             0x785c
#define AR9287_AN_RF2G3_DB1             0xE0000000
#define AR9287_AN_RF2G3_DB1_S           29
#define AR9287_AN_RF2G3_DB2             0x1C000000
#define AR9287_AN_RF2G3_DB2_S           26
#define AR9287_AN_RF2G3_OB_CCK          0x03800000
#define AR9287_AN_RF2G3_OB_CCK_S        23
#define AR9287_AN_RF2G3_OB_PSK          0x00700000
#define AR9287_AN_RF2G3_OB_PSK_S        20
#define AR9287_AN_RF2G3_OB_QAM          0x000E0000
#define AR9287_AN_RF2G3_OB_QAM_S        17
#define AR9287_AN_RF2G3_OB_PAL_OFF      0x0001C000
#define AR9287_AN_RF2G3_OB_PAL_OFF_S    14

#define AR9287_AN_TXPC0                 0x7898
#define AR9287_AN_TXPC0_TXPCMODE        0x0000C000
#define AR9287_AN_TXPC0_TXPCMODE_S      14
#define AR9287_AN_TXPC0_TXPCMODE_NORMAL    0
#define AR9287_AN_TXPC0_TXPCMODE_TEST      1
#define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2
#define AR9287_AN_TXPC0_TXPCMODE_ATBTEST   3

#define AR9287_AN_TOP2                  0x78b4
#define AR9287_AN_TOP2_XPABIAS_LVL      0xC0000000
#define AR9287_AN_TOP2_XPABIAS_LVL_S    30

/* AR9271 specific stuff */
#define AR9271_RESET_POWER_DOWN_CONTROL		0x50044
#define AR9271_RADIO_RF_RST			0x20
#define AR9271_GATE_MAC_CTL			0x4000

#define AR_STA_ID0                 0x8000
#define AR_STA_ID1                 0x8004
#define AR_STA_ID1_SADH_MASK       0x0000FFFF
#define AR_STA_ID1_STA_AP          0x00010000
#define AR_STA_ID1_ADHOC           0x00020000
#define AR_STA_ID1_PWR_SAV         0x00040000
#define AR_STA_ID1_KSRCHDIS        0x00080000
#define AR_STA_ID1_PCF             0x00100000
#define AR_STA_ID1_USE_DEFANT      0x00200000
#define AR_STA_ID1_DEFANT_UPDATE   0x00400000
#define AR_STA_ID1_AR9100_BA_FIX   0x00400000
#define AR_STA_ID1_RTS_USE_DEF     0x00800000
#define AR_STA_ID1_ACKCTS_6MB      0x01000000
#define AR_STA_ID1_BASE_RATE_11B   0x02000000
#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000
#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000
#define AR_STA_ID1_KSRCH_MODE      0x10000000
#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000
#define AR_STA_ID1_CBCIV_ENDIAN    0x40000000
#define AR_STA_ID1_MCAST_KSRCH     0x80000000

#define AR_BSS_ID0          0x8008
#define AR_BSS_ID1          0x800C
#define AR_BSS_ID1_U16       0x0000FFFF
#define AR_BSS_ID1_AID       0x07FF0000
#define AR_BSS_ID1_AID_S     16

#define AR_BCN_RSSI_AVE      0x8010
#define AR_BCN_RSSI_AVE_MASK 0x00000FFF

#define AR_TIME_OUT         0x8014
#define AR_TIME_OUT_ACK      0x00003FFF
#define AR_TIME_OUT_ACK_S    0
#define AR_TIME_OUT_CTS      0x3FFF0000
#define AR_TIME_OUT_CTS_S    16
#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR    0x16001D56

#define AR_RSSI_THR          0x8018
#define AR_RSSI_THR_MASK     0x000000FF
#define AR_RSSI_THR_BM_THR   0x0000FF00
#define AR_RSSI_THR_BM_THR_S 8
#define AR_RSSI_BCN_WEIGHT   0x1F000000
#define AR_RSSI_BCN_WEIGHT_S 24
#define AR_RSSI_BCN_RSSI_RST 0x20000000

#define AR_USEC              0x801c
#define AR_USEC_USEC         0x0000007F
#define AR_USEC_TX_LAT       0x007FC000
#define AR_USEC_TX_LAT_S     14
#define AR_USEC_RX_LAT       0x1F800000
#define AR_USEC_RX_LAT_S     23
#define AR_USEC_ASYNC_FIFO_DUR    0x12e00074

#define AR_RESET_TSF        0x8020
#define AR_RESET_TSF_ONCE   0x01000000

#define AR_MAX_CFP_DUR      0x8038
#define AR_CFP_VAL          0x0000FFFF

#define AR_RX_FILTER        0x803C

#define AR_MCAST_FIL0       0x8040
#define AR_MCAST_FIL1       0x8044

/*
 * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes.
 *
 * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with
 * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down
 * receive. The force RX abort bit will kill any frame which is currently being
 * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS)
 * will prevent any new frames from getting started.
 */
#define AR_DIAG_SW                  0x8048
#define AR_DIAG_CACHE_ACK           0x00000001
#define AR_DIAG_ACK_DIS             0x00000002
#define AR_DIAG_CTS_DIS             0x00000004
#define AR_DIAG_ENCRYPT_DIS         0x00000008
#define AR_DIAG_DECRYPT_DIS         0x00000010
#define AR_DIAG_RX_DIS              0x00000020 /* RX block */
#define AR_DIAG_LOOP_BACK           0x00000040
#define AR_DIAG_CORR_FCS            0x00000080
#define AR_DIAG_CHAN_INFO           0x00000100
#define AR_DIAG_SCRAM_SEED          0x0001FE00
#define AR_DIAG_SCRAM_SEED_S        8
#define AR_DIAG_FRAME_NV0           0x00020000
#define AR_DIAG_OBS_PT_SEL1         0x000C0000
#define AR_DIAG_OBS_PT_SEL1_S       18
#define AR_DIAG_FORCE_RX_CLEAR      0x00100000 /* force rx_clear high */
#define AR_DIAG_IGNORE_VIRT_CS      0x00200000
#define AR_DIAG_FORCE_CH_IDLE_HIGH  0x00400000
#define AR_DIAG_EIFS_CTRL_ENA       0x00800000
#define AR_DIAG_DUAL_CHAIN_INFO     0x01000000
#define AR_DIAG_RX_ABORT            0x02000000 /* Force RX abort */
#define AR_DIAG_SATURATE_CYCLE_CNT  0x04000000
#define AR_DIAG_OBS_PT_SEL2         0x08000000
#define AR_DIAG_RX_CLEAR_CTL_LOW    0x10000000
#define AR_DIAG_RX_CLEAR_EXT_LOW    0x20000000

#define AR_TSF_L32          0x804c
#define AR_TSF_U32          0x8050

#define AR_TST_ADDAC        0x8054
#define AR_DEF_ANTENNA      0x8058

#define AR_AES_MUTE_MASK0       0x805c
#define AR_AES_MUTE_MASK0_FC    0x0000FFFF
#define AR_AES_MUTE_MASK0_QOS   0xFFFF0000
#define AR_AES_MUTE_MASK0_QOS_S 16

#define AR_AES_MUTE_MASK1       0x8060
#define AR_AES_MUTE_MASK1_SEQ   0x0000FFFF
#define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000
#define AR_AES_MUTE_MASK1_FC_MGMT_S 16

#define AR_GATED_CLKS       0x8064
#define AR_GATED_CLKS_TX    0x00000002
#define AR_GATED_CLKS_RX    0x00000004
#define AR_GATED_CLKS_REG   0x00000008

#define AR_OBS_BUS_CTRL     0x8068
#define AR_OBS_BUS_SEL_1    0x00040000
#define AR_OBS_BUS_SEL_2    0x00080000
#define AR_OBS_BUS_SEL_3    0x000C0000
#define AR_OBS_BUS_SEL_4    0x08040000
#define AR_OBS_BUS_SEL_5    0x08080000

#define AR_OBS_BUS_1               0x806c
#define AR_OBS_BUS_1_PCU           0x00000001
#define AR_OBS_BUS_1_RX_END        0x00000002
#define AR_OBS_BUS_1_RX_WEP        0x00000004
#define AR_OBS_BUS_1_RX_BEACON     0x00000008
#define AR_OBS_BUS_1_RX_FILTER     0x00000010
#define AR_OBS_BUS_1_TX_HCF        0x00000020
#define AR_OBS_BUS_1_QUIET_TIME    0x00000040
#define AR_OBS_BUS_1_CHAN_IDLE     0x00000080
#define AR_OBS_BUS_1_TX_HOLD       0x00000100
#define AR_OBS_BUS_1_TX_FRAME      0x00000200
#define AR_OBS_BUS_1_RX_FRAME      0x00000400
#define AR_OBS_BUS_1_RX_CLEAR      0x00000800
#define AR_OBS_BUS_1_WEP_STATE     0x0003F000
#define AR_OBS_BUS_1_WEP_STATE_S   12
#define AR_OBS_BUS_1_RX_STATE      0x01F00000
#define AR_OBS_BUS_1_RX_STATE_S    20
#define AR_OBS_BUS_1_TX_STATE      0x7E000000
#define AR_OBS_BUS_1_TX_STATE_S    25

#define AR_LAST_TSTP        0x8080
#define AR_NAV              0x8084
#define AR_RTS_OK           0x8088
#define AR_RTS_FAIL         0x808c
#define AR_ACK_FAIL         0x8090
#define AR_FCS_FAIL         0x8094
#define AR_BEACON_CNT       0x8098

#define AR_SLEEP1               0x80d4
#define AR_SLEEP1_ASSUME_DTIM   0x00080000
#define AR_SLEEP1_CAB_TIMEOUT   0xFFE00000
#define AR_SLEEP1_CAB_TIMEOUT_S 21

#define AR_SLEEP2                   0x80d8
#define AR_SLEEP2_BEACON_TIMEOUT    0xFFE00000
#define AR_SLEEP2_BEACON_TIMEOUT_S  21

#define AR_TPC                 0x80e8
#define AR_TPC_ACK             0x0000003f
#define AR_TPC_ACK_S           0x00
#define AR_TPC_CTS             0x00003f00
#define AR_TPC_CTS_S           0x08
#define AR_TPC_CHIRP           0x003f0000
#define AR_TPC_CHIRP_S         0x16

#define AR_QUIET1          0x80fc
#define AR_QUIET1_NEXT_QUIET_S         0
#define AR_QUIET1_NEXT_QUIET_M         0x0000ffff
#define AR_QUIET1_QUIET_ENABLE         0x00010000
#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000
#define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17
#define AR_QUIET2          0x8100
#define AR_QUIET2_QUIET_PERIOD_S       0
#define AR_QUIET2_QUIET_PERIOD_M       0x0000ffff
#define AR_QUIET2_QUIET_DUR_S     16
#define AR_QUIET2_QUIET_DUR       0xffff0000

#define AR_TSF_PARM        0x8104
#define AR_TSF_INCREMENT_M     0x000000ff
#define AR_TSF_INCREMENT_S     0x00

#define AR_QOS_NO_ACK              0x8108
#define AR_QOS_NO_ACK_TWO_BIT      0x0000000f
#define AR_QOS_NO_ACK_TWO_BIT_S    0
#define AR_QOS_NO_ACK_BIT_OFF      0x00000070
#define AR_QOS_NO_ACK_BIT_OFF_S    4
#define AR_QOS_NO_ACK_BYTE_OFF     0x00000180
#define AR_QOS_NO_ACK_BYTE_OFF_S   7

#define AR_PHY_ERR         0x810c

#define AR_PHY_ERR_DCHIRP      0x00000008
#define AR_PHY_ERR_RADAR       0x00000020
#define AR_PHY_ERR_OFDM_TIMING 0x00020000
#define AR_PHY_ERR_CCK_TIMING  0x02000000

#define AR_RXFIFO_CFG          0x8114


#define AR_MIC_QOS_CONTROL 0x8118
#define AR_MIC_QOS_SELECT  0x811c

#define AR_PCU_MISC                0x8120
#define AR_PCU_FORCE_BSSID_MATCH   0x00000001
#define AR_PCU_MIC_NEW_LOC_ENA     0x00000004
#define AR_PCU_TX_ADD_TSF          0x00000008
#define AR_PCU_CCK_SIFS_MODE       0x00000010
#define AR_PCU_RX_ANT_UPDT         0x00000800
#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000
#define AR_PCU_MISS_BCN_IN_SLEEP   0x00004000
#define AR_PCU_BUG_12306_FIX_ENA   0x00020000
#define AR_PCU_FORCE_QUIET_COLL    0x00040000
#define AR_PCU_TBTT_PROTECT        0x00200000
#define AR_PCU_CLEAR_VMF           0x01000000
#define AR_PCU_CLEAR_BA_VALID      0x04000000
#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000

#define AR_PCU_BT_ANT_PREVENT_RX   0x00100000
#define AR_PCU_BT_ANT_PREVENT_RX_S 20

#define AR_FILT_OFDM           0x8124
#define AR_FILT_OFDM_COUNT     0x00FFFFFF

#define AR_FILT_CCK            0x8128
#define AR_FILT_CCK_COUNT      0x00FFFFFF

#define AR_PHY_ERR_1           0x812c
#define AR_PHY_ERR_1_COUNT     0x00FFFFFF
#define AR_PHY_ERR_MASK_1      0x8130

#define AR_PHY_ERR_2           0x8134
#define AR_PHY_ERR_2_COUNT     0x00FFFFFF
#define AR_PHY_ERR_MASK_2      0x8138

#define AR_PHY_COUNTMAX        (3 << 22)
#define AR_MIBCNT_INTRMASK     (3 << 22)

#define AR_TSFOOR_THRESHOLD       0x813c
#define AR_TSFOOR_THRESHOLD_VAL   0x0000FFFF

#define AR_PHY_ERR_EIFS_MASK   0x8144

#define AR_PHY_ERR_3           0x8168
#define AR_PHY_ERR_3_COUNT     0x00FFFFFF
#define AR_PHY_ERR_MASK_3      0x816c

#define AR_BT_COEX_MODE            0x8170
#define AR_BT_TIME_EXTEND          0x000000ff
#define AR_BT_TIME_EXTEND_S        0
#define AR_BT_TXSTATE_EXTEND       0x00000100
#define AR_BT_TXSTATE_EXTEND_S     8
#define AR_BT_TX_FRAME_EXTEND      0x00000200
#define AR_BT_TX_FRAME_EXTEND_S    9
#define AR_BT_MODE                 0x00000c00
#define AR_BT_MODE_S               10
#define AR_BT_QUIET                0x00001000
#define AR_BT_QUIET_S              12
#define AR_BT_QCU_THRESH           0x0001e000
#define AR_BT_QCU_THRESH_S         13
#define AR_BT_RX_CLEAR_POLARITY    0x00020000
#define AR_BT_RX_CLEAR_POLARITY_S  17
#define AR_BT_PRIORITY_TIME        0x00fc0000
#define AR_BT_PRIORITY_TIME_S      18
#define AR_BT_FIRST_SLOT_TIME      0xff000000
#define AR_BT_FIRST_SLOT_TIME_S    24

#define AR_BT_COEX_WEIGHT          0x8174
#define AR_BT_COEX_WGHT		   0xff55
#define AR_STOMP_ALL_WLAN_WGHT	   0xfcfc
#define AR_STOMP_LOW_WLAN_WGHT	   0xa8a8
#define AR_STOMP_NONE_WLAN_WGHT	   0x0000
#define AR_BTCOEX_BT_WGHT          0x0000ffff
#define AR_BTCOEX_BT_WGHT_S        0
#define AR_BTCOEX_WL_WGHT          0xffff0000
#define AR_BTCOEX_WL_WGHT_S        16

#define AR_BT_COEX_WL_WEIGHTS0     0x8174
#define AR_BT_COEX_WL_WEIGHTS1     0x81c4

#define AR_BT_COEX_BT_WEIGHTS0     0x83ac
#define AR_BT_COEX_BT_WEIGHTS1     0x83b0
#define AR_BT_COEX_BT_WEIGHTS2     0x83b4
#define AR_BT_COEX_BT_WEIGHTS3     0x83b8

#define AR9300_BT_WGHT                     0xcccc4444
#define AR9300_STOMP_ALL_WLAN_WGHT0        0xfffffff0
#define AR9300_STOMP_ALL_WLAN_WGHT1        0xfffffff0
#define AR9300_STOMP_LOW_WLAN_WGHT0        0x88888880
#define AR9300_STOMP_LOW_WLAN_WGHT1        0x88888880
#define AR9300_STOMP_NONE_WLAN_WGHT0       0x00000000
#define AR9300_STOMP_NONE_WLAN_WGHT1       0x00000000

#define AR_BT_COEX_MODE2           0x817c
#define AR_BT_BCN_MISS_THRESH      0x000000ff
#define AR_BT_BCN_MISS_THRESH_S    0
#define AR_BT_BCN_MISS_CNT         0x0000ff00
#define AR_BT_BCN_MISS_CNT_S       8
#define AR_BT_HOLD_RX_CLEAR        0x00010000
#define AR_BT_HOLD_RX_CLEAR_S      16
#define AR_BT_DISABLE_BT_ANT       0x00100000
#define AR_BT_DISABLE_BT_ANT_S     20

#define AR_TXSIFS              0x81d0
#define AR_TXSIFS_TIME         0x000000FF
#define AR_TXSIFS_TX_LATENCY   0x00000F00
#define AR_TXSIFS_TX_LATENCY_S 8
#define AR_TXSIFS_ACK_SHIFT    0x00007000
#define AR_TXSIFS_ACK_SHIFT_S  12

#define AR_TXOP_X          0x81ec
#define AR_TXOP_X_VAL      0x000000FF


#define AR_TXOP_0_3    0x81f0
#define AR_TXOP_4_7    0x81f4
#define AR_TXOP_8_11   0x81f8
#define AR_TXOP_12_15  0x81fc

#define AR_NEXT_NDP2_TIMER                  0x8180
#define AR_FIRST_NDP_TIMER                  7
#define AR_NDP2_PERIOD                      0x81a0
#define AR_NDP2_TIMER_MODE                  0x81c0

#define AR_GEN_TIMERS(_i)                   (0x8200 + ((_i) << 2))
#define AR_NEXT_TBTT_TIMER                  AR_GEN_TIMERS(0)
#define AR_NEXT_DMA_BEACON_ALERT            AR_GEN_TIMERS(1)
#define AR_NEXT_SWBA                        AR_GEN_TIMERS(2)
#define AR_NEXT_CFP                         AR_GEN_TIMERS(2)
#define AR_NEXT_HCF                         AR_GEN_TIMERS(3)
#define AR_NEXT_TIM                         AR_GEN_TIMERS(4)
#define AR_NEXT_DTIM                        AR_GEN_TIMERS(5)
#define AR_NEXT_QUIET_TIMER                 AR_GEN_TIMERS(6)
#define AR_NEXT_NDP_TIMER                   AR_GEN_TIMERS(7)

#define AR_BEACON_PERIOD                    AR_GEN_TIMERS(8)
#define AR_DMA_BEACON_PERIOD                AR_GEN_TIMERS(9)
#define AR_SWBA_PERIOD                      AR_GEN_TIMERS(10)
#define AR_HCF_PERIOD                       AR_GEN_TIMERS(11)
#define AR_TIM_PERIOD                       AR_GEN_TIMERS(12)
#define AR_DTIM_PERIOD                      AR_GEN_TIMERS(13)
#define AR_QUIET_PERIOD                     AR_GEN_TIMERS(14)
#define AR_NDP_PERIOD                       AR_GEN_TIMERS(15)

#define AR_TIMER_MODE                       0x8240
#define AR_TBTT_TIMER_EN                    0x00000001
#define AR_DBA_TIMER_EN                     0x00000002
#define AR_SWBA_TIMER_EN                    0x00000004
#define AR_HCF_TIMER_EN                     0x00000008
#define AR_TIM_TIMER_EN                     0x00000010
#define AR_DTIM_TIMER_EN                    0x00000020
#define AR_QUIET_TIMER_EN                   0x00000040
#define AR_NDP_TIMER_EN                     0x00000080
#define AR_TIMER_OVERFLOW_INDEX             0x00000700
#define AR_TIMER_OVERFLOW_INDEX_S           8
#define AR_TIMER_THRESH                     0xFFFFF000
#define AR_TIMER_THRESH_S                   12

#define AR_SLP32_MODE                  0x8244
#define AR_SLP32_HALF_CLK_LATENCY      0x000FFFFF
#define AR_SLP32_ENA                   0x00100000
#define AR_SLP32_TSF_WRITE_STATUS      0x00200000

#define AR_SLP32_WAKE              0x8248
#define AR_SLP32_WAKE_XTL_TIME     0x0000FFFF

#define AR_SLP32_INC               0x824c
#define AR_SLP32_TST_INC           0x000FFFFF

#define AR_SLP_CNT         0x8250
#define AR_SLP_CYCLE_CNT   0x8254

#define AR_SLP_MIB_CTRL    0x8258
#define AR_SLP_MIB_CLEAR   0x00000001
#define AR_SLP_MIB_PENDING 0x00000002

#define AR_MAC_PCU_LOGIC_ANALYZER               0x8264
#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768   0x20000000


#define AR_2040_MODE                0x8318
#define AR_2040_JOINED_RX_CLEAR 0x00000001


#define AR_EXTRCCNT         0x8328

#define AR_SELFGEN_MASK         0x832c

#define AR_PCU_TXBUF_CTRL               0x8340
#define AR_PCU_TXBUF_CTRL_SIZE_MASK     0x7FF
#define AR_PCU_TXBUF_CTRL_USABLE_SIZE   0x700
#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE   0x380

#define AR_PCU_MISC_MODE2               0x8344
#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE           0x00000002
#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT   0x00000004

#define AR_PCU_MISC_MODE2_RESERVED                     0x00000038
#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE     0x00000040
#define AR_PCU_MISC_MODE2_CFP_IGNORE                   0x00000080
#define AR_PCU_MISC_MODE2_MGMT_QOS                     0x0000FF00
#define AR_PCU_MISC_MODE2_MGMT_QOS_S                   8
#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000
#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP                0x00020000
#define AR_PCU_MISC_MODE2_HWWAR1                       0x00100000
#define AR_PCU_MISC_MODE2_HWWAR2                       0x02000000
#define AR_PCU_MISC_MODE2_RESERVED2                    0xFFFE0000

#define AR_MAC_PCU_ASYNC_FIFO_REG3                     0x8358
#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL        0x00000400
#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET          0x80000000


#define AR_AES_MUTE_MASK0       0x805c
#define AR_AES_MUTE_MASK0_FC    0x0000FFFF
#define AR_AES_MUTE_MASK0_QOS   0xFFFF0000
#define AR_AES_MUTE_MASK0_QOS_S 16

#define AR_AES_MUTE_MASK1              0x8060
#define AR_AES_MUTE_MASK1_SEQ          0x0000FFFF
#define AR_AES_MUTE_MASK1_SEQ_S        0
#define AR_AES_MUTE_MASK1_FC_MGMT      0xFFFF0000
#define AR_AES_MUTE_MASK1_FC_MGMT_S    16

#define AR_RATE_DURATION_0      0x8700
#define AR_RATE_DURATION_31     0x87CC
#define AR_RATE_DURATION_32     0x8780
#define AR_RATE_DURATION(_n)    (AR_RATE_DURATION_0 + ((_n)<<2))


#define AR_KEYTABLE_0           0x8800
#define AR_KEYTABLE(_n)         (AR_KEYTABLE_0 + ((_n)*32))
#define AR_KEY_CACHE_SIZE       128
#define AR_RSVD_KEYTABLE_ENTRIES 4
#define AR_KEY_TYPE             0x00000007
#define AR_KEYTABLE_TYPE_40     0x00000000
#define AR_KEYTABLE_TYPE_104    0x00000001
#define AR_KEYTABLE_TYPE_128    0x00000003
#define AR_KEYTABLE_TYPE_TKIP   0x00000004
#define AR_KEYTABLE_TYPE_AES    0x00000005
#define AR_KEYTABLE_TYPE_CCM    0x00000006
#define AR_KEYTABLE_TYPE_CLR    0x00000007
#define AR_KEYTABLE_ANT         0x00000008
#define AR_KEYTABLE_VALID       0x00008000
#define AR_KEYTABLE_KEY0(_n)    (AR_KEYTABLE(_n) + 0)
#define AR_KEYTABLE_KEY1(_n)    (AR_KEYTABLE(_n) + 4)
#define AR_KEYTABLE_KEY2(_n)    (AR_KEYTABLE(_n) + 8)
#define AR_KEYTABLE_KEY3(_n)    (AR_KEYTABLE(_n) + 12)
#define AR_KEYTABLE_KEY4(_n)    (AR_KEYTABLE(_n) + 16)
#define AR_KEYTABLE_TYPE(_n)    (AR_KEYTABLE(_n) + 20)
#define AR_KEYTABLE_MAC0(_n)    (AR_KEYTABLE(_n) + 24)
#define AR_KEYTABLE_MAC1(_n)    (AR_KEYTABLE(_n) + 28)

#define AR9271_CORE_CLOCK	117   /* clock to 117Mhz */
#define AR9271_TARGET_BAUD_RATE	19200 /* 115200 */

#define AR_AGG_WEP_ENABLE_FIX		0x00000008  /* This allows the use of AR_AGG_WEP_ENABLE */
#define AR_ADHOC_MCAST_KEYID_ENABLE     0x00000040  /* This bit enables the Multicast search
						     * based on both MAC Address and Key ID.
						     * If bit is 0, then Multicast search is
						     * based on MAC address only.
						     * For Merlin and above only.
						     */
#define AR_AGG_WEP_ENABLE               0x00020000  /* This field enables AGG_WEP feature,
						     * when it is enable, AGG_WEP would takes
						     * charge of the encryption interface of
						     * pcu_txsm.
						     */

#define AR9300_SM_BASE				0xa200
#define AR9002_PHY_AGC_CONTROL			0x9860
#define AR9003_PHY_AGC_CONTROL			AR9300_SM_BASE + 0xc4
#define AR_PHY_AGC_CONTROL			(AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)
#define AR_PHY_AGC_CONTROL_CAL			0x00000001  /* do internal calibration */
#define AR_PHY_AGC_CONTROL_NF			0x00000002  /* do noise-floor calibration */
#define AR_PHY_AGC_CONTROL_OFFSET_CAL		0x00000800  /* allow offset calibration */
#define AR_PHY_AGC_CONTROL_ENABLE_NF		0x00008000  /* enable noise floor calibration to happen */
#define AR_PHY_AGC_CONTROL_FLTR_CAL		0x00010000  /* allow tx filter calibration */
#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF		0x00020000  /* don't update noise floor automatically */
#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS	0x00040000  /* extend noise floor power measurement */
#define AR_PHY_AGC_CONTROL_CLC_SUCCESS		0x00080000  /* carrier leak calibration done */
#define AR_PHY_AGC_CONTROL_YCOK_MAX		0x000003c0
#define AR_PHY_AGC_CONTROL_YCOK_MAX_S		6

#endif