summaryrefslogtreecommitdiff
path: root/drivers/video/fbdev/kyro/STG4000Ramdac.c
blob: e6ad037e43961a8dbef69d63381210b5a3dc3eb3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
/*
 *  linux/drivers/video/kyro/STG4000Ramdac.c
 *
 *  Copyright (C) 2002 STMicroelectronics
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <video/kyro.h>

#include "STG4000Reg.h"
#include "STG4000Interface.h"

static u32 STG_PIXEL_BUS_WIDTH = 128;	/* 128 bit bus width      */
static u32 REF_CLOCK = 14318;

int InitialiseRamdac(volatile STG4000REG __iomem * pSTGReg,
		     u32 displayDepth,
		     u32 displayWidth,
		     u32 displayHeight,
		     s32 HSyncPolarity,
		     s32 VSyncPolarity, u32 * pixelClock)
{
	u32 tmp = 0;
	u32 F = 0, R = 0, P = 0;
	u32 stride = 0;
	u32 ulPdiv = 0;
	u32 physicalPixelDepth = 0;
	/* Make sure DAC is in Reset */
	tmp = STG_READ_REG(SoftwareReset);

	if (tmp & 0x1) {
		CLEAR_BIT(1);
		STG_WRITE_REG(SoftwareReset, tmp);
	}

	/* Set Pixel Format */
	tmp = STG_READ_REG(DACPixelFormat);
	CLEAR_BITS_FRM_TO(0, 2);

	/* Set LUT not used from 16bpp to 32 bpp ??? */
	CLEAR_BITS_FRM_TO(8, 9);

	switch (displayDepth) {
	case 16:
		{
			physicalPixelDepth = 16;
			tmp |= _16BPP;
			break;
		}
	case 32:
		{
			/* Set for 32 bits per pixel */
			physicalPixelDepth = 32;
			tmp |= _32BPP;
			break;
		}
	default:
		return -EINVAL;
	}

	STG_WRITE_REG(DACPixelFormat, tmp);

	/* Workout Bus transfer bandwidth according to pixel format */
	ulPdiv = STG_PIXEL_BUS_WIDTH / physicalPixelDepth;

	/* Get Screen Stride in pixels */
	stride = displayWidth;

	/* Set Primary size info */
	tmp = STG_READ_REG(DACPrimSize);
	CLEAR_BITS_FRM_TO(0, 10);
	CLEAR_BITS_FRM_TO(12, 31);
	tmp |=
	    ((((displayHeight - 1) << 12) | (((displayWidth / ulPdiv) -
					      1) << 23))
	     | (stride / ulPdiv));
	STG_WRITE_REG(DACPrimSize, tmp);


	/* Set Pixel Clock */
	*pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P);

	/* Set DAC PLL Mode */
	tmp = STG_READ_REG(DACPLLMode);
	CLEAR_BITS_FRM_TO(0, 15);
	/* tmp |= ((P-1) | ((F-2) << 2) | ((R-2) << 11)); */
	tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));
	STG_WRITE_REG(DACPLLMode, tmp);

	/* Set Prim Address */
	tmp = STG_READ_REG(DACPrimAddress);
	CLEAR_BITS_FRM_TO(0, 20);
	CLEAR_BITS_FRM_TO(20, 31);
	STG_WRITE_REG(DACPrimAddress, tmp);

	/* Set Cursor details with HW Cursor disabled */
	tmp = STG_READ_REG(DACCursorCtrl);
	tmp &= ~SET_BIT(31);
	STG_WRITE_REG(DACCursorCtrl, tmp);

	tmp = STG_READ_REG(DACCursorAddr);
	CLEAR_BITS_FRM_TO(0, 20);
	STG_WRITE_REG(DACCursorAddr, tmp);

	/* Set Video Window */
	tmp = STG_READ_REG(DACVidWinStart);
	CLEAR_BITS_FRM_TO(0, 10);
	CLEAR_BITS_FRM_TO(16, 26);
	STG_WRITE_REG(DACVidWinStart, tmp);

	tmp = STG_READ_REG(DACVidWinEnd);
	CLEAR_BITS_FRM_TO(0, 10);
	CLEAR_BITS_FRM_TO(16, 26);
	STG_WRITE_REG(DACVidWinEnd, tmp);

	/* Set DAC Border Color to default */
	tmp = STG_READ_REG(DACBorderColor);
	CLEAR_BITS_FRM_TO(0, 23);
	STG_WRITE_REG(DACBorderColor, tmp);

	/* Set Graphics and Overlay Burst Control */
	STG_WRITE_REG(DACBurstCtrl, 0x0404);

	/* Set CRC Trigger to default */
	tmp = STG_READ_REG(DACCrcTrigger);
	CLEAR_BIT(0);
	STG_WRITE_REG(DACCrcTrigger, tmp);

	/* Set Video Port Control to default */
	tmp = STG_READ_REG(DigVidPortCtrl);
	CLEAR_BIT(8);
	CLEAR_BITS_FRM_TO(16, 27);
	CLEAR_BITS_FRM_TO(1, 3);
	CLEAR_BITS_FRM_TO(10, 11);
	STG_WRITE_REG(DigVidPortCtrl, tmp);

	return 0;
}

/* Ramdac control, turning output to the screen on and off */
void DisableRamdacOutput(volatile STG4000REG __iomem * pSTGReg)
{
	u32 tmp;

	/* Disable DAC for Graphics Stream Control */
	tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0);
	STG_WRITE_REG(DACStreamCtrl, tmp);
}

void EnableRamdacOutput(volatile STG4000REG __iomem * pSTGReg)
{
	u32 tmp;

	/* Enable DAC for Graphics Stream Control */
	tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0);
	STG_WRITE_REG(DACStreamCtrl, tmp);
}