summaryrefslogtreecommitdiff
path: root/sound/oss/ad1848.c
blob: 7cf9913a47b26ca4e3adb02a25e2538542913463 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
/*
 * sound/oss/ad1848.c
 *
 * The low level driver for the AD1848/CS4248 codec chip which
 * is used for example in the MS Sound System.
 *
 * The CS4231 which is used in the GUS MAX and some other cards is
 * upwards compatible with AD1848 and this driver is able to drive it.
 *
 * CS4231A and AD1845 are upward compatible with CS4231. However
 * the new features of these chips are different.
 *
 * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
 * CS4232A is an improved version of CS4232.
 *
 *
 *
 * Copyright (C) by Hannu Savolainen 1993-1997
 *
 * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
 * Version 2 (June 1991). See the "COPYING" file distributed with this software
 * for more info.
 *
 *
 * Thomas Sailer	: ioctl code reworked (vmalloc/vfree removed)
 *			  general sleep/wakeup clean up.
 * Alan Cox		: reformatted. Fixed SMP bugs. Moved to kernel alloc/free
 *		          of irqs. Use dev_id.
 * Christoph Hellwig	: adapted to module_init/module_exit
 * Aki Laukkanen	: added power management support
 * Arnaldo C. de Melo	: added missing restore_flags in ad1848_resume
 * Miguel Freitas       : added ISA PnP support
 * Alan Cox		: Added CS4236->4239 identification
 * Daniel T. Cobra	: Alernate config/mixer for later chips
 * Alan Cox		: Merged chip idents and config code
 *
 * TODO
 *		APM save restore assist code on IBM thinkpad
 *
 * Status:
 *		Tested. Believed fully functional.
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/stddef.h>
#include <linux/isapnp.h>
#include <linux/pnp.h>
#include <linux/spinlock.h>

#define DEB(x)
#define DEB1(x)
#include "sound_config.h"

#include "ad1848.h"
#include "ad1848_mixer.h"

typedef struct
{
	spinlock_t	lock;
	int             base;
	int             irq;
	int             dma1, dma2;
	int             dual_dma;	/* 1, when two DMA channels allocated */
	int 		subtype;
	unsigned char   MCE_bit;
	unsigned char   saved_regs[64];	/* Includes extended register space */
	int             debug_flag;

	int             audio_flags;
	int             record_dev, playback_dev;

	int             xfer_count;
	int             audio_mode;
	int             open_mode;
	int             intr_active;
	char           *chip_name, *name;
	int             model;
#define MD_1848		1
#define MD_4231		2
#define MD_4231A	3
#define MD_1845		4
#define MD_4232		5
#define MD_C930		6
#define MD_IWAVE	7
#define MD_4235         8 /* Crystal Audio CS4235  */
#define MD_1845_SSCAPE  9 /* Ensoniq Soundscape PNP*/
#define MD_4236		10 /* 4236 and higher */
#define MD_42xB		11 /* CS 42xB */
#define MD_4239		12 /* CS4239 */

	/* Mixer parameters */
	int             recmask;
	int             supported_devices, orig_devices;
	int             supported_rec_devices, orig_rec_devices;
	int            *levels;
	short           mixer_reroute[32];
	int             dev_no;
	volatile unsigned long timer_ticks;
	int             timer_running;
	int             irq_ok;
	mixer_ents     *mix_devices;
	int             mixer_output_port;
} ad1848_info;

typedef struct ad1848_port_info
{
	int             open_mode;
	int             speed;
	unsigned char   speed_bits;
	int             channels;
	int             audio_format;
	unsigned char   format_bits;
}
ad1848_port_info;

static struct address_info cfg;
static int nr_ad1848_devs;

static int deskpro_xl;
static int deskpro_m;
static int soundpro;

static volatile signed char irq2dev[17] = {
	-1, -1, -1, -1, -1, -1, -1, -1,
	-1, -1, -1, -1, -1, -1, -1, -1, -1
};

#ifndef EXCLUDE_TIMERS
static int timer_installed = -1;
#endif

static int loaded;

static int ad_format_mask[13 /*devc->model */ ] =
{
	0,
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,	/* AD1845 */
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
	AFMT_U8 | AFMT_S16_LE /* CS4235 */,
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW	/* Ensoniq Soundscape*/,
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
	AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
};

static ad1848_info adev_info[MAX_AUDIO_DEV];

#define io_Index_Addr(d)	((d)->base)
#define io_Indexed_Data(d)	((d)->base+1)
#define io_Status(d)		((d)->base+2)
#define io_Polled_IO(d)		((d)->base+3)

static struct {
     unsigned char flags;
#define CAP_F_TIMER 0x01     
} capabilities [10 /*devc->model */ ] = {
     {0}
    ,{0}           /* MD_1848  */
    ,{CAP_F_TIMER} /* MD_4231  */
    ,{CAP_F_TIMER} /* MD_4231A */
    ,{CAP_F_TIMER} /* MD_1845  */
    ,{CAP_F_TIMER} /* MD_4232  */
    ,{0}           /* MD_C930  */
    ,{CAP_F_TIMER} /* MD_IWAVE */
    ,{0}           /* MD_4235  */
    ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
};

#ifdef CONFIG_PNP
static int isapnp	= 1;
static int isapnpjump;
static int reverse;

static int audio_activated;
#else
static int isapnp;
#endif



static int      ad1848_open(int dev, int mode);
static void     ad1848_close(int dev);
static void     ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
static void     ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
static int      ad1848_prepare_for_output(int dev, int bsize, int bcount);
static int      ad1848_prepare_for_input(int dev, int bsize, int bcount);
static void     ad1848_halt(int dev);
static void     ad1848_halt_input(int dev);
static void     ad1848_halt_output(int dev);
static void     ad1848_trigger(int dev, int bits);
static irqreturn_t adintr(int irq, void *dev_id);

#ifndef EXCLUDE_TIMERS
static int ad1848_tmr_install(int dev);
static void ad1848_tmr_reprogram(int dev);
#endif

static int ad_read(ad1848_info * devc, int reg)
{
	int x;
	int timeout = 900000;

	while (timeout > 0 && inb(devc->base) == 0x80)	/*Are we initializing */
		timeout--;

	if(reg < 32)
	{
		outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
		x = inb(io_Indexed_Data(devc));
	}
	else
	{
		int xreg, xra;

		xreg = (reg & 0xff) - 32;
		xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
		outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
		outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
		x = inb(io_Indexed_Data(devc));
	}

	return x;
}

static void ad_write(ad1848_info * devc, int reg, int data)
{
	int timeout = 900000;

	while (timeout > 0 && inb(devc->base) == 0x80)	/* Are we initializing */
		timeout--;

	if(reg < 32)
	{
		outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
		outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
	}
	else
	{
		int xreg, xra;
		
		xreg = (reg & 0xff) - 32;
		xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
		outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
		outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
		outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
	}
}

static void wait_for_calibration(ad1848_info * devc)
{
	int timeout = 0;

	/*
	 * Wait until the auto calibration process has finished.
	 *
	 * 1)       Wait until the chip becomes ready (reads don't return 0x80).
	 * 2)       Wait until the ACI bit of I11 gets on and then off.
	 */

	timeout = 100000;
	while (timeout > 0 && inb(devc->base) == 0x80)
		timeout--;
	if (inb(devc->base) & 0x80)
		printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");

	timeout = 100;
	while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
		timeout--;
	if (!(ad_read(devc, 11) & 0x20))
		return;

	timeout = 80000;
	while (timeout > 0 && (ad_read(devc, 11) & 0x20))
		timeout--;
	if (ad_read(devc, 11) & 0x20)
		if ( (devc->model != MD_1845) || (devc->model != MD_1845_SSCAPE))
			printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
}

static void ad_mute(ad1848_info * devc)
{
	int i;
	unsigned char prev;

	/*
	 * Save old register settings and mute output channels
	 */
	 
	for (i = 6; i < 8; i++)
	{
		prev = devc->saved_regs[i] = ad_read(devc, i);
	}

}

static void ad_unmute(ad1848_info * devc)
{
}

static void ad_enter_MCE(ad1848_info * devc)
{
	int timeout = 1000;
	unsigned short prev;

	while (timeout > 0 && inb(devc->base) == 0x80)	/*Are we initializing */
		timeout--;

	devc->MCE_bit = 0x40;
	prev = inb(io_Index_Addr(devc));
	if (prev & 0x40)
	{
		return;
	}
	outb((devc->MCE_bit), io_Index_Addr(devc));
}

static void ad_leave_MCE(ad1848_info * devc)
{
	unsigned char prev, acal;
	int timeout = 1000;

	while (timeout > 0 && inb(devc->base) == 0x80)	/*Are we initializing */
		timeout--;

	acal = ad_read(devc, 9);

	devc->MCE_bit = 0x00;
	prev = inb(io_Index_Addr(devc));
	outb((0x00), io_Index_Addr(devc));	/* Clear the MCE bit */

	if ((prev & 0x40) == 0)	/* Not in MCE mode */
	{
		return;
	}
	outb((0x00), io_Index_Addr(devc));	/* Clear the MCE bit */
	if (acal & 0x08)	/* Auto calibration is enabled */
		wait_for_calibration(devc);
}

static int ad1848_set_recmask(ad1848_info * devc, int mask)
{
	unsigned char   recdev;
	int             i, n;
	unsigned long flags;

	mask &= devc->supported_rec_devices;

	/* Rename the mixer bits if necessary */
	for (i = 0; i < 32; i++)
	{
		if (devc->mixer_reroute[i] != i)
		{
			if (mask & (1 << i))
			{
				mask &= ~(1 << i);
				mask |= (1 << devc->mixer_reroute[i]);
			}
		}
	}
	
	n = 0;
	for (i = 0; i < 32; i++)	/* Count selected device bits */
		if (mask & (1 << i))
			n++;

	spin_lock_irqsave(&devc->lock,flags);
	if (!soundpro) {
		if (n == 0)
			mask = SOUND_MASK_MIC;
		else if (n != 1) {	/* Too many devices selected */
			mask &= ~devc->recmask;	/* Filter out active settings */

			n = 0;
			for (i = 0; i < 32; i++)	/* Count selected device bits */
				if (mask & (1 << i))
					n++;

			if (n != 1)
				mask = SOUND_MASK_MIC;
		}
		switch (mask) {
		case SOUND_MASK_MIC:
			recdev = 2;
			break;

		case SOUND_MASK_LINE:
		case SOUND_MASK_LINE3:
			recdev = 0;
			break;

		case SOUND_MASK_CD:
		case SOUND_MASK_LINE1:
			recdev = 1;
			break;

		case SOUND_MASK_IMIX:
			recdev = 3;
			break;

		default:
			mask = SOUND_MASK_MIC;
			recdev = 2;
		}

		recdev <<= 6;
		ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
		ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
	} else { /* soundpro */
		unsigned char val;
		int set_rec_bit;
		int j;

		for (i = 0; i < 32; i++) {	/* For each bit */
			if ((devc->supported_rec_devices & (1 << i)) == 0)
				continue;	/* Device not supported */

			for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
				if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
					continue;

				/*
				 * This is tricky:
				 * set_rec_bit becomes 1 if the corresponding bit in mask is set
				 * then it gets flipped if the polarity is inverse
				 */
				set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;

				val = ad_read(devc, devc->mix_devices[i][j].recreg);
				val &= ~(1 << devc->mix_devices[i][j].recpos);
				val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
				ad_write(devc, devc->mix_devices[i][j].recreg, val);
			}
		}
	}
	spin_unlock_irqrestore(&devc->lock,flags);

	/* Rename the mixer bits back if necessary */
	for (i = 0; i < 32; i++)
	{
		if (devc->mixer_reroute[i] != i)
		{
			if (mask & (1 << devc->mixer_reroute[i]))
			{
				mask &= ~(1 << devc->mixer_reroute[i]);
				mask |= (1 << i);
			}
		}
	}
	devc->recmask = mask;
	return mask;
}

static void change_bits(ad1848_info * devc, unsigned char *regval,
			unsigned char *muteval, int dev, int chn, int newval)
{
	unsigned char mask;
	int shift;
	int mute;
	int mutemask;
	int set_mute_bit;

	set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;

	if (devc->mix_devices[dev][chn].polarity == 1)	/* Reverse */
		newval = 100 - newval;

	mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
	shift = devc->mix_devices[dev][chn].bitpos;

	if (devc->mix_devices[dev][chn].mutepos == 8)
	{			/* if there is no mute bit */
		mute = 0;	/* No mute bit; do nothing special */
		mutemask = ~0;	/* No mute bit; do nothing special */
	}
	else
	{
		mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
		mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
	}

	newval = (int) ((newval * mask) + 50) / 100;	/* Scale it */
	*regval &= ~(mask << shift);			/* Clear bits */
	*regval |= (newval & mask) << shift;		/* Set new value */

	*muteval &= mutemask;
	*muteval |= mute;
}

static int ad1848_mixer_get(ad1848_info * devc, int dev)
{
	if (!((1 << dev) & devc->supported_devices))
		return -EINVAL;

	dev = devc->mixer_reroute[dev];

	return devc->levels[dev];
}

static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
{
	int regoffs, muteregoffs;
	unsigned char val, muteval;
	unsigned long flags;

	regoffs = devc->mix_devices[dev][channel].regno;
	muteregoffs = devc->mix_devices[dev][channel].mutereg;
	val = ad_read(devc, regoffs);

	if (muteregoffs != regoffs) {
		muteval = ad_read(devc, muteregoffs);
		change_bits(devc, &val, &muteval, dev, channel, value);
	}
	else
		change_bits(devc, &val, &val, dev, channel, value);

	spin_lock_irqsave(&devc->lock,flags);
	ad_write(devc, regoffs, val);
	devc->saved_regs[regoffs] = val;
	if (muteregoffs != regoffs) {
		ad_write(devc, muteregoffs, muteval);
		devc->saved_regs[muteregoffs] = muteval;
	}
	spin_unlock_irqrestore(&devc->lock,flags);
}

static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
{
	int left = value & 0x000000ff;
	int right = (value & 0x0000ff00) >> 8;
	int retvol;

	if (dev > 31)
		return -EINVAL;

	if (!(devc->supported_devices & (1 << dev)))
		return -EINVAL;

	dev = devc->mixer_reroute[dev];

	if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
		return -EINVAL;

	if (left > 100)
		left = 100;
	if (right > 100)
		right = 100;

	if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)	/* Mono control */
		right = left;

	retvol = left | (right << 8);

	/* Scale volumes */
	left = mix_cvt[left];
	right = mix_cvt[right];

	devc->levels[dev] = retvol;

	/*
	 * Set the left channel
	 */
	ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);

	/*
	 * Set the right channel
	 */
	if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
		goto out;
	ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);

 out:
	return retvol;
}

static void ad1848_mixer_reset(ad1848_info * devc)
{
	int i;
	char name[32];
	unsigned long flags;

	devc->mix_devices = &(ad1848_mix_devices[0]);

	sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);

	for (i = 0; i < 32; i++)
		devc->mixer_reroute[i] = i;

	devc->supported_rec_devices = MODE1_REC_DEVICES;

	switch (devc->model)
	{
		case MD_4231:
		case MD_4231A:
		case MD_1845:
		case MD_1845_SSCAPE:
			devc->supported_devices = MODE2_MIXER_DEVICES;
			break;

		case MD_C930:
			devc->supported_devices = C930_MIXER_DEVICES;
			devc->mix_devices = &(c930_mix_devices[0]);
			break;

		case MD_IWAVE:
			devc->supported_devices = MODE3_MIXER_DEVICES;
			devc->mix_devices = &(iwave_mix_devices[0]);
			break;

		case MD_42xB:
		case MD_4239:
			devc->mix_devices = &(cs42xb_mix_devices[0]);
			devc->supported_devices = MODE3_MIXER_DEVICES;
			break;
		case MD_4232:
		case MD_4235:
		case MD_4236:
			devc->supported_devices = MODE3_MIXER_DEVICES;
			break;

		case MD_1848:
			if (soundpro) {
				devc->supported_devices = SPRO_MIXER_DEVICES;
				devc->supported_rec_devices = SPRO_REC_DEVICES;
				devc->mix_devices = &(spro_mix_devices[0]);
				break;
			}

		default:
			devc->supported_devices = MODE1_MIXER_DEVICES;
	}

	devc->orig_devices = devc->supported_devices;
	devc->orig_rec_devices = devc->supported_rec_devices;

	devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);

	for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
	{
		if (devc->supported_devices & (1 << i))
			ad1848_mixer_set(devc, i, devc->levels[i]);
	}
	
	ad1848_set_recmask(devc, SOUND_MASK_MIC);
	
	devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;

	spin_lock_irqsave(&devc->lock,flags);
	if (!soundpro) {
		if (devc->mixer_output_port & AUDIO_SPEAKER)
			ad_write(devc, 26, ad_read(devc, 26) & ~0x40);	/* Unmute mono out */
		else
			ad_write(devc, 26, ad_read(devc, 26) | 0x40);	/* Mute mono out */
	} else {
		/*
		 * From the "wouldn't it be nice if the mixer API had (better)
		 * support for custom stuff" category
		 */
		/* Enable surround mode and SB16 mixer */
		ad_write(devc, 16, 0x60);
	}
	spin_unlock_irqrestore(&devc->lock,flags);
}

static int ad1848_mixer_ioctl(int dev, unsigned int cmd, void __user *arg)
{
	ad1848_info *devc = mixer_devs[dev]->devc;
	int val;

	if (cmd == SOUND_MIXER_PRIVATE1) 
	{
		if (get_user(val, (int __user *)arg))
			return -EFAULT;

		if (val != 0xffff) 
		{
			unsigned long flags;
			val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
			devc->mixer_output_port = val;
			val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT;	/* Always on */
			devc->mixer_output_port = val;
			spin_lock_irqsave(&devc->lock,flags);
			if (val & AUDIO_SPEAKER)
				ad_write(devc, 26, ad_read(devc, 26) & ~0x40);	/* Unmute mono out */
			else
				ad_write(devc, 26, ad_read(devc, 26) | 0x40);		/* Mute mono out */
			spin_unlock_irqrestore(&devc->lock,flags);
		}
		val = devc->mixer_output_port;
		return put_user(val, (int __user *)arg);
	}
	if (cmd == SOUND_MIXER_PRIVATE2)
	{
		if (get_user(val, (int __user *)arg))
			return -EFAULT;
		return(ad1848_control(AD1848_MIXER_REROUTE, val));
	}
	if (((cmd >> 8) & 0xff) == 'M') 
	{
		if (_SIOC_DIR(cmd) & _SIOC_WRITE)
		{
			switch (cmd & 0xff) 
			{
				case SOUND_MIXER_RECSRC:
					if (get_user(val, (int __user *)arg))
						return -EFAULT;
					val = ad1848_set_recmask(devc, val);
					break;
				
				default:
					if (get_user(val, (int __user *)arg))
					return -EFAULT;
					val = ad1848_mixer_set(devc, cmd & 0xff, val);
					break;
			} 
			return put_user(val, (int __user *)arg);
		}
		else
		{
			switch (cmd & 0xff) 
			{
				/*
				 * Return parameters
				 */
			    
				case SOUND_MIXER_RECSRC:
					val = devc->recmask;
					break;
				
				case SOUND_MIXER_DEVMASK:
					val = devc->supported_devices;
					break;
				
				case SOUND_MIXER_STEREODEVS:
					val = devc->supported_devices;
					if (devc->model != MD_C930)
						val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
					break;
				
				case SOUND_MIXER_RECMASK:
					val = devc->supported_rec_devices;
					break;

				case SOUND_MIXER_CAPS:
					val=SOUND_CAP_EXCL_INPUT;
					break;

				default:
					val = ad1848_mixer_get(devc, cmd & 0xff);
					break;
			}
			return put_user(val, (int __user *)arg);
		}
	}
	else
		return -EINVAL;
}

static int ad1848_set_speed(int dev, int arg)
{
	ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
	ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;

	/*
	 * The sampling speed is encoded in the least significant nibble of I8. The
	 * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
	 * three bits select the divisor (indirectly):
	 *
	 * The available speeds are in the following table. Keep the speeds in
	 * the increasing order.
	 */
	typedef struct
	{
		int             speed;
		unsigned char   bits;
	}
	speed_struct;

	static speed_struct speed_table[] =
	{
		{5510, (0 << 1) | 1},
		{5510, (0 << 1) | 1},
		{6620, (7 << 1) | 1},
		{8000, (0 << 1) | 0},
		{9600, (7 << 1) | 0},
		{11025, (1 << 1) | 1},
		{16000, (1 << 1) | 0},
		{18900, (2 << 1) | 1},
		{22050, (3 << 1) | 1},
		{27420, (2 << 1) | 0},
		{32000, (3 << 1) | 0},
		{33075, (6 << 1) | 1},
		{37800, (4 << 1) | 1},
		{44100, (5 << 1) | 1},
		{48000, (6 << 1) | 0}
	};

	int i, n, selected = -1;

	n = sizeof(speed_table) / sizeof(speed_struct);

	if (arg <= 0)
		return portc->speed;

	if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)	/* AD1845 has different timer than others */
	{
		if (arg < 4000)
			arg = 4000;
		if (arg > 50000)
			arg = 50000;

		portc->speed = arg;
		portc->speed_bits = speed_table[3].bits;
		return portc->speed;
	}
	if (arg < speed_table[0].speed)
		selected = 0;
	if (arg > speed_table[n - 1].speed)
		selected = n - 1;

	for (i = 1 /*really */ ; selected == -1 && i < n; i++)
	{
		if (speed_table[i].speed == arg)
			selected = i;
		else if (speed_table[i].speed > arg)
		{
			int diff1, diff2;

			diff1 = arg - speed_table[i - 1].speed;
			diff2 = speed_table[i].speed - arg;

			if (diff1 < diff2)
				selected = i - 1;
			else
				selected = i;
		}
	}
	if (selected == -1)
	{
		printk(KERN_WARNING "ad1848: Can't find speed???\n");
		selected = 3;
	}
	portc->speed = speed_table[selected].speed;
	portc->speed_bits = speed_table[selected].bits;
	return portc->speed;
}

static short ad1848_set_channels(int dev, short arg)
{
	ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;

	if (arg != 1 && arg != 2)
		return portc->channels;

	portc->channels = arg;
	return arg;
}

static unsigned int ad1848_set_bits(int dev, unsigned int arg)
{
	ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
	ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;

	static struct format_tbl
	{
		  int             format;
		  unsigned char   bits;
	}
	format2bits[] =
	{
		{
			0, 0
		}
		,
		{
			AFMT_MU_LAW, 1
		}
		,
		{
			AFMT_A_LAW, 3
		}
		,
		{
			AFMT_IMA_ADPCM, 5
		}
		,
		{
			AFMT_U8, 0
		}
		,
		{
			AFMT_S16_LE, 2
		}
		,
		{
			AFMT_S16_BE, 6
		}
		,
		{
			AFMT_S8, 0
		}
		,
		{
			AFMT_U16_LE, 0
		}
		,
		{
			AFMT_U16_BE, 0
		}
	};
	int i, n = sizeof(format2bits) / sizeof(struct format_tbl);

	if (arg == 0)
		return portc->audio_format;

	if (!(arg & ad_format_mask[devc->model]))
		arg = AFMT_U8;

	portc->audio_format = arg;

	for (i = 0; i < n; i++)
		if (format2bits[i].format == arg)
		{
			if ((portc->format_bits = format2bits[i].bits) == 0)
				return portc->audio_format = AFMT_U8;		/* Was not supported */

			return arg;
		}
	/* Still hanging here. Something must be terribly wrong */
	portc->format_bits = 0;
	return portc->audio_format = AFMT_U8;
}

static struct audio_driver ad1848_audio_driver =
{
	.owner			= THIS_MODULE,
	.open			= ad1848_open,
	.close			= ad1848_close,
	.output_block		= ad1848_output_block,
	.start_input		= ad1848_start_input,
	.prepare_for_input	= ad1848_prepare_for_input,
	.prepare_for_output	= ad1848_prepare_for_output,
	.halt_io		= ad1848_halt,
	.halt_input		= ad1848_halt_input,
	.halt_output		= ad1848_halt_output,
	.trigger		= ad1848_trigger,
	.set_speed		= ad1848_set_speed,
	.set_bits		= ad1848_set_bits,
	.set_channels		= ad1848_set_channels
};

static struct mixer_operations ad1848_mixer_operations =
{
	.owner	= THIS_MODULE,
	.id	= "SOUNDPORT",
	.name	= "AD1848/CS4248/CS4231",
	.ioctl	= ad1848_mixer_ioctl
};

static int ad1848_open(int dev, int mode)
{
	ad1848_info    *devc;
	ad1848_port_info *portc;
	unsigned long   flags;

	if (dev < 0 || dev >= num_audiodevs)
		return -ENXIO;

	devc = (ad1848_info *) audio_devs[dev]->devc;
	portc = (ad1848_port_info *) audio_devs[dev]->portc;

	/* here we don't have to protect against intr */
	spin_lock(&devc->lock);
	if (portc->open_mode || (devc->open_mode & mode))
	{
		spin_unlock(&devc->lock);
		return -EBUSY;
	}
	devc->dual_dma = 0;

	if (audio_devs[dev]->flags & DMA_DUPLEX)
	{
		devc->dual_dma = 1;
	}
	devc->intr_active = 0;
	devc->audio_mode = 0;
	devc->open_mode |= mode;
	portc->open_mode = mode;
	spin_unlock(&devc->lock);
	ad1848_trigger(dev, 0);

	if (mode & OPEN_READ)
		devc->record_dev = dev;
	if (mode & OPEN_WRITE)
		devc->playback_dev = dev;
/*
 * Mute output until the playback really starts. This decreases clicking (hope so).
 */
	spin_lock_irqsave(&devc->lock,flags);
	ad_mute(devc);
	spin_unlock_irqrestore(&devc->lock,flags);

	return 0;
}

static void ad1848_close(int dev)
{
	unsigned long   flags;
	ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
	ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;

	DEB(printk("ad1848_close(void)\n"));

	devc->intr_active = 0;
	ad1848_halt(dev);

	spin_lock_irqsave(&devc->lock,flags);

	devc->audio_mode = 0;
	devc->open_mode &= ~portc->open_mode;
	portc->open_mode = 0;

	ad_unmute(devc);
	spin_unlock_irqrestore(&devc->lock,flags);
}

static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
{
	unsigned long   flags, cnt;
	ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
	ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;

	cnt = count;

	if (portc->audio_format == AFMT_IMA_ADPCM)
	{
		cnt /= 4;
	}
	else
	{
		if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))	/* 16 bit data */
			cnt >>= 1;
	}
	if (portc->channels > 1)
		cnt >>= 1;
	cnt--;

	if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
	    intrflag &&
	    cnt == devc->xfer_count)
	{
		devc->audio_mode |= PCM_ENABLE_OUTPUT;
		devc->intr_active = 1;
		return;	/*
			 * Auto DMA mode on. No need to react
			 */
	}
	spin_lock_irqsave(&devc->lock,flags);

	ad_write(devc, 15, (unsigned char) (cnt & 0xff));
	ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));

	devc->xfer_count = cnt;
	devc->audio_mode |= PCM_ENABLE_OUTPUT;
	devc->intr_active = 1;
	spin_unlock_irqrestore(&devc->lock,flags);
}

static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
{
	unsigned long   flags, cnt;
	ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
	ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;

	cnt = count;
	if (portc->audio_format == AFMT_IMA_ADPCM)
	{
		cnt /= 4;
	}
	else
	{
		if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))	/* 16 bit data */
			cnt >>= 1;
	}
	if (portc->channels > 1)
		cnt >>= 1;
	cnt--;

	if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
		intrflag &&
		cnt == devc->xfer_count)
	{
		devc->audio_mode |= PCM_ENABLE_INPUT;
		devc->intr_active = 1;
		return;	/*
			 * Auto DMA mode on. No need to react
			 */
	}
	spin_lock_irqsave(&devc->lock,flags);

	if (devc->model == MD_1848)
	{
		  ad_write(devc, 15, (unsigned char) (cnt & 0xff));
		  ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
	}
	else
	{
		  ad_write(devc, 31, (unsigned char) (cnt & 0xff));
		  ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
	}

	ad_unmute(devc);

	devc->xfer_count = cnt;
	devc->audio_mode |= PCM_ENABLE_INPUT;
	devc->intr_active = 1;
	spin_unlock_irqrestore(&devc->lock,flags);
}

static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
{
	int             timeout;
	unsigned char   fs, old_fs, tmp = 0;
	unsigned long   flags;
	ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
	ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;

	ad_mute(devc);

	spin_lock_irqsave(&devc->lock,flags);
	fs = portc->speed_bits | (portc->format_bits << 5);

	if (portc->channels > 1)
		fs |= 0x10;

	ad_enter_MCE(devc);	/* Enables changes to the format select reg */

	if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
	{
		fs &= 0xf0;	/* Mask off the rate select bits */

		ad_write(devc, 22, (portc->speed >> 8) & 0xff);	/* Speed MSB */
		ad_write(devc, 23, portc->speed & 0xff);	/* Speed LSB */
	}
	old_fs = ad_read(devc, 8);

	if (devc->model == MD_4232 || devc->model >= MD_4236)
	{
		tmp = ad_read(devc, 16);
		ad_write(devc, 16, tmp | 0x30);
	}
	if (devc->model == MD_IWAVE)
		ad_write(devc, 17, 0xc2);	/* Disable variable frequency select */

	ad_write(devc, 8, fs);

	/*
	 * Write to I8 starts resynchronization. Wait until it completes.
	 */

	timeout = 0;
	while (timeout < 100 && inb(devc->base) != 0x80)
		timeout++;
	timeout = 0;
	while (timeout < 10000 && inb(devc->base) == 0x80)
		timeout++;

	if (devc->model >= MD_4232)
		ad_write(devc, 16, tmp & ~0x30);

	ad_leave_MCE(devc);	/*
				 * Starts the calibration process.
				 */
	spin_unlock_irqrestore(&devc->lock,flags);
	devc->xfer_count = 0;

#ifndef EXCLUDE_TIMERS
	if (dev == timer_installed && devc->timer_running)
		if ((fs & 0x01) != (old_fs & 0x01))
		{
			ad1848_tmr_reprogram(dev);
		}
#endif
	ad1848_halt_output(dev);
	return 0;
}

static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
{
	int timeout;
	unsigned char fs, old_fs, tmp = 0;
	unsigned long flags;
	ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
	ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;

	if (devc->audio_mode)
		return 0;

	spin_lock_irqsave(&devc->lock,flags);
	fs = portc->speed_bits | (portc->format_bits << 5);

	if (portc->channels > 1)
		fs |= 0x10;

	ad_enter_MCE(devc);	/* Enables changes to the format select reg */

	if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE))	/* Use alternate speed select registers */
	{
		fs &= 0xf0;	/* Mask off the rate select bits */

		ad_write(devc, 22, (portc->speed >> 8) & 0xff);	/* Speed MSB */
		ad_write(devc, 23, portc->speed & 0xff);	/* Speed LSB */
	}
	if (devc->model == MD_4232)
	{
		tmp = ad_read(devc, 16);
		ad_write(devc, 16, tmp | 0x30);
	}
	if (devc->model == MD_IWAVE)
		ad_write(devc, 17, 0xc2);	/* Disable variable frequency select */

	/*
	 * If mode >= 2 (CS4231), set I28. It's the capture format register.
	 */
	
	if (devc->model != MD_1848)
	{
		old_fs = ad_read(devc, 28);
		ad_write(devc, 28, fs);

		/*
		 * Write to I28 starts resynchronization. Wait until it completes.
		 */
		
		timeout = 0;
		while (timeout < 100 && inb(devc->base) != 0x80)
			timeout++;

		timeout = 0;
		while (timeout < 10000 && inb(devc->base) == 0x80)
			timeout++;

		if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
		{
			/*
			 * CS4231 compatible devices don't have separate sampling rate selection
			 * register for recording an playback. The I8 register is shared so we have to
			 * set the speed encoding bits of it too.
			 */
			unsigned char   tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);

			ad_write(devc, 8, tmp);
			/*
			 * Write to I8 starts resynchronization. Wait until it completes.
			 */
			timeout = 0;
			while (timeout < 100 && inb(devc->base) != 0x80)
				timeout++;

			timeout = 0;
			while (timeout < 10000 && inb(devc->base) == 0x80)
				timeout++;
		}
	}
	else
	{			/* For AD1848 set I8. */

		old_fs = ad_read(devc, 8);
		ad_write(devc, 8, fs);
		/*
		 * Write to I8 starts resynchronization. Wait until it completes.
		 */
		timeout = 0;
		while (timeout < 100 && inb(devc->base) != 0x80)
			timeout++;
		timeout = 0;
		while (timeout < 10000 && inb(devc->base) == 0x80)
			timeout++;
	}

	if (devc->model == MD_4232)
		ad_write(devc, 16, tmp & ~0x30);

	ad_leave_MCE(devc);	/*
				 * Starts the calibration process.
				 */
	spin_unlock_irqrestore(&devc->lock,flags);
	devc->xfer_count = 0;

#ifndef EXCLUDE_TIMERS
	if (dev == timer_installed && devc->timer_running)
	{
		if ((fs & 0x01) != (old_fs & 0x01))
		{
			ad1848_tmr_reprogram(dev);
		}
	}
#endif
	ad1848_halt_input(dev);
	return 0;
}

static void ad1848_halt(int dev)
{
	ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
	ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;

	unsigned char   bits = ad_read(devc, 9);

	if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
		ad1848_halt_output(dev);

	if (bits & 0x02 && (portc->open_mode & OPEN_READ))
		ad1848_halt_input(dev);
	devc->audio_mode = 0;
}

static void ad1848_halt_input(int dev)
{
	ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
	unsigned long   flags;

	if (!(ad_read(devc, 9) & 0x02))
		return;		/* Capture not enabled */

	spin_lock_irqsave(&devc->lock,flags);

	ad_mute(devc);

	{
		int             tmout;
		
		if(!isa_dma_bridge_buggy)
		        disable_dma(audio_devs[dev]->dmap_in->dma);

		for (tmout = 0; tmout < 100000; tmout++)
			if (ad_read(devc, 11) & 0x10)
				break;
		ad_write(devc, 9, ad_read(devc, 9) & ~0x02);	/* Stop capture */

		if(!isa_dma_bridge_buggy)
		        enable_dma(audio_devs[dev]->dmap_in->dma);
		devc->audio_mode &= ~PCM_ENABLE_INPUT;
	}

	outb(0, io_Status(devc));	/* Clear interrupt status */
	outb(0, io_Status(devc));	/* Clear interrupt status */

	devc->audio_mode &= ~PCM_ENABLE_INPUT;

	spin_unlock_irqrestore(&devc->lock,flags);
}

static void ad1848_halt_output(int dev)
{
	ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
	unsigned long flags;

	if (!(ad_read(devc, 9) & 0x01))
		return;		/* Playback not enabled */

	spin_lock_irqsave(&devc->lock,flags);

	ad_mute(devc);
	{
		int             tmout;

		if(!isa_dma_bridge_buggy)
		        disable_dma(audio_devs[dev]->dmap_out->dma);

		for (tmout = 0; tmout < 100000; tmout++)
			if (ad_read(devc, 11) & 0x10)
				break;
		ad_write(devc, 9, ad_read(devc, 9) & ~0x01);	/* Stop playback */

		if(!isa_dma_bridge_buggy)
		       enable_dma(audio_devs[dev]->dmap_out->dma);

		devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
	}

	outb((0), io_Status(devc));	/* Clear interrupt status */
	outb((0), io_Status(devc));	/* Clear interrupt status */

	devc->audio_mode &= ~PCM_ENABLE_OUTPUT;

	spin_unlock_irqrestore(&devc->lock,flags);
}

static void ad1848_trigger(int dev, int state)
{
	ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
	ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
	unsigned long   flags;
	unsigned char   tmp, old;

	spin_lock_irqsave(&devc->lock,flags);
	state &= devc->audio_mode;

	tmp = old = ad_read(devc, 9);

	if (portc->open_mode & OPEN_READ)
	{
		  if (state & PCM_ENABLE_INPUT)
			  tmp |= 0x02;
		  else
			  tmp &= ~0x02;
	}
	if (portc->open_mode & OPEN_WRITE)
	{
		if (state & PCM_ENABLE_OUTPUT)
			tmp |= 0x01;
		else
			tmp &= ~0x01;
	}
	/* ad_mute(devc); */
	if (tmp != old)
	{
		  ad_write(devc, 9, tmp);
		  ad_unmute(devc);
	}
	spin_unlock_irqrestore(&devc->lock,flags);
}

static void ad1848_init_hw(ad1848_info * devc)
{
	int i;
	int *init_values;

	/*
	 * Initial values for the indirect registers of CS4248/AD1848.
	 */
	static int      init_values_a[] =
	{
		0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
		0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,

	/* Positions 16 to 31 just for CS4231/2 and ad1845 */
		0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
	};

	static int      init_values_b[] =
	{
		/* 
		   Values for the newer chips
		   Some of the register initialization values were changed. In
		   order to get rid of the click that preceded PCM playback,
		   calibration was disabled on the 10th byte. On that same byte,
		   dual DMA was enabled; on the 11th byte, ADC dithering was
		   enabled, since that is theoretically desirable; on the 13th
		   byte, Mode 3 was selected, to enable access to extended
		   registers.
		 */
		0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
		0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
 		0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
	};

	/*
	 *	Select initialisation data
	 */
	 
	init_values = init_values_a;
	if(devc->model >= MD_4236)
		init_values = init_values_b;

	for (i = 0; i < 16; i++)
		ad_write(devc, i, init_values[i]);


	ad_mute(devc);		/* Initialize some variables */
	ad_unmute(devc);	/* Leave it unmuted now */

	if (devc->model > MD_1848)
	{
		if (devc->model == MD_1845_SSCAPE)
			ad_write(devc, 12, ad_read(devc, 12) | 0x50);
		else 
			ad_write(devc, 12, ad_read(devc, 12) | 0x40);		/* Mode2 = enabled */

		if (devc->model == MD_IWAVE)
			ad_write(devc, 12, 0x6c);	/* Select codec mode 3 */

		if (devc->model != MD_1845_SSCAPE)
			for (i = 16; i < 32; i++)
				ad_write(devc, i, init_values[i]);

		if (devc->model == MD_IWAVE)
			ad_write(devc, 16, 0x30);	/* Playback and capture counters enabled */
	}
	if (devc->model > MD_1848)
	{
		if (devc->audio_flags & DMA_DUPLEX)
			ad_write(devc, 9, ad_read(devc, 9) & ~0x04);	/* Dual DMA mode */
		else
			ad_write(devc, 9, ad_read(devc, 9) | 0x04);	/* Single DMA mode */

		if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
			ad_write(devc, 27, ad_read(devc, 27) | 0x08);		/* Alternate freq select enabled */

		if (devc->model == MD_IWAVE)
		{		/* Some magic Interwave specific initialization */
			ad_write(devc, 12, 0x6c);	/* Select codec mode 3 */
			ad_write(devc, 16, 0x30);	/* Playback and capture counters enabled */
			ad_write(devc, 17, 0xc2);	/* Alternate feature enable */
		}
	}
	else
	{
		  devc->audio_flags &= ~DMA_DUPLEX;
		  ad_write(devc, 9, ad_read(devc, 9) | 0x04);	/* Single DMA mode */
		  if (soundpro)
			  ad_write(devc, 12, ad_read(devc, 12) | 0x40);	/* Mode2 = enabled */
	}

	outb((0), io_Status(devc));	/* Clear pending interrupts */

	/*
	 * Toggle the MCE bit. It completes the initialization phase.
	 */

	ad_enter_MCE(devc);	/* In case the bit was off */
	ad_leave_MCE(devc);

	ad1848_mixer_reset(devc);
}

int ad1848_detect(struct resource *ports, int *ad_flags, int *osp)
{
	unsigned char tmp;
	ad1848_info *devc = &adev_info[nr_ad1848_devs];
	unsigned char tmp1 = 0xff, tmp2 = 0xff;
	int optiC930 = 0;	/* OPTi 82C930 flag */
	int interwave = 0;
	int ad1847_flag = 0;
	int cs4248_flag = 0;
	int sscape_flag = 0;
	int io_base = ports->start;

	int i;

	DDB(printk("ad1848_detect(%x)\n", io_base));

	if (ad_flags)
	{
		if (*ad_flags == 0x12345678)
		{
			interwave = 1;
			*ad_flags = 0;
		}
		
		if (*ad_flags == 0x87654321)
		{
			sscape_flag = 1;
			*ad_flags = 0;
		}
		
		if (*ad_flags == 0x12345677)
		{
		    cs4248_flag = 1;
		    *ad_flags = 0;
		}
	}
	if (nr_ad1848_devs >= MAX_AUDIO_DEV)
	{
		printk(KERN_ERR "ad1848 - Too many audio devices\n");
		return 0;
	}
	spin_lock_init(&devc->lock);
	devc->base = io_base;
	devc->irq_ok = 0;
	devc->timer_running = 0;
	devc->MCE_bit = 0x40;
	devc->irq = 0;
	devc->open_mode = 0;
	devc->chip_name = devc->name = "AD1848";
	devc->model = MD_1848;	/* AD1848 or CS4248 */
	devc->levels = NULL;
	devc->debug_flag = 0;

	/*
	 * Check that the I/O address is in use.
	 *
	 * The bit 0x80 of the base I/O port is known to be 0 after the
	 * chip has performed its power on initialization. Just assume
	 * this has happened before the OS is starting.
	 *
	 * If the I/O address is unused, it typically returns 0xff.
	 */

	if (inb(devc->base) == 0xff)
	{
		DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
	}

	/*
	 * Wait for the device to stop initialization
	 */
	
	DDB(printk("ad1848_detect() - step 0\n"));

	for (i = 0; i < 10000000; i++)
	{
		unsigned char   x = inb(devc->base);

		if (x == 0xff || !(x & 0x80))
			break;
	}

	DDB(printk("ad1848_detect() - step A\n"));

	if (inb(devc->base) == 0x80)	/* Not ready. Let's wait */
		ad_leave_MCE(devc);

	if ((inb(devc->base) & 0x80) != 0x00)	/* Not a AD1848 */
	{
		DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
		return 0;
	}
	
	/*
	 * Test if it's possible to change contents of the indirect registers.
	 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
	 * so try to avoid using it.
	 */

	DDB(printk("ad1848_detect() - step B\n"));
	ad_write(devc, 0, 0xaa);
	ad_write(devc, 1, 0x45);	/* 0x55 with bit 0x10 clear */

	if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
	{
		if (tmp2 == 0x65)	/* AD1847 has couple of bits hardcoded to 1 */
			ad1847_flag = 1;
		else
		{
			DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
			return 0;
		}
	}
	DDB(printk("ad1848_detect() - step C\n"));
	ad_write(devc, 0, 0x45);
	ad_write(devc, 1, 0xaa);

	if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
	{
		if (tmp2 == 0x8a)	/* AD1847 has few bits hardcoded to 1 */
			ad1847_flag = 1;
		else
		{
			DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
			return 0;
		}
	}

	/*
	 * The indirect register I12 has some read only bits. Let's
	 * try to change them.
	 */

	DDB(printk("ad1848_detect() - step D\n"));
	tmp = ad_read(devc, 12);
	ad_write(devc, 12, (~tmp) & 0x0f);

	if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
	{
		DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
		return 0;
	}
	
	/*
	 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
	 *   0x01=RevB and 0x0A=RevC.
	 */

	/*
	 * The original AD1848/CS4248 has just 15 indirect registers. This means
	 * that I0 and I16 should return the same value (etc.).
	 * However this doesn't work with CS4248. Actually it seems to be impossible
	 * to detect if the chip is a CS4231 or CS4248.
	 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
	 * with CS4231.
	 */

	/*
	 * OPTi 82C930 has mode2 control bit in another place. This test will fail
	 * with it. Accept this situation as a possible indication of this chip.
	 */

	DDB(printk("ad1848_detect() - step F\n"));
	ad_write(devc, 12, 0);	/* Mode2=disabled */

	for (i = 0; i < 16; i++)
	{
		if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
		{
			DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
			if (!ad1847_flag)
				optiC930 = 1;
			break;
		}
	}

	/*
	 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
	 * The bit 0x80 is always 1 in CS4248 and CS4231.
	 */

	DDB(printk("ad1848_detect() - step G\n"));

	if (ad_flags && *ad_flags == 400)
		*ad_flags = 0;
	else
		ad_write(devc, 12, 0x40);	/* Set mode2, clear 0x80 */


	if (ad_flags)
		*ad_flags = 0;

	tmp1 = ad_read(devc, 12);
	if (tmp1 & 0x80)
	{
		if (ad_flags)
			*ad_flags |= AD_F_CS4248;

		devc->chip_name = "CS4248";	/* Our best knowledge just now */
	}
	if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
	{
		/*
		 *      CS4231 detected - is it?
		 *
		 *      Verify that setting I0 doesn't change I16.
		 */
		
		DDB(printk("ad1848_detect() - step H\n"));
		ad_write(devc, 16, 0);	/* Set I16 to known value */

		ad_write(devc, 0, 0x45);
		if ((tmp1 = ad_read(devc, 16)) != 0x45)	/* No change -> CS4231? */
		{
			ad_write(devc, 0, 0xaa);
			if ((tmp1 = ad_read(devc, 16)) == 0xaa)	/* Rotten bits? */
			{
				DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
				return 0;
			}
			
			/*
			 * Verify that some bits of I25 are read only.
			 */

			DDB(printk("ad1848_detect() - step I\n"));
			tmp1 = ad_read(devc, 25);	/* Original bits */
			ad_write(devc, 25, ~tmp1);	/* Invert all bits */
			if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
			{
				int id;

				/*
				 *      It's at least CS4231
				 */

				devc->chip_name = "CS4231";
				devc->model = MD_4231;
				
				/*
				 * It could be an AD1845 or CS4231A as well.
				 * CS4231 and AD1845 report the same revision info in I25
				 * while the CS4231A reports different.
				 */

				id = ad_read(devc, 25);
				if ((id & 0xe7) == 0x80)	/* Device busy??? */
					id = ad_read(devc, 25);
				if ((id & 0xe7) == 0x80)	/* Device still busy??? */
					id = ad_read(devc, 25);
				DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));

                                if ((id & 0xe7) == 0x80) {
					/* 
					 * It must be a CS4231 or AD1845. The register I23 of
					 * CS4231 is undefined and it appears to be read only.
					 * AD1845 uses I23 for setting sample rate. Assume
					 * the chip is AD1845 if I23 is changeable.
					 */

					unsigned char   tmp = ad_read(devc, 23);
					ad_write(devc, 23, ~tmp);

					if (interwave)
					{
						devc->model = MD_IWAVE;
						devc->chip_name = "IWave";
					}
					else if (ad_read(devc, 23) != tmp)	/* AD1845 ? */
					{
						devc->chip_name = "AD1845";
						devc->model = MD_1845;
					}
					else if (cs4248_flag)
					{
						if (ad_flags)
							  *ad_flags |= AD_F_CS4248;
						devc->chip_name = "CS4248";
						devc->model = MD_1848;
						ad_write(devc, 12, ad_read(devc, 12) & ~0x40);	/* Mode2 off */
					}
					ad_write(devc, 23, tmp);	/* Restore */
				}
				else
				{
					switch (id & 0x1f) {
					case 3: /* CS4236/CS4235/CS42xB/CS4239 */
						{
							int xid;
							ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
							ad_write(devc, 23, 0x9c); /* select extended register 25 */
							xid = inb(io_Indexed_Data(devc));
							ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
							switch (xid & 0x1f)
							{
								case 0x00:
									devc->chip_name = "CS4237B(B)";
									devc->model = MD_42xB;
									break;
								case 0x08:
									/* Seems to be a 4238 ?? */
									devc->chip_name = "CS4238";
									devc->model = MD_42xB;
									break;
								case 0x09:
									devc->chip_name = "CS4238B";
									devc->model = MD_42xB;
									break;
								case 0x0b:
									devc->chip_name = "CS4236B";
									devc->model = MD_4236;
									break;
								case 0x10:
									devc->chip_name = "CS4237B";
									devc->model = MD_42xB;
									break;
								case 0x1d:
									devc->chip_name = "CS4235";
									devc->model = MD_4235;
									break;
								case 0x1e:
									devc->chip_name = "CS4239";
									devc->model = MD_4239;
									break;
								default:
									printk("Chip ident is %X.\n", xid&0x1F);
									devc->chip_name = "CS42xx";
									devc->model = MD_4232;
									break;
							}
						}
						break;

					case 2: /* CS4232/CS4232A */
						devc->chip_name = "CS4232";
						devc->model = MD_4232;
						break;
				
					case 0:
						if ((id & 0xe0) == 0xa0)
						{
							devc->chip_name = "CS4231A";
							devc->model = MD_4231A;
						}
						else
						{
							devc->chip_name = "CS4321";
							devc->model = MD_4231;
						}
						break;

					default: /* maybe */
						DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
                                                if (optiC930)
                                                {
                                                        devc->chip_name = "82C930";
                                                        devc->model = MD_C930;
                                                }
						else
						{
							devc->chip_name = "CS4231";
							devc->model = MD_4231;
						}
					}
				}
			}
			ad_write(devc, 25, tmp1);	/* Restore bits */

			DDB(printk("ad1848_detect() - step K\n"));
		}
	} else if (tmp1 == 0x0a) {
		/*
		 * Is it perhaps a SoundPro CMI8330?
		 * If so, then we should be able to change indirect registers
		 * greater than I15 after activating MODE2, even though reading
		 * back I12 does not show it.
		 */

		/*
		 * Let's try comparing register values
		 */
		for (i = 0; i < 16; i++) {
			if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
				DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
				soundpro = 1;
				devc->chip_name = "SoundPro CMI 8330";
				break;
			}
		}
	}

	DDB(printk("ad1848_detect() - step L\n"));
	if (ad_flags)
	{
		  if (devc->model != MD_1848)
			  *ad_flags |= AD_F_CS4231;
	}
	DDB(printk("ad1848_detect() - Detected OK\n"));

	if (devc->model == MD_1848 && ad1847_flag)
		devc->chip_name = "AD1847";


	if (sscape_flag == 1)
		devc->model = MD_1845_SSCAPE;

	return 1;
}

int ad1848_init (char *name, struct resource *ports, int irq, int dma_playback,
		int dma_capture, int share_dma, int *osp, struct module *owner)
{
	/*
	 * NOTE! If irq < 0, there is another driver which has allocated the IRQ
	 *   so that this driver doesn't need to allocate/deallocate it.
	 *   The actually used IRQ is ABS(irq).
	 */

	int my_dev;
	char dev_name[100];
	int e;

	ad1848_info  *devc = &adev_info[nr_ad1848_devs];

	ad1848_port_info *portc = NULL;

	devc->irq = (irq > 0) ? irq : 0;
	devc->open_mode = 0;
	devc->timer_ticks = 0;
	devc->dma1 = dma_playback;
	devc->dma2 = dma_capture;
	devc->subtype = cfg.card_subtype;
	devc->audio_flags = DMA_AUTOMODE;
	devc->playback_dev = devc->record_dev = 0;
	if (name != NULL)
		devc->name = name;

	if (name != NULL && name[0] != 0)
		sprintf(dev_name,
			"%s (%s)", name, devc->chip_name);
	else
		sprintf(dev_name,
			"Generic audio codec (%s)", devc->chip_name);

	rename_region(ports, devc->name);

	conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);

	if (devc->model == MD_1848 || devc->model == MD_C930)
		devc->audio_flags |= DMA_HARDSTOP;

	if (devc->model > MD_1848)
	{
		if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
			devc->audio_flags &= ~DMA_DUPLEX;
		else
			devc->audio_flags |= DMA_DUPLEX;
	}

	portc = kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
	if(portc==NULL) {
		release_region(devc->base, 4);
		return -1;
	}

	if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
					     dev_name,
					     &ad1848_audio_driver,
					     sizeof(struct audio_driver),
					     devc->audio_flags,
					     ad_format_mask[devc->model],
					     devc,
					     dma_playback,
					     dma_capture)) < 0)
	{
		release_region(devc->base, 4);
		kfree(portc);
		return -1;
	}
	
	audio_devs[my_dev]->portc = portc;
	audio_devs[my_dev]->mixer_dev = -1;
	if (owner)
		audio_devs[my_dev]->d->owner = owner;
	memset((char *) portc, 0, sizeof(*portc));

	nr_ad1848_devs++;

	ad1848_init_hw(devc);

	if (irq > 0)
	{
		devc->dev_no = my_dev;
		if (request_irq(devc->irq, adintr, 0, devc->name,
				(void *)(long)my_dev) < 0)
		{
			printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
			/* Don't free it either then.. */
			devc->irq = 0;
		}
		if (capabilities[devc->model].flags & CAP_F_TIMER)
		{
#ifndef CONFIG_SMP
			int x;
			unsigned char tmp = ad_read(devc, 16);
#endif			

			devc->timer_ticks = 0;

			ad_write(devc, 21, 0x00);	/* Timer MSB */
			ad_write(devc, 20, 0x10);	/* Timer LSB */
#ifndef CONFIG_SMP
			ad_write(devc, 16, tmp | 0x40);	/* Enable timer */
			for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
			ad_write(devc, 16, tmp & ~0x40);	/* Disable timer */

			if (devc->timer_ticks == 0)
				printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
			else
			{
				DDB(printk("Interrupt test OK\n"));
				devc->irq_ok = 1;
			}
#else
			devc->irq_ok = 1;
#endif			
		}
		else
			devc->irq_ok = 1;	/* Couldn't test. assume it's OK */
	} else if (irq < 0)
		irq2dev[-irq] = devc->dev_no = my_dev;

#ifndef EXCLUDE_TIMERS
	if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
	    devc->irq_ok)
		ad1848_tmr_install(my_dev);
#endif

	if (!share_dma)
	{
		if (sound_alloc_dma(dma_playback, devc->name))
			printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);

		if (dma_capture != dma_playback)
			if (sound_alloc_dma(dma_capture, devc->name))
				printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
	}

	if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
				     dev_name,
				     &ad1848_mixer_operations,
				     sizeof(struct mixer_operations),
				     devc)) >= 0)
	{
		audio_devs[my_dev]->mixer_dev = e;
		if (owner)
			mixer_devs[e]->owner = owner;
	}
	return my_dev;
}

int ad1848_control(int cmd, int arg)
{
	ad1848_info *devc;
	unsigned long flags;

	if (nr_ad1848_devs < 1)
		return -ENODEV;

	devc = &adev_info[nr_ad1848_devs - 1];

	switch (cmd)
	{
		case AD1848_SET_XTAL:	/* Change clock frequency of AD1845 (only ) */
			if (devc->model != MD_1845 || devc->model != MD_1845_SSCAPE)
				return -EINVAL;
			spin_lock_irqsave(&devc->lock,flags);
			ad_enter_MCE(devc);
			ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
			ad_leave_MCE(devc);
			spin_unlock_irqrestore(&devc->lock,flags);
			break;

		case AD1848_MIXER_REROUTE:
		{
			int o = (arg >> 8) & 0xff;
			int n = arg & 0xff;

			if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
				return -EINVAL;

			if (!(devc->supported_devices & (1 << o)) &&
			    !(devc->supported_rec_devices & (1 << o)))
				return -EINVAL;

			if (n == SOUND_MIXER_NONE)
			{	/* Just hide this control */
				ad1848_mixer_set(devc, o, 0);	/* Shut up it */
				devc->supported_devices &= ~(1 << o);
				devc->supported_rec_devices &= ~(1 << o);
				break;
			}

			/* Make the mixer control identified by o to appear as n */
			if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
				return -EINVAL;

			devc->mixer_reroute[n] = o;	/* Rename the control */
			if (devc->supported_devices & (1 << o))
				devc->supported_devices |= (1 << n);
			if (devc->supported_rec_devices & (1 << o))
				devc->supported_rec_devices |= (1 << n);

			devc->supported_devices &= ~(1 << o);
			devc->supported_rec_devices &= ~(1 << o);
		}
		break;
	}
	return 0;
}

void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
{
	int i, mixer, dev = 0;
	ad1848_info *devc = NULL;

	for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
	{
		if (adev_info[i].base == io_base)
		{
			devc = &adev_info[i];
			dev = devc->dev_no;
		}
	}
		
	if (devc != NULL)
	{
		kfree(audio_devs[dev]->portc);
		release_region(devc->base, 4);

		if (!share_dma)
		{
			if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
				free_irq(devc->irq, (void *)(long)devc->dev_no);

			sound_free_dma(dma_playback);

			if (dma_playback != dma_capture)
				sound_free_dma(dma_capture);

		}
		mixer = audio_devs[devc->dev_no]->mixer_dev;
		if(mixer>=0)
			sound_unload_mixerdev(mixer);

		nr_ad1848_devs--;
		for ( ; i < nr_ad1848_devs ; i++)
			adev_info[i] = adev_info[i+1];
	}
	else
		printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
}

static irqreturn_t adintr(int irq, void *dev_id)
{
	unsigned char status;
	ad1848_info *devc;
	int dev;
	int alt_stat = 0xff;
	unsigned char c930_stat = 0;
	int cnt = 0;

	dev = (long)dev_id;
	devc = (ad1848_info *) audio_devs[dev]->devc;

interrupt_again:		/* Jump back here if int status doesn't reset */

	status = inb(io_Status(devc));

	if (status == 0x80)
		printk(KERN_DEBUG "adintr: Why?\n");
	if (devc->model == MD_1848)
		outb((0), io_Status(devc));	/* Clear interrupt status */

	if (status & 0x01)
	{
		if (devc->model == MD_C930)
		{		/* 82C930 has interrupt status register in MAD16 register MC11 */

			spin_lock(&devc->lock);

			/* 0xe0e is C930 address port
			 * 0xe0f is C930 data port
			 */
			outb(11, 0xe0e);
			c930_stat = inb(0xe0f);
			outb((~c930_stat), 0xe0f);

			spin_unlock(&devc->lock);

			alt_stat = (c930_stat << 2) & 0x30;
		}
		else if (devc->model != MD_1848)
		{
			spin_lock(&devc->lock);
			alt_stat = ad_read(devc, 24);
			ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat);	/* Selective ack */
			spin_unlock(&devc->lock);
		}

		if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
		{
			DMAbuf_inputintr(devc->record_dev);
		}
		if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
		      (alt_stat & 0x10))
		{
			DMAbuf_outputintr(devc->playback_dev, 1);
		}
		if (devc->model != MD_1848 && (alt_stat & 0x40))	/* Timer interrupt */
		{
			devc->timer_ticks++;
#ifndef EXCLUDE_TIMERS
			if (timer_installed == dev && devc->timer_running)
				sound_timer_interrupt();
#endif
		}
	}
/*
 * Sometimes playback or capture interrupts occur while a timer interrupt
 * is being handled. The interrupt will not be retriggered if we don't
 * handle it now. Check if an interrupt is still pending and restart
 * the handler in this case.
 */
	if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
	{
		  goto interrupt_again;
	}
	return IRQ_HANDLED;
}

/*
 *	Experimental initialization sequence for the integrated sound system
 *	of the Compaq Deskpro M.
 */

static int init_deskpro_m(struct address_info *hw_config)
{
	unsigned char   tmp;

	if ((tmp = inb(0xc44)) == 0xff)
	{
		DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
		return 0;
	}

	outb(0x10, 0xc44);
	outb(0x40, 0xc45);
	outb(0x00, 0xc46);
	outb(0xe8, 0xc47);
	outb(0x14, 0xc44);
	outb(0x40, 0xc45);
	outb(0x00, 0xc46);
	outb(0xe8, 0xc47);
	outb(0x10, 0xc44);

	return 1;
}

/*
 *	Experimental initialization sequence for the integrated sound system
 *	of Compaq Deskpro XL.
 */

static int init_deskpro(struct address_info *hw_config)
{
	unsigned char   tmp;

	if ((tmp = inb(0xc44)) == 0xff)
	{
		DDB(printk("init_deskpro: Dead port 0xc44\n"));
		return 0;
	}
	outb((tmp | 0x04), 0xc44);	/* Select bank 1 */
	if (inb(0xc44) != 0x04)
	{
		DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
		return 0;
	}
	/*
	 * OK. It looks like a Deskpro so let's proceed.
	 */

	/*
	 * I/O port 0xc44 Audio configuration register.
	 *
	 * bits 0xc0:   Audio revision bits
	 *              0x00 = Compaq Business Audio
	 *              0x40 = MS Sound System Compatible (reset default)
	 *              0x80 = Reserved
	 *              0xc0 = Reserved
	 * bit 0x20:    No Wait State Enable
	 *              0x00 = Disabled (reset default, DMA mode)
	 *              0x20 = Enabled (programmed I/O mode)
	 * bit 0x10:    MS Sound System Decode Enable
	 *              0x00 = Decoding disabled (reset default)
	 *              0x10 = Decoding enabled
	 * bit 0x08:    FM Synthesis Decode Enable
	 *              0x00 = Decoding Disabled (reset default)
	 *              0x08 = Decoding enabled
	 * bit 0x04     Bank select
	 *              0x00 = Bank 0
	 *              0x04 = Bank 1
	 * bits 0x03    MSS Base address
	 *              0x00 = 0x530 (reset default)
	 *              0x01 = 0x604
	 *              0x02 = 0xf40
	 *              0x03 = 0xe80
	 */

#ifdef DEBUGXL
	/* Debug printing */
	printk("Port 0xc44 (before): ");
	outb((tmp & ~0x04), 0xc44);
	printk("%02x ", inb(0xc44));
	outb((tmp | 0x04), 0xc44);
	printk("%02x\n", inb(0xc44));
#endif

	/* Set bank 1 of the register */
	tmp = 0x58;		/* MSS Mode, MSS&FM decode enabled */

	switch (hw_config->io_base)
	{
		case 0x530:
			tmp |= 0x00;
			break;
		case 0x604:
			tmp |= 0x01;
			break;
		case 0xf40:
			tmp |= 0x02;
			break;
		case 0xe80:
			tmp |= 0x03;
			break;
		default:
			DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
			return 0;
	}
	outb((tmp & ~0x04), 0xc44);	/* Write to bank=0 */

#ifdef DEBUGXL
	/* Debug printing */
	printk("Port 0xc44 (after): ");
	outb((tmp & ~0x04), 0xc44);	/* Select bank=0 */
	printk("%02x ", inb(0xc44));
	outb((tmp | 0x04), 0xc44);	/* Select bank=1 */
	printk("%02x\n", inb(0xc44));
#endif

	/*
	 * I/O port 0xc45 FM Address Decode/MSS ID Register.
	 *
	 * bank=0, bits 0xfe:   FM synthesis Decode Compare bits 7:1 (default=0x88)
	 * bank=0, bit 0x01:    SBIC Power Control Bit
	 *                      0x00 = Powered up
	 *                      0x01 = Powered down
	 * bank=1, bits 0xfc:   MSS ID (default=0x40)
	 */

#ifdef DEBUGXL
	/* Debug printing */
	printk("Port 0xc45 (before): ");
	outb((tmp & ~0x04), 0xc44);	/* Select bank=0 */
	printk("%02x ", inb(0xc45));
	outb((tmp | 0x04), 0xc44);	/* Select bank=1 */
	printk("%02x\n", inb(0xc45));
#endif

	outb((tmp & ~0x04), 0xc44);	/* Select bank=0 */
	outb((0x88), 0xc45);	/* FM base 7:0 = 0x88 */
	outb((tmp | 0x04), 0xc44);	/* Select bank=1 */
	outb((0x10), 0xc45);	/* MSS ID = 0x10 (MSS port returns 0x04) */

#ifdef DEBUGXL
	/* Debug printing */
	printk("Port 0xc45 (after): ");
	outb((tmp & ~0x04), 0xc44);	/* Select bank=0 */
	printk("%02x ", inb(0xc45));
	outb((tmp | 0x04), 0xc44);	/* Select bank=1 */
	printk("%02x\n", inb(0xc45));
#endif


	/*
	 * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
	 *
	 * bank=0, bits 0xff:   FM synthesis Decode Compare bits 15:8 (default=0x03)
	 * bank=1, bits 0xff:   Audio addressing ASIC id
	 */

#ifdef DEBUGXL
	/* Debug printing */
	printk("Port 0xc46 (before): ");
	outb((tmp & ~0x04), 0xc44);	/* Select bank=0 */
	printk("%02x ", inb(0xc46));
	outb((tmp | 0x04), 0xc44);	/* Select bank=1 */
	printk("%02x\n", inb(0xc46));
#endif

	outb((tmp & ~0x04), 0xc44);	/* Select bank=0 */
	outb((0x03), 0xc46);	/* FM base 15:8 = 0x03 */
	outb((tmp | 0x04), 0xc44);	/* Select bank=1 */
	outb((0x11), 0xc46);	/* ASIC ID = 0x11 */

#ifdef DEBUGXL
	/* Debug printing */
	printk("Port 0xc46 (after): ");
	outb((tmp & ~0x04), 0xc44);	/* Select bank=0 */
	printk("%02x ", inb(0xc46));
	outb((tmp | 0x04), 0xc44);	/* Select bank=1 */
	printk("%02x\n", inb(0xc46));
#endif

	/*
	 * I/O port 0xc47 FM Address Decode Register.
	 *
	 * bank=0, bits 0xff:   Decode enable selection for various FM address bits
	 * bank=1, bits 0xff:   Reserved
	 */

#ifdef DEBUGXL
	/* Debug printing */
	printk("Port 0xc47 (before): ");
	outb((tmp & ~0x04), 0xc44);	/* Select bank=0 */
	printk("%02x ", inb(0xc47));
	outb((tmp | 0x04), 0xc44);	/* Select bank=1 */
	printk("%02x\n", inb(0xc47));
#endif

	outb((tmp & ~0x04), 0xc44);	/* Select bank=0 */
	outb((0x7c), 0xc47);	/* FM decode enable bits = 0x7c */
	outb((tmp | 0x04), 0xc44);	/* Select bank=1 */
	outb((0x00), 0xc47);	/* Reserved bank1 = 0x00 */

#ifdef DEBUGXL
	/* Debug printing */
	printk("Port 0xc47 (after): ");
	outb((tmp & ~0x04), 0xc44);	/* Select bank=0 */
	printk("%02x ", inb(0xc47));
	outb((tmp | 0x04), 0xc44);	/* Select bank=1 */
	printk("%02x\n", inb(0xc47));
#endif

	/*
	 * I/O port 0xc6f = Audio Disable Function Register
	 */

#ifdef DEBUGXL
	printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
#endif

	outb((0x80), 0xc6f);

#ifdef DEBUGXL
	printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
#endif

	return 1;
}

int probe_ms_sound(struct address_info *hw_config, struct resource *ports)
{
	unsigned char   tmp;

	DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));

	if (hw_config->card_subtype == 1)	/* Has no IRQ/DMA registers */
	{
		/* check_opl3(0x388, hw_config); */
		return ad1848_detect(ports, NULL, hw_config->osp);
	}

	if (deskpro_xl && hw_config->card_subtype == 2)	/* Compaq Deskpro XL */
	{
		if (!init_deskpro(hw_config))
			return 0;
	}

	if (deskpro_m)	/* Compaq Deskpro M */
	{
		if (!init_deskpro_m(hw_config))
			return 0;
	}

	/*
	   * Check if the IO port returns valid signature. The original MS Sound
	   * system returns 0x04 while some cards (AudioTrix Pro for example)
	   * return 0x00 or 0x0f.
	 */

	if ((tmp = inb(hw_config->io_base + 3)) == 0xff)	/* Bus float */
	{
		  int             ret;

		  DDB(printk("I/O address is inactive (%x)\n", tmp));
		  if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
			  return 0;
		  return 1;
	}
	DDB(printk("MSS signature = %x\n", tmp & 0x3f));
	if ((tmp & 0x3f) != 0x04 &&
	    (tmp & 0x3f) != 0x0f &&
	    (tmp & 0x3f) != 0x00)
	{
		int ret;

		MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
		DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
		if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
			return 0;

		hw_config->card_subtype = 1;
		return 1;
	}
	if ((hw_config->irq != 5)  &&
	    (hw_config->irq != 7)  &&
	    (hw_config->irq != 9)  &&
	    (hw_config->irq != 10) &&
	    (hw_config->irq != 11) &&
	    (hw_config->irq != 12))
	{
		printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
		return 0;
	}
	if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
	{
		  printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
		  return 0;
	}
	/*
	 * Check that DMA0 is not in use with a 8 bit board.
	 */

	if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
	{
		printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
		return 0;
	}
	if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
	{
		printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
		return 0;
	}
	return ad1848_detect(ports, NULL, hw_config->osp);
}

void attach_ms_sound(struct address_info *hw_config, struct resource *ports, struct module *owner)
{
	static signed char interrupt_bits[12] =
	{
		-1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
	};
	signed char     bits;
	char            dma2_bit = 0;

	static char     dma_bits[4] =
	{
		1, 2, 0, 3
	};

	int config_port = hw_config->io_base + 0;
	int version_port = hw_config->io_base + 3;
	int dma = hw_config->dma;
	int dma2 = hw_config->dma2;

	if (hw_config->card_subtype == 1)	/* Has no IRQ/DMA registers */
	{
		hw_config->slots[0] = ad1848_init("MS Sound System", ports,
						    hw_config->irq,
						    hw_config->dma,
						    hw_config->dma2, 0, 
						    hw_config->osp,
						    owner);
		return;
	}
	/*
	 * Set the IRQ and DMA addresses.
	 */

	bits = interrupt_bits[hw_config->irq];
	if (bits == -1)
	{
		printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
		release_region(ports->start, 4);
		release_region(ports->start - 4, 4);
		return;
	}
	outb((bits | 0x40), config_port);
	if ((inb(version_port) & 0x40) == 0)
		printk(KERN_ERR "[MSS: IRQ Conflict?]\n");

/*
 * Handle the capture DMA channel
 */

	if (dma2 != -1 && dma2 != dma)
	{
		if (!((dma == 0 && dma2 == 1) ||
			(dma == 1 && dma2 == 0) ||
			(dma == 3 && dma2 == 0)))
		{	/* Unsupported combination. Try to swap channels */
			int tmp = dma;

			dma = dma2;
			dma2 = tmp;
		}
		if ((dma == 0 && dma2 == 1) ||
			(dma == 1 && dma2 == 0) ||
			(dma == 3 && dma2 == 0))
		{
			dma2_bit = 0x04;	/* Enable capture DMA */
		}
		else
		{
			printk(KERN_WARNING "MSS: Invalid capture DMA\n");
			dma2 = dma;
		}
	}
	else
	{
		dma2 = dma;
	}

	hw_config->dma = dma;
	hw_config->dma2 = dma2;

	outb((bits | dma_bits[dma] | dma2_bit), config_port);	/* Write IRQ+DMA setup */

	hw_config->slots[0] = ad1848_init("MS Sound System", ports,
					  hw_config->irq,
					  dma, dma2, 0,
					  hw_config->osp,
					  THIS_MODULE);
}

void unload_ms_sound(struct address_info *hw_config)
{
	ad1848_unload(hw_config->io_base + 4,
		      hw_config->irq,
		      hw_config->dma,
		      hw_config->dma2, 0);
	sound_unload_audiodev(hw_config->slots[0]);
	release_region(hw_config->io_base, 4);
}

#ifndef EXCLUDE_TIMERS

/*
 * Timer stuff (for /dev/music).
 */

static unsigned int current_interval;

static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
{
	unsigned long   flags;
	ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
	unsigned long   xtal_nsecs;	/* nanoseconds per xtal oscillator tick */
	unsigned long   divider;

	spin_lock_irqsave(&devc->lock,flags);

	/*
	 * Length of the timer interval (in nanoseconds) depends on the
	 * selected crystal oscillator. Check this from bit 0x01 of I8.
	 *
	 * AD1845 has just one oscillator which has cycle time of 10.050 us
	 * (when a 24.576 MHz xtal oscillator is used).
	 *
	 * Convert requested interval to nanoseconds before computing
	 * the timer divider.
	 */

	if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
		xtal_nsecs = 10050;
	else if (ad_read(devc, 8) & 0x01)
		xtal_nsecs = 9920;
	else
		xtal_nsecs = 9969;

	divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;

	if (divider < 100)	/* Don't allow shorter intervals than about 1ms */
		divider = 100;

	if (divider > 65535)	/* Overflow check */
		divider = 65535;

	ad_write(devc, 21, (divider >> 8) & 0xff);	/* Set upper bits */
	ad_write(devc, 20, divider & 0xff);	/* Set lower bits */
	ad_write(devc, 16, ad_read(devc, 16) | 0x40);	/* Start the timer */
	devc->timer_running = 1;
	spin_unlock_irqrestore(&devc->lock,flags);

	return current_interval = (divider * xtal_nsecs + 500) / 1000;
}

static void ad1848_tmr_reprogram(int dev)
{
	/*
	 *    Audio driver has changed sampling rate so that a different xtal
	 *      oscillator was selected. We have to reprogram the timer rate.
	 */

	ad1848_tmr_start(dev, current_interval);
	sound_timer_syncinterval(current_interval);
}

static void ad1848_tmr_disable(int dev)
{
	unsigned long   flags;
	ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;

	spin_lock_irqsave(&devc->lock,flags);
	ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
	devc->timer_running = 0;
	spin_unlock_irqrestore(&devc->lock,flags);
}

static void ad1848_tmr_restart(int dev)
{
	unsigned long   flags;
	ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;

	if (current_interval == 0)
		return;

	spin_lock_irqsave(&devc->lock,flags);
	ad_write(devc, 16, ad_read(devc, 16) | 0x40);
	devc->timer_running = 1;
	spin_unlock_irqrestore(&devc->lock,flags);
}

static struct sound_lowlev_timer ad1848_tmr =
{
	0,
	2,
	ad1848_tmr_start,
	ad1848_tmr_disable,
	ad1848_tmr_restart
};

static int ad1848_tmr_install(int dev)
{
	if (timer_installed != -1)
		return 0;	/* Don't install another timer */

	timer_installed = ad1848_tmr.dev = dev;
	sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);

	return 1;
}
#endif /* EXCLUDE_TIMERS */

EXPORT_SYMBOL(ad1848_detect);
EXPORT_SYMBOL(ad1848_init);
EXPORT_SYMBOL(ad1848_unload);
EXPORT_SYMBOL(ad1848_control);
EXPORT_SYMBOL(probe_ms_sound);
EXPORT_SYMBOL(attach_ms_sound);
EXPORT_SYMBOL(unload_ms_sound);

static int __initdata io = -1;
static int __initdata irq = -1;
static int __initdata dma = -1;
static int __initdata dma2 = -1;
static int __initdata type = 0;

module_param(io, int, 0);		/* I/O for a raw AD1848 card */
module_param(irq, int, 0);		/* IRQ to use */
module_param(dma, int, 0);		/* First DMA channel */
module_param(dma2, int, 0);		/* Second DMA channel */
module_param(type, int, 0);		/* Card type */
module_param(deskpro_xl, bool, 0);	/* Special magic for Deskpro XL boxen */
module_param(deskpro_m, bool, 0);	/* Special magic for Deskpro M box */
module_param(soundpro, bool, 0);	/* More special magic for SoundPro chips */

#ifdef CONFIG_PNP
module_param(isapnp, int, 0);
module_param(isapnpjump, int, 0);
module_param(reverse, bool, 0);
MODULE_PARM_DESC(isapnp,	"When set to 0, Plug & Play support will be disabled");
MODULE_PARM_DESC(isapnpjump,	"Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
MODULE_PARM_DESC(reverse,	"When set to 1, will reverse ISAPnP search order");

static struct pnp_dev	*ad1848_dev  = NULL;

/* Please add new entries at the end of the table */
static struct {
	char *name;
	unsigned short	card_vendor, card_device,
			vendor, function;
	short mss_io, irq, dma, dma2;   /* index into isapnp table */
        int type;
} ad1848_isapnp_list[] __initdata = {
	{"CMI 8330 SoundPRO",
		ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
		ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001),
		0, 0, 0,-1, 0},
        {"CS4232 based card",
                ISAPNP_ANY_ID, ISAPNP_ANY_ID,
		ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000),
		0, 0, 0, 1, 0},
        {"CS4232 based card",
                ISAPNP_ANY_ID, ISAPNP_ANY_ID,
		ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100),
		0, 0, 0, 1, 0},
        {"OPL3-SA2 WSS mode",
        	ISAPNP_ANY_ID, ISAPNP_ANY_ID,
		ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021),
                1, 0, 0, 1, 1},
	{"Advanced Gravis InterWave Audio",
		ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
		ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000),
		0, 0, 0, 1, 0},
	{NULL}
};

static struct isapnp_device_id id_table[] __devinitdata = {
	{	ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
		ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), 0 },
        {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
		ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000), 0 },
        {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
		ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100), 0 },
	/* The main driver for this card is opl3sa2
        {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
		ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021), 0 },
	*/
	{	ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
		ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000), 0 },
	{0}
};

MODULE_DEVICE_TABLE(isapnp, id_table);

static struct pnp_dev *activate_dev(char *devname, char *resname, struct pnp_dev *dev)
{
	int err;

	err = pnp_device_attach(dev);
	if (err < 0)
		return(NULL);

	if((err = pnp_activate_dev(dev)) < 0) {
		printk(KERN_ERR "ad1848: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);

		pnp_device_detach(dev);

		return(NULL);
	}
	audio_activated = 1;
	return(dev);
}

static struct pnp_dev __init *ad1848_init_generic(struct pnp_card *bus,
				struct address_info *hw_config, int slot)
{

	/* Configure Audio device */
	if((ad1848_dev = pnp_find_dev(bus, ad1848_isapnp_list[slot].vendor, ad1848_isapnp_list[slot].function, NULL)))
	{
		if((ad1848_dev = activate_dev(ad1848_isapnp_list[slot].name, "ad1848", ad1848_dev)))
		{
			hw_config->io_base 	= pnp_port_start(ad1848_dev, ad1848_isapnp_list[slot].mss_io);
			hw_config->irq 		= pnp_irq(ad1848_dev, ad1848_isapnp_list[slot].irq);
			hw_config->dma 		= pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma);
			if(ad1848_isapnp_list[slot].dma2 != -1)
				hw_config->dma2 = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma2);
			else
				hw_config->dma2 = -1;
                        hw_config->card_subtype = ad1848_isapnp_list[slot].type;
		} else
			return(NULL);
	} else
		return(NULL);

	return(ad1848_dev);
}

static int __init ad1848_isapnp_init(struct address_info *hw_config, struct pnp_card *bus, int slot)
{
	char *busname = bus->name[0] ? bus->name : ad1848_isapnp_list[slot].name;

	/* Initialize this baby. */

	if(ad1848_init_generic(bus, hw_config, slot)) {
		/* We got it. */

		printk(KERN_NOTICE "ad1848: PnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
		       busname,
		       hw_config->io_base, hw_config->irq, hw_config->dma,
		       hw_config->dma2);
		return 1;
	}
	return 0;
}

static int __init ad1848_isapnp_probe(struct address_info *hw_config)
{
	static int first = 1;
	int i;

	/* Count entries in sb_isapnp_list */
	for (i = 0; ad1848_isapnp_list[i].card_vendor != 0; i++);
	i--;

	/* Check and adjust isapnpjump */
	if( isapnpjump < 0 || isapnpjump > i) {
		isapnpjump = reverse ? i : 0;
		printk(KERN_ERR "ad1848: Valid range for isapnpjump is 0-%d. Adjusted to %d.\n", i, isapnpjump);
	}

	if(!first || !reverse)
		i = isapnpjump;
	first = 0;
	while(ad1848_isapnp_list[i].card_vendor != 0) {
		static struct pnp_card *bus = NULL;

		while ((bus = pnp_find_card(
				ad1848_isapnp_list[i].card_vendor,
				ad1848_isapnp_list[i].card_device,
				bus))) {

			if(ad1848_isapnp_init(hw_config, bus, i)) {
				isapnpjump = i; /* start next search from here */
				return 0;
			}
		}
		i += reverse ? -1 : 1;
	}

	return -ENODEV;
}
#endif


static int __init init_ad1848(void)
{
	printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");

#ifdef CONFIG_PNP
	if(isapnp && (ad1848_isapnp_probe(&cfg) < 0) ) {
		printk(KERN_NOTICE "ad1848: No ISAPnP cards found, trying standard ones...\n");
		isapnp = 0;
	}
#endif

	if(io != -1) {
		struct resource *ports;
	        if( isapnp == 0 )
	        {
			if(irq == -1 || dma == -1) {
				printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
				return -EINVAL;
			}

			cfg.irq = irq;
			cfg.io_base = io;
			cfg.dma = dma;
			cfg.dma2 = dma2;
			cfg.card_subtype = type;
	        }

		ports = request_region(io + 4, 4, "ad1848");

		if (!ports)
			return -EBUSY;

		if (!request_region(io, 4, "WSS config")) {
			release_region(io + 4, 4);
			return -EBUSY;
		}

		if (!probe_ms_sound(&cfg, ports)) {
			release_region(io + 4, 4);
			release_region(io, 4);
			return -ENODEV;
		}
		attach_ms_sound(&cfg, ports, THIS_MODULE);
		loaded = 1;
	}
	return 0;
}

static void __exit cleanup_ad1848(void)
{
	if(loaded)
		unload_ms_sound(&cfg);

#ifdef CONFIG_PNP
	if(ad1848_dev){
		if(audio_activated)
			pnp_device_detach(ad1848_dev);
	}
#endif
}

module_init(init_ad1848);
module_exit(cleanup_ad1848);

#ifndef MODULE
static int __init setup_ad1848(char *str)
{
        /* io, irq, dma, dma2, type */
	int ints[6];
	
	str = get_options(str, ARRAY_SIZE(ints), ints);

	io	= ints[1];
	irq	= ints[2];
	dma	= ints[3];
	dma2	= ints[4];
	type	= ints[5];

	return 1;
}

__setup("ad1848=", setup_ad1848);	
#endif
MODULE_LICENSE("GPL");