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[
{
"PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
"BriefDescription": "imx8qxp: bytes of all masters read from ddr0",
"MetricName": "imx8qxp-ddr0-all-r",
"MetricExpr": "imx8_ddr0\\/read\\-cycles\\/ * 4 * 4",
"MetricGroup": "i.MX8QXP_DDR_MON",
"SocName": "i.MX8QXP"
},
{
"PublicDescription": "Calculate bytes all masters wirte to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.",
"BriefDescription": "imx8qxp: bytes of all masters write to ddr0",
"MetricName": "imx8qxp-ddr0-all-w",
"MetricExpr": "imx8_ddr0\\/write\\-cycles\\/ * 4 * 4",
"MetricGroup": "i.MX8QXP_DDR_MON",
"SocName": "i.MX8QXP"
}
]
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