u-boot: provide a mainline u-boot, based on 2019.07 rc1

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
author: Max Krummenacher <max.krummenacher@toradex.com> 2019-05-13 14:52:49 +0200
committer: Max Krummenacher <max.krummenacher@toradex.com> 2019-05-13 19:32:22 +0200
commit: 258adbe3d2ac9c7c8d31e5071c0689a4227dae09 (patch)
tree: 79c9c1168904b56bc9a1611f39ff31c3aefe4795
parent: dc4a695bba8f4becb8b821515e16079453ccd135 (diff)
31 files changed, 4467 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot-mainline/README b/recipes-bsp/u-boot-mainline/README
new file mode 100644
index 0000000..fc9f335
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/README
@@ -0,0 +1,4 @@
+Pulled from oe master @ ea527e5008c28c410806cd0a2e8513ff6dcac450
+
+Then change to U-Boot master and add our pending patches.
+http://git.denx.de/?p=u-boot.git;a=commit;h=b4ee6daad7a2604ca9466b2ba48de86cc27d381f
diff --git a/recipes-bsp/u-boot-mainline/files/0001-configs-colibri_imx6-don-t-configure-video-in-spl.patch b/recipes-bsp/u-boot-mainline/files/0001-configs-colibri_imx6-don-t-configure-video-in-spl.patch
new file mode 100644
index 0000000..674a186
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0001-configs-colibri_imx6-don-t-configure-video-in-spl.patch
@@ -0,0 +1,36 @@
+From 0db178f077486f63f5a83ed71e80734995306239 Mon Sep 17 00:00:00 2001
+From: Max Krummenacher <max.krummenacher@toradex.com>
+Date: Thu, 21 Sep 2017 15:21:33 +0200
+Subject: [PATCH 01/19] configs: colibri_imx6: don't configure video in spl
+
+The functionality is not needed in the SPL. It allows to remove
+code conditionally in the spl case in some drivers.
+
+Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
+---
+ include/configs/colibri_imx6.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
+index 129a42466d..87b402505e 100644
+--- a/include/configs/colibri_imx6.h
++++ b/include/configs/colibri_imx6.h
+@@ -66,6 +66,7 @@
+ #define CONFIG_USBD_HS
+ 
+ /* Framebuffer and LCD */
++#if !defined(CONFIG_SPL_BUILD)
+ #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+ #define CONFIG_VIDEO_BMP_RLE8
+ #define CONFIG_SPLASH_SCREEN
+@@ -76,6 +77,7 @@
+ #define CONFIG_CONSOLE_MUX
+ #define CONFIG_IMX_HDMI
+ #define CONFIG_IMX_VIDEO_SKIP
++#endif
+ 
+ /* allow to overwrite serial and ethaddr */
+ #define CONFIG_ENV_OVERWRITE
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0002-configs-apalis_imx6-don-t-configure-video-in-spl.patch b/recipes-bsp/u-boot-mainline/files/0002-configs-apalis_imx6-don-t-configure-video-in-spl.patch
new file mode 100644
index 0000000..5a395ff
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0002-configs-apalis_imx6-don-t-configure-video-in-spl.patch
@@ -0,0 +1,52 @@
+From a90cb933df44d2fa9ead3ce620313077f907b52a Mon Sep 17 00:00:00 2001
+From: Max Krummenacher <max.krummenacher@toradex.com>
+Date: Thu, 21 Sep 2017 15:29:33 +0200
+Subject: [PATCH 02/19] configs: apalis_imx6: don't configure video in spl
+
+The functionality is not needed in the SPL. It allows to remove
+code conditionally in the spl case in some drivers.
+
+Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
+
+Series-to: u-boot
+
+Series-cc: Anatolij Gustschin <agust@denx.de>, festevam@gmail.com <festevam@gmail.com>, sbabic@denx.de <sbabic@denx.de>
+Series-cc: jagan@openedev.com <jagan@openedev.com>, otavio@ossystems.com.br <otavio@ossystems.com.br>
+Series-cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>, Stefan Agner <stefan.agner@toradex.com>
+
+Cover-letter:
+configs: apalis/colibri imx6: don't configure video in spl
+
+This series remove unneeded SPL config options. This is needed
+to successfully compile with the following patch applied:
+https://lists.denx.de/pipermail/u-boot/2017-August/304010.html
+
+This series is available at http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next
+END
+---
+ include/configs/apalis_imx6.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
+index 91054d8c05..84d7c4b4f0 100644
+--- a/include/configs/apalis_imx6.h
++++ b/include/configs/apalis_imx6.h
+@@ -74,6 +74,7 @@
+ /* Client */
+ #define CONFIG_USBD_HS
+ 
++#if !defined(CONFIG_SPL_BUILD)
+ /* Framebuffer and LCD */
+ #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+ #define CONFIG_VIDEO_BMP_RLE8
+@@ -85,6 +86,7 @@
+ #define CONFIG_CONSOLE_MUX
+ #define CONFIG_IMX_HDMI
+ #define CONFIG_IMX_VIDEO_SKIP
++#endif
+ 
+ /* allow to overwrite serial and ethaddr */
+ #define CONFIG_ENV_OVERWRITE
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0003-usb-limit-USB_MAX_XFER_BLK-to-256.patch b/recipes-bsp/u-boot-mainline/files/0003-usb-limit-USB_MAX_XFER_BLK-to-256.patch
new file mode 100644
index 0000000..58526af
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0003-usb-limit-USB_MAX_XFER_BLK-to-256.patch
@@ -0,0 +1,67 @@
+From 70e00d1f20c331a1da991abc7b36f0f6a20751dc Mon Sep 17 00:00:00 2001
+From: Peng Fan <peng.fan@nxp.com>
+Date: Mon, 6 Jun 2016 13:53:43 +0800
+Subject: [PATCH 03/19] usb: limit USB_MAX_XFER_BLK to 256
+
+For Some USB mass storage devices, such as:
+"
+ - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA
+ - Class: (from Interface) Mass Storage
+ - PacketSize: 64  Configurations: 1
+ - Vendor: 0x0930  Product 0x6545 Version 1.16
+"
+When `usb read 0x80000000 0 0x2000`, we met
+"EHCI timed out on TD - token=0x80008d80".
+
+The devices does not support scsi VPD page, we are not able
+to get the maximum transfer length for READ(10)/WRITE(10).
+
+So we limit this to 256 blocks as READ(6).
+
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+(cherry picked from commit df0052575b2bc9d66ae73584768e1a457ed5d914)
+
+Series-to: u-boot@lists.denx.de
+
+Series-prefix: RFC
+
+Series-version: 3
+
+Series-changes: 2
+- Fixed spelling in comment as suggested by Igor.
+
+Series-changes: 3
+- Drop the reference to the NXP internal MLK-xxx tracking number as
+  suggested by Peng.
+
+Commit-notes:
+This comes from NXP's downstream and has proven to tremendously improve
+the situation with those odd USB mass storage aka memory sticks. This is
+why I post it here asking whether or not this may be something
+benefiting more people. Any feedback and suggestions are welcome.
+END
+---
+ common/usb_storage.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/common/usb_storage.c b/common/usb_storage.c
+index 8c889bb1a6..4e284645f5 100644
+--- a/common/usb_storage.c
++++ b/common/usb_storage.c
+@@ -949,7 +949,11 @@ static void usb_stor_set_max_xfer_blk(struct usb_device *udev,
+ 	 * there is enough free heap space left, but the SCSI READ(10) and
+ 	 * WRITE(10) commands are limited to 65535 blocks.
+ 	 */
+-	blk = USHRT_MAX;
++	/*
++	 * Some USB mass storage devices have issues, limiting this to 256
++	 * fixes this.
++	 */
++	blk = 256;
+ #else
+ 	blk = 20;
+ #endif
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0004-apalis_imx6-add-device-tree-to-makefile.patch b/recipes-bsp/u-boot-mainline/files/0004-apalis_imx6-add-device-tree-to-makefile.patch
new file mode 100644
index 0000000..7f285fd
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0004-apalis_imx6-add-device-tree-to-makefile.patch
@@ -0,0 +1,48 @@
+From 949abc726eab7477cee095d7696eca57247c8572 Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Date: Sun, 24 Mar 2019 03:31:04 +0100
+Subject: [PATCH 04/19] apalis_imx6: add device tree to makefile
+
+Add device tree to Makefile to avoid newly introduced error:
+
+Device Tree Source is not correctly specified.
+Please define 'CONFIG_DEFAULT_DEVICE_TREE'
+or build with 'DEVICE_TREE=<device_tree>' argument
+
+make[1]: *** [dts/Makefile:28: arch/arm/dts/imx6-apalis.dtb] Error 1
+make: *** [Makefile:1009: dts/dt.dtb] Error 2
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
+
+Series-to: u-boot@lists.denx.de
+Series-cc: Stefano Babic <sbabic@denx.de>
+
+Series-version: 3
+
+Series-changes: 2
+- Drop adding the colibri-imx6 device tree as Stefano already pulled v1
+  75992d0e7dfc ("apalis/colibri_imx6: add device trees to makefile") but
+  somehow dropped adding the apalis-imx6 one as well.
+
+Series-changes: 3
+- Added Igor's reviewed-by tag.
+---
+ arch/arm/dts/Makefile | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index dfa5b02958..e56a39e0b1 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -561,6 +561,7 @@ dtb-$(CONFIG_MX6ULL) += \
+ 	imx6ull-dart-6ul.dtb
+ 
+ dtb-$(CONFIG_ARCH_MX6) += \
++	imx6-apalis.dtb \
+ 	imx6-colibri.dtb
+ 
+ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0005-colibri-imx6ull-fix-usb-host-mode.patch b/recipes-bsp/u-boot-mainline/files/0005-colibri-imx6ull-fix-usb-host-mode.patch
new file mode 100644
index 0000000..efbce00
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0005-colibri-imx6ull-fix-usb-host-mode.patch
@@ -0,0 +1,37 @@
+From 853800ced8e96bfd2b57851226e528e342ec30e7 Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Date: Thu, 28 Mar 2019 18:40:47 +0100
+Subject: [PATCH 05/19] colibri-imx6ull: fix usb host mode
+
+This fixes an issue with USB host mode.
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
+
+Series-to: u-boot@lists.denx.de
+Series-cc: Stefano Babic <sbabic@denx.de>
+
+Commit-notes:
+I believe this is the one and only v3 change we missed as Stefano
+pulled v2 instead.
+END
+---
+ arch/arm/dts/imx6ull-colibri.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts
+index 4196cbdf22..6c847ab792 100644
+--- a/arch/arm/dts/imx6ull-colibri.dts
++++ b/arch/arm/dts/imx6ull-colibri.dts
+@@ -220,7 +220,7 @@
+ 
+ /* Colibri USBC */
+ &usbotg1 {
+-	dr_mode = "otg";
++	dr_mode = "host";
+ 	srp-disable;
+ 	hnp-disable;
+ 	adp-disable;
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0006-net-fec_mxc-not-access-reserved-register-on-i.MX8.patch b/recipes-bsp/u-boot-mainline/files/0006-net-fec_mxc-not-access-reserved-register-on-i.MX8.patch
new file mode 100644
index 0000000..ae74e32
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0006-net-fec_mxc-not-access-reserved-register-on-i.MX8.patch
@@ -0,0 +1,29 @@
+From 94e374129741c5e3b1fc248445f1acd0ce1564c2 Mon Sep 17 00:00:00 2001
+From: Peng Fan <peng.fan@nxp.com>
+Date: Mon, 15 Apr 2019 05:18:33 +0000
+Subject: [PATCH 06/19] net: fec_mxc: not access reserved register on i.MX8
+
+We should not access reserved register on i.MX8, otherwise met SERROR
+
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Acked-by: Joe Hershberger <joe.hershberger@ni.com>
+---
+ drivers/net/fec_mxc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
+index a672250e16..d7c080943a 100644
+--- a/drivers/net/fec_mxc.c
++++ b/drivers/net/fec_mxc.c
+@@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
+ 	writel(0x00000000, &fec->eth->gaddr2);
+ 
+ 	/* Do not access reserved register */
+-	if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) {
++	if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
+ 		/* clear MIB RAM */
+ 		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
+ 			writel(0, i);
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0007-imx-fix-building-for-i.mx8-without-spl.patch b/recipes-bsp/u-boot-mainline/files/0007-imx-fix-building-for-i.mx8-without-spl.patch
new file mode 100644
index 0000000..b4ebfad
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0007-imx-fix-building-for-i.mx8-without-spl.patch
@@ -0,0 +1,37 @@
+From 961ca9ed15a4f2c1f590f4dc02f69b93c773a90f Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Date: Fri, 26 Apr 2019 10:56:13 +0200
+Subject: [PATCH 07/19] imx: fix building for i.mx8 without spl
+
+Building with Travis CI complained and stopped with the following error:
++cc1: fatal error: opening output file spl/u-boot-spl.cfgout: No such
+file or directory
++compilation terminated.
+
+This fixes commit caceb739ea07 ("imx: build flash.bin for i.MX8") which
+took SPL being enabled on i.MX8 for granted.
+
+Reported-by: Stefano Babic <sbabic@denx.de>
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Reviewed-by: Peng Fan <peng.fan@nxp.com>
+---
+ arch/arm/mach-imx/Makefile | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
+index 37675d0558..6531c67fc6 100644
+--- a/arch/arm/mach-imx/Makefile
++++ b/arch/arm/mach-imx/Makefile
+@@ -107,7 +107,9 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%)
+ ifeq ($(CONFIG_ARCH_IMX8), y)
+ CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
+ IMAGE_TYPE := imx8image
++ifeq ($(CONFIG_SPL_BUILD),y)
+ SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi)
++endif
+ DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
+ else ifeq ($(CONFIG_ARCH_IMX8M), y)
+ IMAGE_TYPE := imx8mimage
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0008-board-toradex-add-colibri-imx8qxp-2gb-wb-it-v1.0b-mo.patch b/recipes-bsp/u-boot-mainline/files/0008-board-toradex-add-colibri-imx8qxp-2gb-wb-it-v1.0b-mo.patch
new file mode 100644
index 0000000..2b54935
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0008-board-toradex-add-colibri-imx8qxp-2gb-wb-it-v1.0b-mo.patch
@@ -0,0 +1,1228 @@
+From 52c2bae8472f47c6cb0b9d4877168160e0b7636a Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Date: Sat, 6 Apr 2019 13:42:24 +0200
+Subject: [PATCH 08/19] board: toradex: add colibri imx8qxp 2gb wb it v1.0b
+ module support
+
+This commit adds initial support for the Toradex Colibri iMX8QXP 2GB WB
+IT V1.0B module. Unlike the V1.0A early access samples exclusively
+booting from SD card, they are now strapped to boot from eFuses which
+are factory fused to properly boot from their on-module eMMC. U-Boot
+supports either booting from the on-module eMMC or may be used for
+recovery purpose using the universal update utility (uuu) aka mfgtools
+3.0.
+
+Functionality wise the following is known to be working:
+- eMMC and MMC/SD card
+- Ethernet
+- GPIOs
+- I2C
+
+Unfortunately, there is no USB functionality for the i.MX 8QXP as of
+yet.
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
+
+Series-to: u-boot@lists.denx.de
+Series-cc: Igor Opaniuk <igor.opaniuk@toradex.com>
+Series-cc: Stefano Babic <sbabic@denx.de>
+Series-cc: Peng Fan <peng.fan@nxp.com>
+
+Series-version: 6
+
+Series-changes: 2
+- Changed imx-atf git clone command to include initial branch
+  information as suggested by Igor.
+- Sorted board file includes alphabetically as suggested by Igor.
+- Got rid of SPL configuration in legacy header file as suggested by
+  Igor and the whole use of SPL on i.MX 8X anyway neither works well
+  nor makes any much sense at all.
+
+Series-changes: 3
+- Added Igor's reviewed-by tag.
+
+Series-changes: 4
+- Fixed SPDX as well as using SZ_ macros where applicable as suggested
+  by Igor.
+- Fixed superfluous trailing line continuation introduced by commit
+  0d331c035a09 ("imx: support i.MX8QM MEK board") in the Makefile plus
+  sorted stuff alphabetically again.
+- Applied changes similar to commit 3b9ac5415084 ("imx: 8qxp_mek: fix
+  fdt_file and console"). However, note that using ${baudrate} in
+  console= like that won't actually work!
+- Applied changes similar to commit e5b8f7e665aa ("imx8qxp: mek: enable
+  dm-spl for pm").
+
+Series-changes: 5
+- Keep alphabetical order of device trees in Makefile.
+- Order targets in Kconfig alphabetically.
+- Fix indentation in SPDX.
+- Remove stale includes from board file.
+- Take into account ahab-container being platform specific.
+- Use vidargs instead of multiple discrete video= in configuration.
+- Fix console baudrate specification.
+- Remove redundant CONFIG_SYS_MMC_ENV_DEV define and add some clarifying
+  comment.
+- Fix product name being Colibri iMX8X in a comment.
+- Remove obsolete CONFIG_NR_DRAM_BANKS.
+
+Series-changes: 6
+- Use firmware-imx-8.0 matching NXP's sumo-4.14.78-1.0.0_ga BSP as
+  suggested by Max during review of Apalis iMX8QM.
+- Drop anyway commented out board_gpio_init() stuff.
+- Drop Qualcomm (formwerly Atheros) AR8031 specific board_phy_config()
+  stuff not applicable to the Micrel PHY we are using as suggested by
+  Max during review of Apalis iMX8QM.
+
+Cover-letter:
+colibri imx8qxp 2gb wb it v1.0b module support
+
+This series fixes building for i.MX8 without SPL and adds support for
+more lpuart instances, cleans-up and extends the Toradex SKU handling
+and last but not least introduces support for the Toradex Colibri
+iMX8QXP 2GB WB IT V1.0B module.
+
+This series is available together with the last few clean-up patches
+on our git server [1] as well.
+
+[1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next
+END
+---
+ arch/arm/dts/Makefile                           |   3 +-
+ arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi    | 117 +++++++++
+ arch/arm/dts/fsl-imx8qxp-colibri.dts            | 328 ++++++++++++++++++++++++
+ arch/arm/mach-imx/imx8/Kconfig                  |  12 +-
+ board/toradex/colibri-imx8qxp/Kconfig           |  30 +++
+ board/toradex/colibri-imx8qxp/MAINTAINERS       |   9 +
+ board/toradex/colibri-imx8qxp/Makefile          |   6 +
+ board/toradex/colibri-imx8qxp/README            |  66 +++++
+ board/toradex/colibri-imx8qxp/colibri-imx8qxp.c | 160 ++++++++++++
+ board/toradex/colibri-imx8qxp/imximage.cfg      |  24 ++
+ configs/colibri-imx8qxp_defconfig               |  53 ++++
+ include/configs/colibri-imx8qxp.h               | 210 +++++++++++++++
+ 12 files changed, 1014 insertions(+), 4 deletions(-)
+ create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
+ create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts
+ create mode 100644 board/toradex/colibri-imx8qxp/Kconfig
+ create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS
+ create mode 100644 board/toradex/colibri-imx8qxp/Makefile
+ create mode 100644 board/toradex/colibri-imx8qxp/README
+ create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
+ create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg
+ create mode 100644 configs/colibri-imx8qxp_defconfig
+ create mode 100644 include/configs/colibri-imx8qxp.h
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index e56a39e0b1..598dc213e3 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -576,8 +576,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
+ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+ 
+ dtb-$(CONFIG_ARCH_IMX8) += \
+-	fsl-imx8qxp-mek.dtb \
+ 	fsl-imx8qm-mek.dtb \
++	fsl-imx8qxp-colibri.dtb \
++	fsl-imx8qxp-mek.dtb
+ 
+ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
+ 
+diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
+new file mode 100644
+index 0000000000..5b061f94ba
+--- /dev/null
++++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
+@@ -0,0 +1,117 @@
++// SPDX-License-Identifier: GPL-2.0+ OR X11
++/*
++ * Copyright 2019 Toradex AG
++ */
++
++&{/imx8qx-pm} {
++
++	u-boot,dm-spl;
++};
++
++&mu {
++	u-boot,dm-spl;
++};
++
++&clk {
++	u-boot,dm-spl;
++};
++
++&iomuxc {
++	u-boot,dm-spl;
++};
++
++&pd_lsio {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio0 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio1 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio2 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio3 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio4 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio5 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio6 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio7 {
++	u-boot,dm-spl;
++};
++
++&pd_conn {
++	u-boot,dm-spl;
++};
++
++&pd_conn_sdch0 {
++	u-boot,dm-spl;
++};
++
++&pd_conn_sdch1 {
++	u-boot,dm-spl;
++};
++
++&pd_conn_sdch2 {
++	u-boot,dm-spl;
++};
++
++&gpio0 {
++	u-boot,dm-spl;
++};
++
++&gpio1 {
++	u-boot,dm-spl;
++};
++
++&gpio2 {
++	u-boot,dm-spl;
++};
++
++&gpio3 {
++	u-boot,dm-spl;
++};
++
++&gpio4 {
++	u-boot,dm-spl;
++};
++
++&gpio5 {
++	u-boot,dm-spl;
++};
++
++&gpio6 {
++	u-boot,dm-spl;
++};
++
++&gpio7 {
++	u-boot,dm-spl;
++};
++
++&lpuart3 {
++	u-boot,dm-spl;
++};
++
++&usdhc1 {
++	u-boot,dm-spl;
++};
++
++&usdhc2 {
++	u-boot,dm-spl;
++};
+diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts
+new file mode 100644
+index 0000000000..0c20edf2cf
+--- /dev/null
++++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
+@@ -0,0 +1,328 @@
++// SPDX-License-Identifier: GPL-2.0+ OR X11
++/*
++ * Copyright 2019 Toradex AG
++ */
++
++/dts-v1/;
++
++#include "fsl-imx8qxp.dtsi"
++#include "fsl-imx8qxp-colibri-u-boot.dtsi"
++
++/ {
++	model = "Toradex Colibri iMX8QXP";
++	compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
++
++	chosen {
++		bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
++		stdout-path = &lpuart3;
++	};
++
++	reg_usbh_vbus: regulator-usbh-vbus {
++		compatible = "regulator-fixed";
++		pinctrl-names = "default";
++		pinctrl-0 = <&pinctrl_usbh1_reg>;
++		regulator-name = "usbh_vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
++	};
++};
++
++&iomuxc {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
++
++	colibri-imx8qxp {
++		pinctrl_lpuart0: lpuart0grp {
++			fsl,pins = <
++				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
++				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
++			>;
++		};
++
++		pinctrl_lpuart3: lpuart3grp {
++			fsl,pins = <
++				SC_P_FLEXCAN2_RX_ADMA_UART3_RX	0x06000020
++				SC_P_FLEXCAN2_TX_ADMA_UART3_TX	0x06000020
++			>;
++		};
++
++		pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
++			fsl,pins = <
++				SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */
++				SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x00000020 /* CTS */
++				SC_P_SAI1_RXC_LSIO_GPIO0_IO30		0x00000020 /* RTS */
++				SC_P_CSI_RESET_LSIO_GPIO3_IO03		0x00000020 /* DSR */
++				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x00000020 /* DCD */
++				SC_P_CSI_EN_LSIO_GPIO3_IO02		0x00000020 /* RI */
++			>;
++		};
++
++		pinctrl_fec1: fec1grp {
++			fsl,pins = <
++				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0 /* Use pads in 3.3V mode */
++				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0 /* Use pads in 3.3V mode */
++				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
++				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
++				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000061
++				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061
++				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000061
++				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000061
++				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000061
++				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000061
++				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000061
++				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x00000061
++			>;
++		};
++
++		pinctrl_gpio_bl_on: gpio-bl-on {
++			fsl,pins = <
++				SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12	0x00000040
++			>;
++		};
++
++		pinctrl_hog0: hog0grp {
++			fsl,pins = <
++				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0 /* Use pads in 3.3V mode */
++			>;
++		};
++
++		pinctrl_hog1: hog1grp {
++			fsl,pins = <
++				SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10	0x00000020 /*  45 */
++				SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	0x06000020 /*  65 */
++					SC_P_CSI_D07_CI_PI_D09		0x00000061
++				SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11	0x00000020 /*  69 */
++				SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13		0x00000020 /*  73 */
++				SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x00000020 /*  79 */
++					SC_P_CSI_D02_CI_PI_D04		0x00000061
++				SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03	0x06000020 /*  85 */
++					SC_P_CSI_D06_CI_PI_D08		0x00000061
++				SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x00000020 /*  95 */
++				SC_P_SAI0_RXD_LSIO_GPIO0_IO27		0x00000020 /*  97 */
++					SC_P_CSI_D03_CI_PI_D05		0x00000061
++				SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x00000020 /*  99 */
++				SC_P_SAI0_TXFS_LSIO_GPIO0_IO28		0x00000020 /* 101 */
++					SC_P_CSI_D00_CI_PI_D02		0x00000061
++				SC_P_SAI0_TXD_LSIO_GPIO0_IO25		0x00000020 /* 103 */
++					SC_P_CSI_D01_CI_PI_D03		0x00000061
++				SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x00000020 /* 105 */
++				SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20	0x00000020 /* 107 */
++				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x00000020 /* 127 */
++				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x00000020 /* 131 */
++				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x00000020 /* 133 */
++				SC_P_CSI_PCLK_LSIO_GPIO3_IO00		0x00000020 /*  96 */
++				SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21	0x00000020 /*  98 */
++				SC_P_SAI1_RXFS_LSIO_GPIO0_IO31		0x00000020 /* 100 */
++				SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22		0x00000020 /* 102 */
++				SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23	0x00000020 /* 104 */
++				SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24	0x00000020 /* 106 */
++			>;
++		};
++
++		pinctrl_hog2: hog2grp {
++			fsl,pins = <
++				SC_P_CSI_MCLK_LSIO_GPIO3_IO01		0x00000020 /*  75 */
++				SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14	0x00000020 /*  77 */
++				SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15	0x00000020 /*  89 */
++				SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16	0x00000020 /*  93 */
++			>;
++		};
++
++		/* Off Module I2C */
++		pinctrl_i2c1: i2c1grp {
++			fsl,pins = <
++				SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021
++				SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021
++			>;
++		};
++
++		/*INT*/
++		pinctrl_usb3503a: usb3503a-grp {
++			fsl,pins = <
++				SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061
++			>;
++		};
++
++		pinctrl_usbc_det: usbc-det {
++			fsl,pins = <
++				SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040
++			>;
++		};
++
++		pinctrl_usbh1_reg: usbh1-reg {
++			fsl,pins = <
++				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000040
++			>;
++		};
++
++		pinctrl_usdhc1: usdhc1grp {
++			fsl,pins = <
++				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
++				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
++				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
++				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
++				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
++				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
++				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
++				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
++				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
++				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
++				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
++				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
++			>;
++		};
++
++		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
++			fsl,pins = <
++				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
++				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
++				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
++				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
++				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
++				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
++				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
++				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
++				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
++				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
++				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
++				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
++			>;
++		};
++
++		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
++			fsl,pins = <
++				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
++				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
++				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
++				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
++				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
++				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
++				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
++				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
++				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
++				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
++				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
++				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
++			>;
++		};
++
++		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
++			fsl,pins = <
++				SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09	0x06000021
++			>;
++		};
++
++		pinctrl_usdhc2: usdhc2grp {
++			fsl,pins = <
++				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
++				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
++				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
++				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
++				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
++				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
++				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
++			>;
++		};
++
++		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
++			fsl,pins = <
++				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
++				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
++				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
++				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
++				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
++				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
++				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
++			>;
++		};
++
++		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
++			fsl,pins = <
++				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
++				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
++				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
++				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
++				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
++				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
++				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
++			>;
++		};
++	};
++};
++
++&lpuart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lpuart0>;
++	status = "okay";
++};
++
++&lpuart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
++	status = "okay";
++};
++
++&gpio0 {
++	status = "okay";
++};
++
++&gpio1 {
++	status = "okay";
++};
++
++&gpio3 {
++	status = "okay";
++};
++
++&gpio4 {
++	status = "okay";
++};
++
++&fec1 {
++	phy-handle = <&ethphy0>;
++	phy-mode = "rmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_fec1>;
++	status = "okay";
++
++	mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		ethphy0: ethernet-phy@2 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			max-speed = <100>;
++			reg = <2>;
++		};
++	};
++};
++
++&i2c1 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	clock-frequency = <100000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_i2c1>;
++	status = "okay";
++};
++
++&usdhc1 {
++	bus-width = <8>;
++	non-removable;
++	pinctrl-names = "default", "state_100mhz", "state_200mhz";
++	pinctrl-0 = <&pinctrl_usdhc1>;
++	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
++	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
++	status = "okay";
++};
++
++&usdhc2 {
++	bus-width = <4>;
++	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
++	pinctrl-names = "default", "state_100mhz", "state_200mhz";
++	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
++	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
++	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
++	status = "okay";
++};
+diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
+index c32f7dbb61..90223aaefc 100644
+--- a/arch/arm/mach-imx/imx8/Kconfig
++++ b/arch/arm/mach-imx/imx8/Kconfig
+@@ -27,8 +27,8 @@ choice
+ 	prompt "i.MX8 board select"
+ 	optional
+ 
+-config TARGET_IMX8QXP_MEK
+-	bool "Support i.MX8QXP MEK board"
++config TARGET_COLIBRI_IMX8QXP
++	bool "Support Colibri iMX8QXP module"
+ 	select BOARD_LATE_INIT
+ 	select IMX8QXP
+ 
+@@ -37,9 +37,15 @@ config TARGET_IMX8QM_MEK
+ 	select BOARD_LATE_INIT
+ 	select IMX8QM
+ 
++config TARGET_IMX8QXP_MEK
++	bool "Support i.MX8QXP MEK board"
++	select BOARD_LATE_INIT
++	select IMX8QXP
++
+ endchoice
+ 
+-source "board/freescale/imx8qxp_mek/Kconfig"
+ source "board/freescale/imx8qm_mek/Kconfig"
++source "board/freescale/imx8qxp_mek/Kconfig"
++source "board/toradex/colibri-imx8qxp/Kconfig"
+ 
+ endif
+diff --git a/board/toradex/colibri-imx8qxp/Kconfig b/board/toradex/colibri-imx8qxp/Kconfig
+new file mode 100644
+index 0000000000..340fe72816
+--- /dev/null
++++ b/board/toradex/colibri-imx8qxp/Kconfig
+@@ -0,0 +1,30 @@
++if TARGET_COLIBRI_IMX8QXP
++
++config SYS_BOARD
++	default "colibri-imx8qxp"
++
++config SYS_VENDOR
++	default "toradex"
++
++config SYS_CONFIG_NAME
++	default "colibri-imx8qxp"
++
++config TDX_CFG_BLOCK
++	default y
++
++config TDX_HAVE_MMC
++	default y
++
++config TDX_CFG_BLOCK_DEV
++	default "0"
++
++config TDX_CFG_BLOCK_PART
++	default "1"
++
++# Toradex config block in eMMC, at the end of 1st "boot sector"
++config TDX_CFG_BLOCK_OFFSET
++	default "-512"
++
++source "board/toradex/common/Kconfig"
++
++endif
+diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS b/board/toradex/colibri-imx8qxp/MAINTAINERS
+new file mode 100644
+index 0000000000..39a9eb79b7
+--- /dev/null
++++ b/board/toradex/colibri-imx8qxp/MAINTAINERS
+@@ -0,0 +1,9 @@
++Colibri iMX8QXP
++M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
++W:	http://developer.toradex.com/software/linux/linux-software
++S:	Maintained
++F:	arch/arm/dts/fsl-imx8qxp-colibri.dts
++F:	arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
++F:	board/toradex/colibri-imx8qxp/
++F:	configs/colibri-imx8qxp_defconfig
++F:	include/configs/colibri-imx8qxp.h
+diff --git a/board/toradex/colibri-imx8qxp/Makefile b/board/toradex/colibri-imx8qxp/Makefile
+new file mode 100644
+index 0000000000..db5a718416
+--- /dev/null
++++ b/board/toradex/colibri-imx8qxp/Makefile
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0+
++#
++# Copyright 2019 Toradex
++#
++
++obj-y += colibri-imx8qxp.o
+diff --git a/board/toradex/colibri-imx8qxp/README b/board/toradex/colibri-imx8qxp/README
+new file mode 100644
+index 0000000000..708bb3e51c
+--- /dev/null
++++ b/board/toradex/colibri-imx8qxp/README
+@@ -0,0 +1,66 @@
++U-Boot for the Toradex Colibri iMX8QXP V1.0B Module
++
++Quick Start
++===========
++
++- Build the ARM trusted firmware binary
++- Get scfw_tcm.bin and ahab-container.img
++- Build U-Boot
++- Load U-Boot binary using uuu
++- Flash U-Boot binary into the eMMC
++- Boot
++
++Get and Build the ARM Trusted Firmware
++======================================
++
++$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
++$ cd imx-atf/
++$ make PLAT=imx8qxp bl31
++
++Get scfw_tcm.bin and ahab-container.img
++=======================================
++
++$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
++$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin
++$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
++$ chmod +x firmware-imx-8.0.bin
++$ ./firmware-imx-8.0.bin
++
++Copy the following binaries to the U-Boot folder:
++
++$ cp imx-atf/build/imx8qxp/release/bl31.bin .
++$ cp u-boot/u-boot.bin .
++
++Copy the following firmware to the U-Boot folder:
++
++$ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
++
++Build U-Boot
++============
++
++$ make colibri-imx8qxp_defconfig
++$ make u-boot-dtb.imx
++
++Load the U-Boot Binary Using UUU
++================================
++
++Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
++
++https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
++
++Put the module into USB recovery aka serial downloader mode, connect USB device
++to your host and execute uuu:
++
++sudo ./uuu u-boot/u-boot-dtb.imx
++
++Flash the U-Boot Binary into the eMMC
++=====================================
++
++Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
++
++load mmc 1:1 $loadaddr u-boot-dtb.imx
++setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
++mmc dev 0 1
++mmc write ${loadaddr} 0x0 ${blkcnt}
++
++Boot
+diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
+new file mode 100644
+index 0000000000..aa8eaa0ea1
+--- /dev/null
++++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
+@@ -0,0 +1,160 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2019 Toradex
++ */
++
++#include <common.h>
++
++#include <asm/arch/clock.h>
++#include <asm/arch/imx8-pins.h>
++#include <asm/arch/iomux.h>
++#include <asm/arch/sci/sci.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/gpio.h>
++#include <asm/io.h>
++#include <environment.h>
++#include <errno.h>
++#include <linux/libfdt.h>
++
++#include "../common/tdx-cfg-block.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
++			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
++			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
++			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
++
++static iomux_cfg_t uart3_pads[] = {
++	SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
++	SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
++	/* Transceiver FORCEOFF# signal, mux to use pull-up */
++	SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL),
++};
++
++static void setup_iomux_uart(void)
++{
++	imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
++}
++
++int board_early_init_f(void)
++{
++	sc_pm_clock_rate_t rate;
++	sc_err_t err = 0;
++
++	/*
++	 * This works around that having only UART3 up the baudrate is 1.2M
++	 * instead of 115.2k. Set UART0 clock root to 80 MHz
++	 */
++	rate = 80000000;
++	err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
++	if (err != SC_ERR_NONE)
++		return 0;
++
++	/* Power up UART3 */
++	err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3, SC_PM_PW_MODE_ON);
++	if (err != SC_ERR_NONE)
++		return 0;
++
++	/* Set UART3 clock root to 80 MHz */
++	rate = 80000000;
++	err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER, &rate);
++	if (err != SC_ERR_NONE)
++		return 0;
++
++	/* Enable UART3 clock root */
++	err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER, true, false);
++	if (err != SC_ERR_NONE)
++		return 0;
++
++	setup_iomux_uart();
++
++	return 0;
++}
++
++#if IS_ENABLED(CONFIG_DM_GPIO)
++static void board_gpio_init(void)
++{
++	/* TODO */
++}
++#else
++static inline void board_gpio_init(void) {}
++#endif
++
++#if IS_ENABLED(CONFIG_FEC_MXC)
++#include <miiphy.h>
++
++int board_phy_config(struct phy_device *phydev)
++{
++	if (phydev->drv->config)
++		phydev->drv->config(phydev);
++
++	return 0;
++}
++#endif
++
++void build_info(void)
++{
++	u32 sc_build = 0, sc_commit = 0;
++
++	/* Get SCFW build and commit id */
++	sc_misc_build_info(-1, &sc_build, &sc_commit);
++	if (!sc_build) {
++		printf("SCFW does not support build info\n");
++		sc_commit = 0; /* Display 0 if build info not supported */
++	}
++	printf("Build: SCFW %x\n", sc_commit);
++}
++
++int checkboard(void)
++{
++	puts("Model: Toradex Colibri iMX8X\n");
++
++	build_info();
++	print_bootinfo();
++
++	return 0;
++}
++
++int board_init(void)
++{
++	board_gpio_init();
++
++	return 0;
++}
++
++void detail_board_ddr_info(void)
++{
++	puts("\nDDR    ");
++}
++
++/*
++ * Board specific reset that is system reset.
++ */
++void reset_cpu(ulong addr)
++{
++	/* TODO */
++}
++
++#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
++int ft_board_setup(void *blob, bd_t *bd)
++{
++	return ft_common_board_setup(blob, bd);
++}
++#endif
++
++int board_mmc_get_env_dev(int devno)
++{
++	return devno;
++}
++
++int board_late_init(void)
++{
++#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
++/* TODO move to common */
++	env_set("board_name", "Colibri iMX8QXP");
++	env_set("board_rev", "v1.0");
++#endif
++
++	return 0;
++}
+diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg b/board/toradex/colibri-imx8qxp/imximage.cfg
+new file mode 100644
+index 0000000000..1dcd13271d
+--- /dev/null
++++ b/board/toradex/colibri-imx8qxp/imximage.cfg
+@@ -0,0 +1,24 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2019 Toradex
++ *
++ * Refer doc/README.imx8image for more details about how-to configure
++ * and create imx8image boot image
++ */
++
++#define __ASSEMBLY__
++
++/* Boot from SD, sector size 0x400 */
++BOOT_FROM EMMC_FASTBOOT 0x400
++/* SoC type IMX8QX */
++SOC_TYPE IMX8QX
++/* Append seco container image */
++APPEND mx8qx-ahab-container.img
++/* Create the 2nd container */
++CONTAINER
++/* Add scfw image with exec attribute */
++IMAGE SCU mx8qx-colibri-scfw-tcm.bin
++/* Add ATF image with exec attribute */
++IMAGE A35 bl31.bin 0x80000000
++/* Add U-Boot image with load attribute */
++DATA A35 u-boot-dtb.bin 0x80020000
+diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig
+new file mode 100644
+index 0000000000..6dee0be35a
+--- /dev/null
++++ b/configs/colibri-imx8qxp_defconfig
+@@ -0,0 +1,53 @@
++CONFIG_ARM=y
++CONFIG_ARCH_IMX8=y
++CONFIG_SYS_TEXT_BASE=0x80020000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_TARGET_COLIBRI_IMX8QXP=y
++CONFIG_DISTRO_DEFAULTS=y
++CONFIG_NR_DRAM_BANKS=3
++CONFIG_FIT=y
++CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8qxp/imximage.cfg"
++CONFIG_LOG=y
++CONFIG_VERSION_VARIABLE=y
++# CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_BOARD_EARLY_INIT_F=y
++CONFIG_CMD_CPU=y
++# CONFIG_CMD_IMPORTENV is not set
++CONFIG_CMD_MEMTEST=y
++CONFIG_CMD_CLK=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_UUID=y
++CONFIG_CMD_EXT4_WRITE=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_CLK_IMX8=y
++CONFIG_CPU=y
++CONFIG_DM_GPIO=y
++CONFIG_MXC_GPIO=y
++CONFIG_DM_I2C=y
++CONFIG_SYS_I2C_IMX_LPI2C=y
++CONFIG_MISC=y
++CONFIG_DM_MMC=y
++CONFIG_PHYLIB=y
++CONFIG_PHY_ADDR_ENABLE=y
++CONFIG_PHY_MICREL=y
++CONFIG_DM_ETH=y
++CONFIG_FEC_MXC_SHARE_MDIO=y
++CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
++CONFIG_FEC_MXC=y
++CONFIG_MII=y
++CONFIG_PINCTRL=y
++CONFIG_PINCTRL_IMX8=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_IMX8_POWER_DOMAIN=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_SERIAL=y
++CONFIG_FSL_LPUART=y
++CONFIG_DM_THERMAL=y
++# CONFIG_EFI_LOADER is not set
+diff --git a/include/configs/colibri-imx8qxp.h b/include/configs/colibri-imx8qxp.h
+new file mode 100644
+index 0000000000..1bfeea6ab2
+--- /dev/null
++++ b/include/configs/colibri-imx8qxp.h
+@@ -0,0 +1,210 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2019 Toradex
++ */
++
++#ifndef __COLIBRI_IMX8QXP_H
++#define __COLIBRI_IMX8QXP_H
++
++#include <asm/arch/imx-regs.h>
++#include <linux/sizes.h>
++
++#define CONFIG_REMAKE_ELF
++
++#define CONFIG_DISPLAY_BOARDINFO_LATE
++
++#undef CONFIG_CMD_EXPORTENV
++#undef CONFIG_CMD_IMPORTENV
++#undef CONFIG_CMD_IMLS
++
++#undef CONFIG_CMD_CRC32
++#undef CONFIG_BOOTM_NETBSD
++
++#define CONFIG_FSL_ESDHC
++#define CONFIG_FSL_USDHC
++#define CONFIG_SYS_FSL_ESDHC_ADDR	0
++#define USDHC1_BASE_ADDR		0x5B010000
++#define USDHC2_BASE_ADDR		0x5B020000
++#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
++
++#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
++
++/* Networking */
++#define FEC_QUIRK_ENET_MAC
++
++#define CONFIG_IP_DEFRAG
++#define CONFIG_TFTP_BLOCKSIZE		SZ_4K
++#define CONFIG_TFTP_TSIZE
++
++#define CONFIG_IPADDR			192.168.10.2
++#define CONFIG_NETMASK			255.255.255.0
++#define CONFIG_SERVERIP			192.168.10.1
++
++#define MEM_LAYOUT_ENV_SETTINGS \
++	"fdt_addr_r=0x84000000\0" \
++	"kernel_addr_r=0x82000000\0" \
++	"ramdisk_addr_r=0x84100000\0"
++
++#ifdef CONFIG_AHAB_BOOT
++#define AHAB_ENV "sec_boot=yes\0"
++#else
++#define AHAB_ENV "sec_boot=no\0"
++#endif
++
++/* Boot M4 */
++#define M4_BOOT_ENV \
++	"m4_0_image=m4_0.bin\0" \
++	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
++		"${m4_0_image}\0" \
++	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
++
++#define MFG_NAND_PARTITION ""
++
++#define BOOT_TARGET_DEVICES(func) \
++	func(MMC, mmc, 0) \
++	func(MMC, mmc, 1) \
++	func(DHCP, dhcp, na)
++#include <config_distro_bootcmd.h>
++#undef BOOTENV_RUN_NET_USB_START
++#define BOOTENV_RUN_NET_USB_START ""
++
++#define CONFIG_MFG_ENV_SETTINGS \
++	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
++		"rdinit=/linuxrc g_mass_storage.stall=0 " \
++		"g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
++		"g_mass_storage.idProduct=0x37FF " \
++		"g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \
++		"${vidargs} clk_ignore_unused\0" \
++	"initrd_addr=0x83800000\0" \
++	"initrd_high=0xffffffff\0" \
++	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
++		"${fdt_addr};\0" \
++
++/* Initial environment variables */
++#define CONFIG_EXTRA_ENV_SETTINGS \
++	AHAB_ENV \
++	BOOTENV \
++	CONFIG_MFG_ENV_SETTINGS \
++	M4_BOOT_ENV \
++	MEM_LAYOUT_ENV_SETTINGS \
++	"boot_fdt=try\0" \
++	"bootscript=echo Running bootscript from mmc ...; source\0" \
++	"console=ttyLP3 earlycon\0" \
++	"fdt_addr=0x83000000\0"	\
++	"fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \
++	"fdt_high=0xffffffffffffffff\0"	\
++	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
++	"image=Image\0" \
++	"initrd_addr=0x83800000\0" \
++	"initrd_high=0xffffffffffffffff\0" \
++	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
++		"${script};\0" \
++	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
++	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
++	"mmcargs=setenv bootargs console=${console},${baudrate} " \
++		"root=PARTUUID=${uuid} rootwait " \
++	"mmcautodetect=yes\0" \
++	"mmcboot=echo Booting from mmc ...; " \
++		"run finduuid; run mmcargs; " \
++		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
++			"if run loadfdt; then " \
++				"booti ${loadaddr} - ${fdt_addr}; " \
++			"else " \
++				"echo WARN: Cannot load the DT; " \
++			"fi; " \
++		"else " \
++			"echo wait for boot; " \
++		"fi;\0" \
++	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
++	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
++	"netargs=setenv bootargs console=${console},${baudrate} " \
++		"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
++		"${vidargs}\0" \
++	"netboot=echo Booting from net ...; " \
++		"run netargs; " \
++		"if test ${ip_dyn} = yes; then " \
++			"setenv get_cmd dhcp; " \
++		"else " \
++			"setenv get_cmd tftp; " \
++		"fi; " \
++		"${get_cmd} ${loadaddr} ${image}; " \
++		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
++			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
++				"booti ${loadaddr} - ${fdt_addr}; " \
++			"else " \
++				"echo WARN: Cannot load the DT; " \
++			"fi; " \
++		"else " \
++			"booti; " \
++		"fi;\0" \
++	"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
++		"colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - " \
++		"${fdt_addr}\0" \
++	"panel=NULL\0" \
++	"script=boot.scr\0" \
++	"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
++
++#undef CONFIG_BOOTCOMMAND
++#define CONFIG_BOOTCOMMAND \
++	   "mmc dev ${mmcdev}; if mmc rescan; then " \
++		   "if run loadbootscript; then " \
++			   "run bootscript; " \
++		   "else " \
++			   "if run loadimage; then " \
++				   "run mmcboot; " \
++			   "else run netboot; " \
++			   "fi; " \
++		   "fi; " \
++	   "else booti ${loadaddr} - ${fdt_addr}; fi"
++
++/* Link Definitions */
++#define CONFIG_LOADADDR			0x80280000
++
++#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
++
++#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
++
++#define CONFIG_SYS_MEMTEST_START	0x88000000
++#define CONFIG_SYS_MEMTEST_END		0x89000000
++
++/* Environment in eMMC, before config block at the end of 1st "boot sector" */
++#define CONFIG_ENV_SIZE			SZ_8K
++#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
++					 CONFIG_TDX_CFG_BLOCK_OFFSET)
++#define CONFIG_SYS_MMC_ENV_DEV		0	/* USDHC1 eMMC */
++#define CONFIG_SYS_MMC_ENV_PART		1
++
++#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
++
++/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
++#define CONFIG_SYS_FSL_USDHC_NUM	2
++
++/* Size of malloc() pool */
++#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
++
++#define CONFIG_SYS_SDRAM_BASE		0x80000000
++#define PHYS_SDRAM_1			0x80000000
++#define PHYS_SDRAM_2			0x880000000
++#define PHYS_SDRAM_1_SIZE		SZ_2G		/* 2 GB */
++#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 GB */
++
++/* Serial */
++#define CONFIG_BAUDRATE			115200
++
++/* Monitor Command Prompt */
++#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
++#define CONFIG_SYS_CBSIZE		SZ_2K
++#define CONFIG_SYS_MAXARGS		64
++#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
++#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
++					sizeof(CONFIG_SYS_PROMPT) + 16)
++
++/* Generic Timer Definitions */
++#define COUNTER_FREQUENCY		8000000	/* 8MHz */
++
++#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
++#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
++
++#endif /* __COLIBRI_IMX8QXP_H */
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0009-board-toradex-drop-support.arm-maintainer-email.patch b/recipes-bsp/u-boot-mainline/files/0009-board-toradex-drop-support.arm-maintainer-email.patch
new file mode 100644
index 0000000..2fdca85
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0009-board-toradex-drop-support.arm-maintainer-email.patch
@@ -0,0 +1,42 @@
+From f381404c0c1bdeb981c515f62b3a6fde1ceaa73d Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Date: Tue, 23 Apr 2019 12:55:30 +0200
+Subject: [PATCH 09/19] board: toradex: drop support.arm maintainer email
+
+Drop Toradex ARM Support <support.arm@toradex.com> from maintainer email
+list as this just clogs our support ticketing system.
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Acked-by: Stefan Agner <stefan.agner@toradex.com>
+
+Series-to: u-boot@lists.denx.de
+---
+ board/toradex/colibri-imx6ull/MAINTAINERS | 1 -
+ board/toradex/colibri_imx7/MAINTAINERS    | 1 -
+ 2 files changed, 2 deletions(-)
+
+diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS
+index 7cda555984..626c1f94f9 100644
+--- a/board/toradex/colibri-imx6ull/MAINTAINERS
++++ b/board/toradex/colibri-imx6ull/MAINTAINERS
+@@ -1,6 +1,5 @@
+ Colibri iMX6ULL
+ M:	Stefan Agner <stefan.agner@toradex.com>
+-M:	Toradex ARM Support <support.arm@toradex.com>
+ W:	http://developer.toradex.com/software/linux/linux-software
+ W:	https://www.toradex.com/community
+ S:	Maintained
+diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS
+index f55f8045f4..cd0f9c9b2d 100644
+--- a/board/toradex/colibri_imx7/MAINTAINERS
++++ b/board/toradex/colibri_imx7/MAINTAINERS
+@@ -1,6 +1,5 @@
+ Colibri iMX7
+ M:	Stefan Agner <stefan.agner@toradex.com>
+-M:	Toradex ARM Support <support.arm@toradex.com>
+ W:	http://developer.toradex.com/software/linux/linux-software
+ W:	https://www.toradex.com/community
+ S:	Maintained
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0010-misc-imx8-add-sc_misc_get_temp.patch b/recipes-bsp/u-boot-mainline/files/0010-misc-imx8-add-sc_misc_get_temp.patch
new file mode 100644
index 0000000..fd50211
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0010-misc-imx8-add-sc_misc_get_temp.patch
@@ -0,0 +1,80 @@
+From 286d5ccf4ab601c8b93be40acaaeb4af6f6b2d49 Mon Sep 17 00:00:00 2001
+From: Peng Fan <peng.fan@nxp.com>
+Date: Fri, 12 Apr 2019 07:55:00 +0000
+Subject: [PATCH 10/19] misc: imx8: add sc_misc_get_temp
+
+Add sc_misc_get_temp to support get temperature
+
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+---
+ arch/arm/include/asm/arch-imx8/sci/sci.h          |  2 ++
+ arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h |  1 +
+ drivers/misc/imx8/scu_api.c                       | 28 +++++++++++++++++++++++
+ 3 files changed, 31 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h
+index 97377697f0..901b90d705 100644
+--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
++++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
+@@ -72,6 +72,8 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
+ void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
+ void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
+ int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
++int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
++		     s16 *celsius, s8 *tenths);
+ 
+ /* RM API */
+ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
+diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
+index 5d17b553d7..3629eb68d7 100644
+--- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
++++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
+@@ -26,5 +26,6 @@
+ #define SC_MISC_REL_CONTAINER	2U	/* Release container */
+ 
+ typedef u8 sc_misc_boot_status_t;
++typedef u8 sc_misc_temp_t;
+ 
+ #endif /* SC_MISC_API_H */
+diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
+index d9c4d5d784..031bc0048b 100644
+--- a/drivers/misc/imx8/scu_api.c
++++ b/drivers/misc/imx8/scu_api.c
+@@ -273,6 +273,34 @@ int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val)
+ 	return 0;
+ }
+ 
++int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
++		     s16 *celsius, s8 *tenths)
++{
++	struct udevice *dev = gd->arch.scu_dev;
++	int size = sizeof(struct sc_rpc_msg_s);
++	struct sc_rpc_msg_s msg;
++	int ret;
++
++	RPC_VER(&msg) = SC_RPC_VERSION;
++	RPC_SVC(&msg) = (u8)SC_RPC_SVC_MISC;
++	RPC_FUNC(&msg) = (u8)MISC_FUNC_GET_TEMP;
++	RPC_U16(&msg, 0U) = (u16)resource;
++	RPC_U8(&msg, 2U) = (u8)temp;
++	RPC_SIZE(&msg) = 2U;
++
++	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
++	if (ret < 0)
++		return ret;
++
++	if (celsius)
++		*celsius = RPC_I16(&msg, 0U);
++
++	if (tenths)
++		*tenths = RPC_I8(&msg, 2U);
++
++	return 0;
++}
++
+ /* RM */
+ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
+ {
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0011-thermal-add-i.MX8-thermal-driver.patch b/recipes-bsp/u-boot-mainline/files/0011-thermal-add-i.MX8-thermal-driver.patch
new file mode 100644
index 0000000..a87970c
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0011-thermal-add-i.MX8-thermal-driver.patch
@@ -0,0 +1,257 @@
+From 978f589e7c40976f78f177d312d50d9fb3e18303 Mon Sep 17 00:00:00 2001
+From: Peng Fan <peng.fan@nxp.com>
+Date: Fri, 12 Apr 2019 07:55:03 +0000
+Subject: [PATCH 11/19] thermal: add i.MX8 thermal driver
+
+Add i.MX8 thermal driver to support get temperature from SCU.
+
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+---
+ drivers/thermal/Kconfig           |   9 ++
+ drivers/thermal/Makefile          |   1 +
+ drivers/thermal/imx_scu_thermal.c | 203 ++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 213 insertions(+)
+ create mode 100644 drivers/thermal/imx_scu_thermal.c
+
+diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
+index a71b9be5fb..bdf8dc6fef 100644
+--- a/drivers/thermal/Kconfig
++++ b/drivers/thermal/Kconfig
+@@ -17,6 +17,15 @@ config IMX_THERMAL
+           cpufreq is used as the cooling device to throttle CPUs when the
+           passive trip is crossed.
+ 
++config IMX_SCU_THERMAL
++	bool "Temperature sensor driver for NXP i.MX8"
++	depends on ARCH_IMX8
++	help
++	  Support for Temperature sensors on NXP i.MX8.
++	  It supports one critical trip point and one passive trip point. The
++	  boot is hold to the cool device to throttle CPUs when the passive
++	  trip is crossed
++
+ config TI_DRA7_THERMAL
+         bool "Temperature sensor driver for TI dra7xx SOCs"
+         help
+diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
+index cc75e387e4..ef2929d180 100644
+--- a/drivers/thermal/Makefile
++++ b/drivers/thermal/Makefile
+@@ -5,4 +5,5 @@
+ 
+ obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o
+ obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
++obj-$(CONFIG_IMX_SCU_THERMAL) += imx_scu_thermal.o
+ obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o
+diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c
+new file mode 100644
+index 0000000000..7e17377b69
+--- /dev/null
++++ b/drivers/thermal/imx_scu_thermal.c
+@@ -0,0 +1,203 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2019 NXP
++ */
++
++#include <config.h>
++#include <common.h>
++#include <dm.h>
++#include <errno.h>
++#include <thermal.h>
++#include <dm/device-internal.h>
++#include <dm/device.h>
++#include <asm/arch/sci/sci.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++struct imx_sc_thermal_plat {
++	int critical;
++	int alert;
++	int polling_delay;
++	int id;
++	bool zone_node;
++};
++
++static int read_temperature(struct udevice *dev, int *temp)
++{
++	s16 celsius;
++	s8 tenths;
++	int ret;
++
++	sc_rsrc_t *sensor_rsrc = (sc_rsrc_t *)dev_get_driver_data(dev);
++
++	struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
++
++	if (!temp)
++		return -EINVAL;
++
++	ret = sc_misc_get_temp(-1, sensor_rsrc[pdata->id], SC_C_TEMP,
++			       &celsius, &tenths);
++	if (ret) {
++		printf("Error: get temperature failed! (error = %d)\n", ret);
++		return ret;
++	}
++
++	*temp = celsius * 1000 + tenths * 100;
++
++	return 0;
++}
++
++int imx_sc_thermal_get_temp(struct udevice *dev, int *temp)
++{
++	struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
++	int cpu_temp = 0;
++	int ret;
++
++	ret = read_temperature(dev, &cpu_temp);
++	if (ret)
++		return ret;
++
++	while (cpu_temp >= pdata->alert) {
++		printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)",
++		       cpu_temp, pdata->alert, pdata->critical);
++		puts(" waiting...\n");
++		mdelay(pdata->polling_delay);
++		ret = read_temperature(dev, &cpu_temp);
++		if (ret)
++			return ret;
++	}
++
++	*temp = cpu_temp / 1000;
++
++	return 0;
++}
++
++static const struct dm_thermal_ops imx_sc_thermal_ops = {
++	.get_temp	= imx_sc_thermal_get_temp,
++};
++
++static int imx_sc_thermal_probe(struct udevice *dev)
++{
++	debug("%s dev name %s\n", __func__, dev->name);
++	return 0;
++}
++
++static int imx_sc_thermal_bind(struct udevice *dev)
++{
++	struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
++	int reg, ret;
++	int offset;
++	const char *name;
++	const void *prop;
++
++	debug("%s dev name %s\n", __func__, dev->name);
++
++	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "compatible",
++			   NULL);
++	if (!prop)
++		return 0;
++
++	pdata->zone_node = 1;
++
++	reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "tsens-num", 0);
++	if (reg == 0) {
++		printf("%s: no temp sensor number provided!\n", __func__);
++		return -EINVAL;
++	}
++
++	offset = fdt_subnode_offset(gd->fdt_blob, 0, "thermal-zones");
++	fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
++		/* Bind the subnode to this driver */
++		name = fdt_get_name(gd->fdt_blob, offset, NULL);
++
++		ret = device_bind_with_driver_data(dev, dev->driver, name,
++						   dev->driver_data,
++						   offset_to_ofnode(offset),
++						   NULL);
++		if (ret)
++			printf("Error binding driver '%s': %d\n",
++			       dev->driver->name, ret);
++	}
++	return 0;
++}
++
++static int imx_sc_thermal_ofdata_to_platdata(struct udevice *dev)
++{
++	struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev);
++	struct fdtdec_phandle_args args;
++	const char *type;
++	int ret;
++	int trips_np;
++
++	debug("%s dev name %s\n", __func__, dev->name);
++
++	if (pdata->zone_node)
++		return 0;
++
++	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
++					     "thermal-sensors",
++					     "#thermal-sensor-cells",
++					     0, 0, &args);
++	if (ret)
++		return ret;
++
++	if (args.node != dev_of_offset(dev->parent))
++		return -EFAULT;
++
++	if (args.args_count >= 1)
++		pdata->id = args.args[0];
++	else
++		pdata->id = 0;
++
++	debug("args.args_count %d, id %d\n", args.args_count, pdata->id);
++
++	pdata->polling_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
++					      "polling-delay", 1000);
++
++	trips_np = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
++				      "trips");
++	fdt_for_each_subnode(trips_np, gd->fdt_blob, trips_np) {
++		type = fdt_getprop(gd->fdt_blob, trips_np, "type", NULL);
++		if (type) {
++			if (strcmp(type, "critical") == 0) {
++				pdata->critical = fdtdec_get_int(gd->fdt_blob,
++								 trips_np,
++								 "temperature",
++								 85);
++			} else if (strcmp(type, "passive") == 0) {
++				pdata->alert = fdtdec_get_int(gd->fdt_blob,
++							      trips_np,
++							      "temperature",
++							      80);
++			}
++		}
++	}
++
++	debug("id %d polling_delay %d, critical %d, alert %d\n", pdata->id,
++	      pdata->polling_delay, pdata->critical, pdata->alert);
++
++	return 0;
++}
++
++static const sc_rsrc_t imx8qxp_sensor_rsrc[] = {
++	SC_R_SYSTEM, SC_R_DRC_0, SC_R_PMIC_0,
++	SC_R_PMIC_1, SC_R_PMIC_2,
++};
++
++static const struct udevice_id imx_sc_thermal_ids[] = {
++	{ .compatible = "nxp,imx8qxp-sc-tsens", .data =
++		(ulong)&imx8qxp_sensor_rsrc, },
++	{ }
++};
++
++U_BOOT_DRIVER(imx_sc_thermal) = {
++	.name	= "imx_sc_thermal",
++	.id	= UCLASS_THERMAL,
++	.ops	= &imx_sc_thermal_ops,
++	.of_match = imx_sc_thermal_ids,
++	.bind = imx_sc_thermal_bind,
++	.probe	= imx_sc_thermal_probe,
++	.ofdata_to_platdata = imx_sc_thermal_ofdata_to_platdata,
++	.platdata_auto_alloc_size = sizeof(struct imx_sc_thermal_plat),
++	.flags  = DM_FLAG_PRE_RELOC,
++};
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0012-imx8-cpu-get-temperature-when-print-cpu-desc.patch b/recipes-bsp/u-boot-mainline/files/0012-imx8-cpu-get-temperature-when-print-cpu-desc.patch
new file mode 100644
index 0000000..f700305
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0012-imx8-cpu-get-temperature-when-print-cpu-desc.patch
@@ -0,0 +1,75 @@
+From 82467cb2172d0470413876ad398d032a649a7e11 Mon Sep 17 00:00:00 2001
+From: Peng Fan <peng.fan@nxp.com>
+Date: Fri, 12 Apr 2019 07:55:06 +0000
+Subject: [PATCH 12/19] imx8: cpu: get temperature when print cpu desc
+
+Read the temperature when print cpu inforation.
+
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+---
+ arch/arm/mach-imx/imx8/cpu.c | 35 +++++++++++++++++++++++++++++++++--
+ 1 file changed, 33 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
+index 2c425357b5..12716e7e9e 100644
+--- a/arch/arm/mach-imx/imx8/cpu.c
++++ b/arch/arm/mach-imx/imx8/cpu.c
+@@ -11,6 +11,7 @@
+ #include <dm/lists.h>
+ #include <dm/uclass.h>
+ #include <errno.h>
++#include <thermal.h>
+ #include <asm/arch/sci/sci.h>
+ #include <asm/arch/sys_proto.h>
+ #include <asm/arch-imx/cpu.h>
+@@ -573,15 +574,45 @@ const char *get_core_name(void)
+ 		return "?";
+ }
+ 
++#if defined(CONFIG_IMX_SCU_THERMAL)
++static int cpu_imx_get_temp(void)
++{
++	struct udevice *thermal_dev;
++	int cpu_tmp, ret;
++
++	ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
++					&thermal_dev);
++
++	if (!ret) {
++		ret = thermal_get_temp(thermal_dev, &cpu_tmp);
++		if (ret)
++			return 0xdeadbeef;
++	} else {
++		return 0xdeadbeef;
++	}
++
++	return cpu_tmp;
++}
++#endif
++
+ int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
+ {
+ 	struct cpu_imx_platdata *plat = dev_get_platdata(dev);
++	int ret;
+ 
+ 	if (size < 100)
+ 		return -ENOSPC;
+ 
+-	snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n",
+-		 plat->type, plat->rev, plat->name, plat->freq_mhz);
++	ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
++		       plat->type, plat->rev, plat->name, plat->freq_mhz);
++
++	if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
++		buf = buf + ret;
++		size = size - ret;
++		ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
++	}
++
++	snprintf(buf + ret, size - ret, "\n");
+ 
+ 	return 0;
+ }
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0013-imx-imx8dx-qxp-enable-thermal.patch b/recipes-bsp/u-boot-mainline/files/0013-imx-imx8dx-qxp-enable-thermal.patch
new file mode 100644
index 0000000..3caa779
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0013-imx-imx8dx-qxp-enable-thermal.patch
@@ -0,0 +1,103 @@
+From ca9e4fef07365d39566288a45670c75d320e2f32 Mon Sep 17 00:00:00 2001
+From: Peng Fan <peng.fan@nxp.com>
+Date: Fri, 12 Apr 2019 07:55:09 +0000
+Subject: [PATCH 13/19] imx: imx8dx/qxp: enable thermal
+
+Add thermal dts node
+Enable thermal in defconfig
+
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+---
+ arch/arm/dts/fsl-imx8dx.dtsi  | 56 +++++++++++++++++++++++++++++++++++++++++++
+ configs/imx8qxp_mek_defconfig |  2 ++
+ 2 files changed, 58 insertions(+)
+
+diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
+index 715abb413d..4fc87a9fc8 100644
+--- a/arch/arm/dts/fsl-imx8dx.dtsi
++++ b/arch/arm/dts/fsl-imx8dx.dtsi
+@@ -11,6 +11,7 @@
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/pinctrl/pads-imx8qxp.h>
+ #include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/thermal/thermal.h>
+ 
+ / {
+ 	model = "Freescale i.MX8DX";
+@@ -543,6 +544,61 @@
+ 		power-domains = <&pd_conn_enet1>;
+ 		status = "disabled";
+ 	};
++
++	tsens: thermal-sensor {
++		compatible = "nxp,imx8qxp-sc-tsens";
++		/* number of the temp sensor on the chip */
++		tsens-num = <2>;
++		#thermal-sensor-cells = <1>;
++	};
++
++	thermal_zones: thermal-zones {
++		/* cpu thermal */
++		cpu-thermal0 {
++			polling-delay-passive = <250>;
++			polling-delay = <2000>;
++			/*the slope and offset of the temp sensor */
++			thermal-sensors = <&tsens 0>;
++			trips {
++				cpu_alert0: trip0 {
++					temperature = <107000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				cpu_crit0: trip1 {
++					temperature = <127000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++			cooling-maps {
++				map0 {
++					trip = <&cpu_alert0>;
++					cooling-device =
++					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
++			};
++		};
++
++		drc-thermal0 {
++			polling-delay-passive = <250>;
++			polling-delay = <2000>;
++			thermal-sensors = <&tsens 1>;
++			status = "disabled";
++			trips {
++				drc_alert0: trip0 {
++					temperature = <107000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				drc_crit0: trip1 {
++					temperature = <127000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++		};
++	};
+ };
+ 
+ &A35_0 {
+diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
+index 2fb2fdf7ff..6101f62087 100644
+--- a/configs/imx8qxp_mek_defconfig
++++ b/configs/imx8qxp_mek_defconfig
+@@ -74,5 +74,7 @@ CONFIG_DM_REGULATOR_GPIO=y
+ CONFIG_SPL_DM_REGULATOR_GPIO=y
+ CONFIG_DM_SERIAL=y
+ CONFIG_FSL_LPUART=y
++CONFIG_DM_THERMAL=y
++CONFIG_IMX_SCU_THERMAL=y
+ CONFIG_SPL_TINY_MEMSET=y
+ # CONFIG_EFI_LOADER is not set
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0014-arm-dts-imx8qm-add-lpuart1-lpuart2-lpuart3-lpuart4.patch b/recipes-bsp/u-boot-mainline/files/0014-arm-dts-imx8qm-add-lpuart1-lpuart2-lpuart3-lpuart4.patch
new file mode 100644
index 0000000..c5ff58b
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0014-arm-dts-imx8qm-add-lpuart1-lpuart2-lpuart3-lpuart4.patch
@@ -0,0 +1,122 @@
+From 32ff3f8ecf03f60627d4e92de9a34b2fc2cdaf4d Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Date: Mon, 29 Apr 2019 01:22:42 +0200
+Subject: [PATCH 14/19] arm: dts: imx8qm: add lpuart1, lpuart2, lpuart3,
+ lpuart4
+
+Add support for lpuart1, lpuart2, lpuart3 and lpuart4.
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
+---
+ arch/arm/dts/fsl-imx8qm.dtsi | 80 ++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+
+diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
+index b39c40bd98..db01959990 100644
+--- a/arch/arm/dts/fsl-imx8qm.dtsi
++++ b/arch/arm/dts/fsl-imx8qm.dtsi
+@@ -22,6 +22,10 @@
+ 		ethernet0 = &fec1;
+ 		ethernet1 = &fec2;
+ 		serial0 = &lpuart0;
++		serial1 = &lpuart1;
++		serial2 = &lpuart2;
++		serial3 = &lpuart3;
++		serial4 = &lpuart4;
+ 		mmc0 = &usdhc1;
+ 		mmc1 = &usdhc2;
+ 		mmc2 = &usdhc3;
+@@ -193,6 +197,30 @@
+ 				power-domains = <&pd_dma>;
+ 				wakeup-irq = <345>;
+ 			};
++			pd_dma_lpuart1: PD_DMA_UART1 {
++				reg = <SC_R_UART_1>;
++				#power-domain-cells = <0>;
++				power-domains = <&pd_dma>;
++				wakeup-irq = <346>;
++			};
++			pd_dma_lpuart2: PD_DMA_UART2 {
++				reg = <SC_R_UART_2>;
++				#power-domain-cells = <0>;
++				power-domains = <&pd_dma>;
++				wakeup-irq = <347>;
++			};
++			pd_dma_lpuart3: PD_DMA_UART3 {
++				reg = <SC_R_UART_3>;
++				#power-domain-cells = <0>;
++				power-domains = <&pd_dma>;
++				wakeup-irq = <348>;
++			};
++			pd_dma_lpuart4: PD_DMA_UART4 {
++				reg = <SC_R_UART_4>;
++				#power-domain-cells = <0>;
++				power-domains = <&pd_dma>;
++				wakeup-irq = <349>;
++			};
+ 		};
+ 	};
+ 
+@@ -297,6 +325,58 @@
+ 		status = "disabled";
+ 	};
+ 
++	lpuart1: serial@5a070000 {
++		compatible = "fsl,imx8qm-lpuart";
++		reg = <0x0 0x5a070000 0x0 0x1000>;
++		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&clk IMX8QM_UART1_CLK>,
++			 <&clk IMX8QM_UART1_IPG_CLK>;
++		clock-names = "per", "ipg";
++		assigned-clocks = <&clk IMX8QM_UART1_CLK>;
++		assigned-clock-rates = <80000000>;
++		power-domains = <&pd_dma_lpuart1>;
++		status = "disabled";
++	};
++
++	lpuart2: serial@5a080000 {
++		compatible = "fsl,imx8qm-lpuart";
++		reg = <0x0 0x5a080000 0x0 0x1000>;
++		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&clk IMX8QM_UART2_CLK>,
++			 <&clk IMX8QM_UART2_IPG_CLK>;
++		clock-names = "per", "ipg";
++		assigned-clocks = <&clk IMX8QM_UART2_CLK>;
++		assigned-clock-rates = <80000000>;
++		power-domains = <&pd_dma_lpuart2>;
++		status = "disabled";
++	};
++
++	lpuart3: serial@5a090000 {
++		compatible = "fsl,imx8qm-lpuart";
++		reg = <0x0 0x5a090000 0x0 0x1000>;
++		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&clk IMX8QM_UART3_CLK>,
++			 <&clk IMX8QM_UART3_IPG_CLK>;
++		clock-names = "per", "ipg";
++		assigned-clocks = <&clk IMX8QM_UART3_CLK>;
++		assigned-clock-rates = <80000000>;
++		power-domains = <&pd_dma_lpuart3>;
++		status = "disabled";
++	};
++
++	lpuart4: serial@5a0a0000 {
++		compatible = "fsl,imx8qm-lpuart";
++		reg = <0x0 0x5a0a0000 0x0 0x1000>;
++		interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&clk IMX8QM_UART4_CLK>,
++			 <&clk IMX8QM_UART4_IPG_CLK>;
++		clock-names = "per", "ipg";
++		assigned-clocks = <&clk IMX8QM_UART4_CLK>;
++		assigned-clock-rates = <80000000>;
++		power-domains = <&pd_dma_lpuart4>;
++		status = "disabled";
++	};
++
+ 	usdhc1: usdhc@5b010000 {
+ 		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+ 		interrupt-parent = <&gic>;
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0015-arm-dts-imx8qm-add-support-for-i2c0-i2c1-i2c2-i2c3-a.patch b/recipes-bsp/u-boot-mainline/files/0015-arm-dts-imx8qm-add-support-for-i2c0-i2c1-i2c2-i2c3-a.patch
new file mode 100644
index 0000000..2e92485
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0015-arm-dts-imx8qm-add-support-for-i2c0-i2c1-i2c2-i2c3-a.patch
@@ -0,0 +1,110 @@
+From c3717078539984c45329200a1b8fed171d651f33 Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Date: Mon, 29 Apr 2019 18:03:46 +0200
+Subject: [PATCH 15/19] arm: dts: imx8qm: add support for i2c0, i2c1, i2c2,
+ i2c3 and i2c4
+
+Add support for i2c0, i2c1, i2c2, i2c3 and i2c4.
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
+---
+ arch/arm/dts/fsl-imx8qm.dtsi | 75 ++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 75 insertions(+)
+
+diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
+index db01959990..af060db3a1 100644
+--- a/arch/arm/dts/fsl-imx8qm.dtsi
++++ b/arch/arm/dts/fsl-imx8qm.dtsi
+@@ -29,6 +29,11 @@
+ 		mmc0 = &usdhc1;
+ 		mmc1 = &usdhc2;
+ 		mmc2 = &usdhc3;
++		i2c0 = &i2c0;
++		i2c1 = &i2c1;
++		i2c2 = &i2c2;
++		i2c3 = &i2c3;
++		i2c4 = &i2c4;
+ 	};
+ 
+ 	memory@80000000 {
+@@ -224,6 +229,76 @@
+ 		};
+ 	};
+ 
++	i2c0: i2c@5a800000 {
++		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
++		reg = <0x0 0x5a800000 0x0 0x4000>;
++		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-parent = <&gic>;
++		clocks = <&clk IMX8QM_I2C0_CLK>,
++			 <&clk IMX8QM_I2C0_IPG_CLK>;
++		clock-names = "per", "ipg";
++		assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
++		assigned-clock-rates = <24000000>;
++		power-domains = <&pd_dma_lpi2c0>;
++		status = "disabled";
++	};
++
++	i2c1: i2c@5a810000 {
++		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
++		reg = <0x0 0x5a810000 0x0 0x4000>;
++		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-parent = <&gic>;
++		clocks = <&clk IMX8QM_I2C1_CLK>,
++			 <&clk IMX8QM_I2C1_IPG_CLK>;
++		clock-names = "per", "ipg";
++		assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
++		assigned-clock-rates = <24000000>;
++		power-domains = <&pd_dma_lpi2c1>;
++		status = "disabled";
++	};
++
++	i2c2: i2c@5a820000 {
++		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
++		reg = <0x0 0x5a820000 0x0 0x4000>;
++		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-parent = <&gic>;
++		clocks = <&clk IMX8QM_I2C2_CLK>,
++			 <&clk IMX8QM_I2C2_IPG_CLK>;
++		clock-names = "per", "ipg";
++		assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
++		assigned-clock-rates = <24000000>;
++		power-domains = <&pd_dma_lpi2c2>;
++		status = "disabled";
++	};
++
++	i2c3: i2c@5a830000 {
++		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
++		reg = <0x0 0x5a830000 0x0 0x4000>;
++		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-parent = <&gic>;
++		clocks = <&clk IMX8QM_I2C3_CLK>,
++			 <&clk IMX8QM_I2C3_IPG_CLK>;
++		clock-names = "per", "ipg";
++		assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
++		assigned-clock-rates = <24000000>;
++		power-domains = <&pd_dma_lpi2c3>;
++		status = "disabled";
++	};
++
++	i2c4: i2c@5a840000 {
++		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
++		reg = <0x0 0x5a840000 0x0 0x4000>;
++		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-parent = <&gic>;
++		clocks = <&clk IMX8QM_I2C4_CLK>,
++			 <&clk IMX8QM_I2C4_IPG_CLK>;
++		clock-names = "per", "ipg";
++		assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
++		assigned-clock-rates = <24000000>;
++		power-domains = <&pd_dma_lpi2c4>;
++		status = "disabled";
++	};
++
+ 	gpio0: gpio@5d080000 {
+ 		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+ 		reg = <0x0 0x5d080000 0x0 0x10000>;
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch b/recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch
new file mode 100644
index 0000000..5ef6305
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch
@@ -0,0 +1,65 @@
+From 025a98d87d9e2274a438d3878428c04abf4fc717 Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel@ziswiler.com>
+Date: Mon, 29 Apr 2019 17:57:24 +0200
+Subject: [PATCH 16/19] clk: imx8qm: fix usdhc2 clocks
+
+Trying to bring up uSDHC2 the following error message was observed:
+
+MMC:   imx8_clk_set_rate(Invalid clk ID #60)
+imx8_clk_set_rate(Invalid clk ID #60)
+usdhc@5b030000 - probe failed: -22
+
+This commit fixes this by properly setting resp. clocks.
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
+---
+ drivers/clk/imx/clk-imx8qm.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c
+index 6b5561e178..a6b09d2109 100644
+--- a/drivers/clk/imx/clk-imx8qm.c
++++ b/drivers/clk/imx/clk-imx8qm.c
+@@ -80,6 +80,12 @@ ulong imx8_clk_get_rate(struct clk *clk)
+ 		resource = SC_R_SDHC_1;
+ 		pm_clk = SC_PM_CLK_PER;
+ 		break;
++	case IMX8QM_SDHC2_IPG_CLK:
++	case IMX8QM_SDHC2_CLK:
++	case IMX8QM_SDHC2_DIV:
++		resource = SC_R_SDHC_2;
++		pm_clk = SC_PM_CLK_PER;
++		break;
+ 	case IMX8QM_UART0_IPG_CLK:
+ 	case IMX8QM_UART0_CLK:
+ 		resource = SC_R_UART_0;
+@@ -185,6 +191,12 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+ 		resource = SC_R_SDHC_1;
+ 		pm_clk = SC_PM_CLK_PER;
+ 		break;
++	case IMX8QM_SDHC2_IPG_CLK:
++	case IMX8QM_SDHC2_CLK:
++	case IMX8QM_SDHC2_DIV:
++		resource = SC_R_SDHC_2;
++		pm_clk = SC_PM_CLK_PER;
++		break;
+ 	case IMX8QM_ENET0_IPG_CLK:
+ 	case IMX8QM_ENET0_AHB_CLK:
+ 	case IMX8QM_ENET0_REF_DIV:
+@@ -273,6 +285,12 @@ int __imx8_clk_enable(struct clk *clk, bool enable)
+ 		resource = SC_R_SDHC_1;
+ 		pm_clk = SC_PM_CLK_PER;
+ 		break;
++	case IMX8QM_SDHC2_IPG_CLK:
++	case IMX8QM_SDHC2_CLK:
++	case IMX8QM_SDHC2_DIV:
++		resource = SC_R_SDHC_2;
++		pm_clk = SC_PM_CLK_PER;
++		break;
+ 	case IMX8QM_ENET0_IPG_CLK:
+ 	case IMX8QM_ENET0_AHB_CLK:
+ 	case IMX8QM_ENET0_REF_DIV:
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0017-imx8qm-fix-cpu-frequency-reporting.patch b/recipes-bsp/u-boot-mainline/files/0017-imx8qm-fix-cpu-frequency-reporting.patch
new file mode 100644
index 0000000..088c2d2
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0017-imx8qm-fix-cpu-frequency-reporting.patch
@@ -0,0 +1,40 @@
+From c54d289c92c963d449ad91fd683e13180b88c3b1 Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel@ziswiler.com>
+Date: Tue, 30 Apr 2019 09:50:50 +0200
+Subject: [PATCH 17/19] imx8qm: fix cpu frequency reporting
+
+CPU frequency reporting failed with the following error message being
+printed:
+
+sc_pm_get_clock_rate: resource:507 clk:2: res:3
+Could not read CPU frequency: -22
+CPU:   NXP i.MX8QM RevB A53 at 0 MHz
+
+Fix this by differentiating between the A35 as found on the i.MX 8QXP
+and the A53 as found on the i.MX 8QM SoCs.
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
+---
+ arch/arm/mach-imx/imx8/cpu.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
+index 12716e7e9e..12596c6387 100644
+--- a/arch/arm/mach-imx/imx8/cpu.c
++++ b/arch/arm/mach-imx/imx8/cpu.c
+@@ -654,8 +654,10 @@ static ulong imx8_get_cpu_rate(void)
+ {
+ 	ulong rate;
+ 	int ret;
++	int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ?
++		   SC_R_A53 : SC_R_A72;
+ 
+-	ret = sc_pm_get_clock_rate(-1, SC_R_A35, SC_PM_CLK_CPU,
++	ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
+ 				   (sc_pm_clock_rate_t *)&rate);
+ 	if (ret) {
+ 		printf("Could not read CPU frequency: %d\n", ret);
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0018-imx8-fuse-fix-fuse-driver.patch b/recipes-bsp/u-boot-mainline/files/0018-imx8-fuse-fix-fuse-driver.patch
new file mode 100644
index 0000000..9177373
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0018-imx8-fuse-fix-fuse-driver.patch
@@ -0,0 +1,35 @@
+From 07345149dd07e6b9adec1fa8358663ec8202242b Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel@ziswiler.com>
+Date: Tue, 30 Apr 2019 10:08:55 +0200
+Subject: [PATCH 18/19] imx8: fuse: fix fuse driver
+
+This fixes the i.MX 8 fuse driver to actually build for i.MX 8QM as
+well.
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
+---
+ drivers/misc/imx8/fuse.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c
+index 29d2256a22..2f2fad2c17 100644
+--- a/drivers/misc/imx8/fuse.c
++++ b/drivers/misc/imx8/fuse.c
+@@ -15,13 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
+ #define FSL_ECC_WORD_START_1	 0x10
+ #define FSL_ECC_WORD_END_1	 0x10F
+ 
+-#ifdef CONFIG_IMX8QXP
+ #define FSL_ECC_WORD_START_2	 0x220
+ #define FSL_ECC_WORD_END_2	 0x31F
+ 
+ #define FSL_QXP_FUSE_GAP_START	 0x110
+ #define FSL_QXP_FUSE_GAP_END	 0x21F
+-#endif
+ 
+ #define FSL_SIP_OTP_READ             0xc200000A
+ #define FSL_SIP_OTP_WRITE            0xc200000B
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/0019-board-toradex-add-apalis-imx8qm-4gb-wb-it-v1.0b-modu.patch b/recipes-bsp/u-boot-mainline/files/0019-board-toradex-add-apalis-imx8qm-4gb-wb-it-v1.0b-modu.patch
new file mode 100644
index 0000000..4102993
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/0019-board-toradex-add-apalis-imx8qm-4gb-wb-it-v1.0b-modu.patch
@@ -0,0 +1,1434 @@
+From 6c5418e7567c367c76c7657726cdea85e497a470 Mon Sep 17 00:00:00 2001
+From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Date: Mon, 29 Apr 2019 01:24:25 +0200
+Subject: [PATCH 19/19] board: toradex: add apalis imx8qm 4gb wb it v1.0b
+ module support
+
+This commit adds initial support for the Toradex Apalis iMX8QM 4GB WB IT
+V1.0B module. Unlike the V1.0A early access samples exclusively booting
+from SD card, they are now strapped to boot from eFuses which are
+factory fused to properly boot from their on-module eMMC. U-Boot
+supports either booting from the on-module eMMC or may be used for
+recovery purpose using the universal update utility (uuu) aka mfgtools
+3.0.
+
+Functionality wise the following is known to be working:
+- eMMC, 8-bit and 4-bit MMC/SD card slots
+- Gigabit Ethernet
+- GPIOs
+- I2C
+
+Unfortunately, there is no USB functionality for the i.MX 8QM as of yet.
+
+Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
+
+Series-to: u-boot@lists.denx.de
+
+Series-version: 2
+
+Series-changes: 2
+- Use firmware-imx-8.0 matching NXP's sumo-4.14.78-1.0.0_ga BSP as
+  suggested by Max.
+- Drop Qualcomm (formwerly Atheros) AR8031 specific board_phy_config()
+  stuff not applicable to the Micrel PHY we are using as suggested by Max.
+- Drop CONFIG_FEC_XCV_TYPE in favour of device tree configuration therof
+  as suggested by Max.
+
+Cover-letter:
+apalis imx8qm 4gb wb it v1.0b module support
+
+This series adds support for more lpuart instances, support for i2c0,
+i2c1, i2c2, i2c3, i2c4, fixes support for uSDHC2, fixes CPU frequency
+reporting, fixes fuse driver and last but not least introduces support
+for the Toradex Apalis iMX8QM 4GB WB IT V1.0B module.
+
+This series is available together with the last few clean-up patches
+and the Colibri iMX8QXP patch series on our git server [1] as well.
+
+[1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next
+END
+---
+ arch/arm/dts/Makefile                       |   1 +
+ arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi  | 128 ++++++
+ arch/arm/dts/fsl-imx8qm-apalis.dts          | 615 ++++++++++++++++++++++++++++
+ arch/arm/mach-imx/imx8/Kconfig              |   6 +
+ board/toradex/apalis-imx8qm/Kconfig         |  30 ++
+ board/toradex/apalis-imx8qm/MAINTAINERS     |   9 +
+ board/toradex/apalis-imx8qm/Makefile        |   6 +
+ board/toradex/apalis-imx8qm/README          |  66 +++
+ board/toradex/apalis-imx8qm/apalis-imx8qm.c | 149 +++++++
+ board/toradex/apalis-imx8qm/imximage.cfg    |  24 ++
+ configs/apalis-imx8qm_defconfig             |  56 +++
+ include/configs/apalis-imx8qm.h             | 177 ++++++++
+ 12 files changed, 1267 insertions(+)
+ create mode 100644 arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
+ create mode 100644 arch/arm/dts/fsl-imx8qm-apalis.dts
+ create mode 100644 board/toradex/apalis-imx8qm/Kconfig
+ create mode 100644 board/toradex/apalis-imx8qm/MAINTAINERS
+ create mode 100644 board/toradex/apalis-imx8qm/Makefile
+ create mode 100644 board/toradex/apalis-imx8qm/README
+ create mode 100644 board/toradex/apalis-imx8qm/apalis-imx8qm.c
+ create mode 100644 board/toradex/apalis-imx8qm/imximage.cfg
+ create mode 100644 configs/apalis-imx8qm_defconfig
+ create mode 100644 include/configs/apalis-imx8qm.h
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 598dc213e3..2c1cf3122a 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -576,6 +576,7 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
+ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+ 
+ dtb-$(CONFIG_ARCH_IMX8) += \
++	fsl-imx8qm-apalis.dtb \
+ 	fsl-imx8qm-mek.dtb \
+ 	fsl-imx8qxp-colibri.dtb \
+ 	fsl-imx8qxp-mek.dtb
+diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
+new file mode 100644
+index 0000000000..7b1a9550e4
+--- /dev/null
++++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
+@@ -0,0 +1,128 @@
++// SPDX-License-Identifier: GPL-2.0+ OR X11
++/*
++ * Copyright 2019 Toradex AG
++ */
++
++&mu {
++	u-boot,dm-spl;
++};
++
++&clk {
++	u-boot,dm-spl;
++};
++
++&iomuxc {
++	u-boot,dm-spl;
++};
++
++&pd_lsio {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio0 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio1 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio2 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio3 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio4 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio5 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio6 {
++	u-boot,dm-spl;
++};
++
++&pd_lsio_gpio7 {
++	u-boot,dm-spl;
++};
++
++&pd_conn {
++	u-boot,dm-spl;
++};
++
++&pd_conn_sdch0 {
++	u-boot,dm-spl;
++};
++
++&pd_conn_sdch1 {
++	u-boot,dm-spl;
++};
++
++&pd_conn_sdch2 {
++	u-boot,dm-spl;
++};
++
++&gpio0 {
++	u-boot,dm-spl;
++};
++
++&gpio1 {
++	u-boot,dm-spl;
++};
++
++&gpio2 {
++	u-boot,dm-spl;
++};
++
++&gpio3 {
++	u-boot,dm-spl;
++};
++
++&gpio4 {
++	u-boot,dm-spl;
++};
++
++&gpio5 {
++	u-boot,dm-spl;
++};
++
++&gpio6 {
++	u-boot,dm-spl;
++};
++
++&gpio7 {
++	u-boot,dm-spl;
++};
++
++&lpuart0 {
++	u-boot,dm-spl;
++};
++
++&lpuart1 {
++	u-boot,dm-spl;
++};
++
++&lpuart2 {
++	u-boot,dm-spl;
++};
++
++&lpuart3 {
++	u-boot,dm-spl;
++};
++
++&usdhc1 {
++	u-boot,dm-spl;
++};
++
++&usdhc2 {
++	u-boot,dm-spl;
++};
++
++&usdhc3 {
++	u-boot,dm-spl;
++};
+diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts
+new file mode 100644
+index 0000000000..9b1f8aa32d
+--- /dev/null
++++ b/arch/arm/dts/fsl-imx8qm-apalis.dts
+@@ -0,0 +1,615 @@
++// SPDX-License-Identifier: GPL-2.0+ OR X11
++/*
++ * Copyright 2017-2019 Toradex
++ */
++
++/dts-v1/;
++
++/* First 128KB is for PSCI ATF. */
++/memreserve/ 0x80000000 0x00020000;
++
++#include "fsl-imx8qm.dtsi"
++#include "fsl-imx8qm-apalis-u-boot.dtsi"
++
++/ {
++	model = "Toradex Apalis iMX8QM";
++	compatible = "toradex,apalis-imx8qm", "fsl,imx8qm";
++
++	chosen {
++		bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200";
++		stdout-path = &lpuart1;
++	};
++};
++
++&iomuxc {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
++		    <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
++		    <&pinctrl_gpio12>, <&pinctrl_gpio34>, <&pinctrl_gpio56>,
++		    <&pinctrl_gpio7>, <&pinctrl_gpio8>, <&pinctrl_gpio_bkl_on>,
++		    <&pinctrl_gpio_keys>, <&pinctrl_gpio_pwm0>,
++		    <&pinctrl_gpio_pwm1>, <&pinctrl_gpio_pwm2>,
++		    <&pinctrl_gpio_pwm3>, <&pinctrl_gpio_pwm_bkl>,
++		    <&pinctrl_gpio_usbh_en>, <&pinctrl_gpio_usbh_oc_n>,
++		    <&pinctrl_gpio_usbo1_en>, <&pinctrl_gpio_usbo1_oc_n>,
++		    <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>,
++		    <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>,
++		    <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>,
++		    <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,
++		    <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>;
++
++	apalis-imx8qm {
++		pinctrl_gpio12: gpio12grp {
++			fsl,pins = <
++				/* Apalis GPIO1 */
++				SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08		0x06000021
++				/* Apalis GPIO2 */
++				SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09		0x06000021
++			>;
++		};
++
++		pinctrl_gpio34: gpio34grp {
++			fsl,pins = <
++				/* Apalis GPIO3 */
++				SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12		0x06000021
++				/* Apalis GPIO4 */
++				SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13		0x06000021
++			>;
++		};
++
++		pinctrl_gpio56: gpio56grp {
++			fsl,pins = <
++				/* Apalis GPIO5 */
++				SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01		0x06000021
++				/* Apalis GPIO6 */
++				SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02		0x06000021
++			>;
++		};
++
++		pinctrl_gpio7: gpio7 {
++			fsl,pins = <
++				/* Apalis GPIO7 */
++				SC_P_MLB_SIG_LSIO_GPIO3_IO26			0x00000021
++			>;
++		};
++
++		pinctrl_gpio8: gpio8 {
++			fsl,pins = <
++				/* Apalis GPIO8 */
++				SC_P_MLB_DATA_LSIO_GPIO3_IO28			0x00000021
++			>;
++		};
++
++		pinctrl_gpio_keys: gpio-keys {
++			fsl,pins = <
++				/* Apalis WAKE1_MICO */
++				SC_P_SPI3_CS0_LSIO_GPIO2_IO20		0x06000021
++			>;
++		};
++
++		pinctrl_fec1: fec1grp {
++			fsl,pins = <
++				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD	0x000014a0 /* Use pads in 3.3V mode */
++				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
++				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
++				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
++				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
++				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
++				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
++				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
++				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
++				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
++				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
++				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
++				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
++				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
++				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
++				SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M	0x06000020
++				/* ETH_RESET# */
++				SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11		0x06000020
++			>;
++		};
++
++		pinctrl_gpio_bkl_on: gpio-bkl-on {
++			fsl,pins = <
++				/* Apalis BKL_ON */
++				SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04	0x00000021
++			>;
++		};
++
++		/* Apalis I2C2 (DDC) */
++		pinctrl_lpi2c0: lpi2c0grp {
++			fsl,pins = <
++				SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0x04000022
++				SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0x04000022
++			>;
++		};
++
++		pinctrl_cam1_gpios: cam1gpiosgrp {
++			fsl,pins = <
++				/* Apalis CAM1_D7 */
++				SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20	0x00000021
++				/* Apalis CAM1_D6 */
++				SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21	0x00000021
++				/* Apalis CAM1_D5 */
++				SC_P_ESAI0_TX0_LSIO_GPIO2_IO26		0x00000021
++				/* Apalis CAM1_D4 */
++				SC_P_ESAI0_TX1_LSIO_GPIO2_IO27		0x00000021
++				/* Apalis CAM1_D3 */
++				SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28	0x00000021
++				/* Apalis CAM1_D2 */
++				SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29	0x00000021
++				/* Apalis CAM1_D1 */
++				SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30	0x00000021
++				/* Apalis CAM1_D0 */
++				SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31	0x00000021
++				/* Apalis CAM1_PCLK */
++				SC_P_MCLK_IN0_LSIO_GPIO3_IO00		0x00000021
++				/* Apalis CAM1_MCLK */
++				SC_P_SPI3_SDO_LSIO_GPIO2_IO18		0x00000021
++				/* Apalis CAM1_VSYNC */
++				SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24		0x00000021
++				/* Apalis CAM1_HSYNC */
++				SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25		0x00000021
++			>;
++		};
++
++		pinctrl_dap1_gpios: dap1gpiosgrp {
++			fsl,pins = <
++				/* Apalis DAP1_MCLK */
++				SC_P_SPI3_SDI_LSIO_GPIO2_IO19			0x00000021
++				/* Apalis DAP1_D_OUT */
++				SC_P_SAI1_RXC_LSIO_GPIO3_IO12			0x00000021
++				/* Apalis DAP1_RESET */
++				SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07			0x00000021
++				/* Apalis DAP1_BIT_CLK */
++				SC_P_SPI0_CS1_LSIO_GPIO3_IO06			0x00000021
++				/* Apalis DAP1_D_IN */
++				SC_P_SAI1_RXFS_LSIO_GPIO3_IO14			0x00000021
++				/* Apalis DAP1_SYNC */
++				SC_P_SPI2_CS1_LSIO_GPIO3_IO11			0x00000021
++				/* Wi-Fi_I2S_EN# */
++				SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13		0x00000021
++			>;
++		};
++
++		pinctrl_esai0_gpios: esai0gpiosgrp {
++			fsl,pins = <
++				/* Apalis LCD1_G1 */
++				SC_P_ESAI0_FSR_LSIO_GPIO2_IO22			0x00000021
++				/* Apalis LCD1_G2 */
++				SC_P_ESAI0_FST_LSIO_GPIO2_IO23			0x00000021
++			>;
++		};
++
++		pinctrl_fec2_gpios: fec2gpiosgrp {
++			fsl,pins = <
++				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD	0x000014a0
++				/* Apalis LCD1_R1 */
++				SC_P_ENET1_MDC_LSIO_GPIO4_IO18			0x00000021
++				/* Apalis LCD1_R0 */
++				SC_P_ENET1_MDIO_LSIO_GPIO4_IO17			0x00000021
++				/* Apalis LCD1_G0 */
++				SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16	0x00000021
++				/* Apalis LCD1_R7 */
++				SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17		0x00000021
++				/* Apalis LCD1_DE */
++				SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18		0x00000021
++				/* Apalis LCD1_HSYNC */
++				SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19		0x00000021
++				/* Apalis LCD1_VSYNC */
++				SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20		0x00000021
++				/* Apalis LCD1_PCLK */
++				SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21		0x00000021
++				/* Apalis LCD1_R6 */
++				SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11		0x00000021
++				/* Apalis LCD1_R5 */
++				SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10		0x00000021
++				/* Apalis LCD1_R4 */
++				SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12		0x00000021
++				/* Apalis LCD1_R3 */
++				SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13		0x00000021
++				/* Apalis LCD1_R2 */
++				SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14		0x00000021
++			>;
++		};
++
++		pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpio {
++			fsl,pins = <
++				/* Apalis TS_2 */
++				SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06		0x00000021
++			>;
++		};
++
++		pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
++			fsl,pins = <
++				/* Apalis LCD1_G6 */
++				SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12		0x00000021
++				/* Apalis LCD1_G7 */
++				SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x00000021
++			>;
++		};
++
++		pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
++			fsl,pins = <
++				/* Apalis TS_4 */
++				SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22		0x00000021
++			>;
++		};
++
++		pinctrl_mlb_gpios: mlbgpiosgrp {
++			fsl,pins = <
++				/* Apalis TS_1 */
++				SC_P_MLB_CLK_LSIO_GPIO3_IO27			0x00000021
++			>;
++		};
++
++		pinctrl_qspi1a_gpios: qspi1agpiosgrp {
++			fsl,pins = <
++				/* Apalis LCD1_B0 */
++				SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26		0x00000021
++				/* Apalis LCD1_B1 */
++				SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25		0x00000021
++				/* Apalis LCD1_B2 */
++				SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24		0x00000021
++				/* Apalis LCD1_B3 */
++				SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23		0x00000021
++				/* Apalis LCD1_B5 */
++				SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22			0x00000021
++				/* Apalis LCD1_B7 */
++				SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21		0x00000021
++				/* Apalis LCD1_B4 */
++				SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19		0x00000021
++				/* Apalis LCD1_B6 */
++				SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20		0x00000021
++			>;
++		};
++
++		pinctrl_sim0_gpios: sim0gpiosgrp {
++			fsl,pins = <
++				/* Apalis LCD1_G5 */
++				SC_P_SIM0_CLK_LSIO_GPIO0_IO00			0x00000021
++				/* Apalis LCD1_G3 */
++				SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05		0x00000021
++				/* Apalis TS_5 */
++				SC_P_SIM0_IO_LSIO_GPIO0_IO02			0x00000021
++				/* Apalis LCD1_G4 */
++				SC_P_SIM0_RST_LSIO_GPIO0_IO01			0x00000021
++			>;
++		};
++
++		pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
++			fsl,pins = <
++				/* Apalis TS_6 */
++				SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23		0x00000021
++			>;
++		};
++
++		pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en {
++			fsl,pins = <
++				/* Apalis TS_3 */
++				SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07		0x00000021
++			>;
++		};
++
++		/* On-module I2C */
++		pinctrl_lpi2c1: lpi2c1grp {
++			fsl,pins = <
++				SC_P_GPT0_CLK_DMA_I2C1_SCL		0x04000020
++				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0x04000020
++			>;
++		};
++
++		/* Apalis I2C1 */
++		pinctrl_lpi2c2: lpi2c2grp {
++			fsl,pins = <
++				SC_P_GPT1_CLK_DMA_I2C2_SCL		0x04000020
++				SC_P_GPT1_CAPTURE_DMA_I2C2_SDA		0x04000020
++			>;
++		};
++
++		/* Apalis I2C3 (CAM) */
++		pinctrl_lpi2c3: lpi2c3grp {
++			fsl,pins = <
++				SC_P_SIM0_PD_DMA_I2C3_SCL		0x04000020
++				SC_P_SIM0_POWER_EN_DMA_I2C3_SDA		0x04000020
++			>;
++		};
++
++		/* Apalis UART3 */
++		pinctrl_lpuart0: lpuart0grp {
++			fsl,pins = <
++				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
++				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
++			>;
++		};
++
++		/* Apalis UART1 */
++		pinctrl_lpuart1: lpuart1grp {
++			fsl,pins = <
++				SC_P_UART1_RX_DMA_UART1_RX		0x06000020
++				SC_P_UART1_TX_DMA_UART1_TX		0x06000020
++				SC_P_UART1_CTS_B_DMA_UART1_CTS_B	0x06000020
++				SC_P_UART1_RTS_B_DMA_UART1_RTS_B	0x06000020
++			>;
++		};
++
++		pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
++			fsl,pins = <
++				/* Apalis UART1_DTR */
++				SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06	0x00000021
++				/* Apalis UART1_DSR */
++				SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07	0x00000021
++				/* Apalis UART1_DCD */
++				SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10	0x00000021
++				/* Apalis UART1_RI */
++				SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11	0x00000021
++			>;
++		};
++
++		/* Apalis UART4 */
++		pinctrl_lpuart2: lpuart2grp {
++			fsl,pins = <
++				SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX	0x06000020
++				SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX	0x06000020
++			>;
++		};
++
++		/* Apalis UART2 */
++		pinctrl_lpuart3: lpuart3grp {
++			fsl,pins = <
++				SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX	0x06000020
++				SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX	0x06000020
++				SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B	0x06000020
++				SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B	0x06000020
++			>;
++		};
++
++		/* Apalis PWM3 */
++		pinctrl_gpio_pwm0: gpiopwm0grp {
++			fsl,pins = <
++				SC_P_UART0_RTS_B_LSIO_GPIO0_IO22	0x00000021
++			>;
++		};
++
++		/* Apalis PWM4 */
++		pinctrl_gpio_pwm1: gpiopwm1grp {
++			fsl,pins = <
++				SC_P_UART0_CTS_B_LSIO_GPIO0_IO23	0x00000021
++			>;
++		};
++
++		/* Apalis PWM1 */
++		pinctrl_gpio_pwm2: gpiopwm2grp {
++			fsl,pins = <
++				SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19	0x00000021
++			>;
++		};
++
++		/* Apalis PWM2 */
++		pinctrl_gpio_pwm3: gpiopwm3grp {
++			fsl,pins = <
++				SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16	0x00000021
++			>;
++		};
++
++		/* Apalis BKL1_PWM */
++		pinctrl_gpio_pwm_bkl: gpiopwmbklgrp {
++			fsl,pins = <
++				SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00	0x00000021
++			>;
++		};
++
++		/* Apalis USBH_EN */
++		pinctrl_gpio_usbh_en: gpiousbhen {
++			fsl,pins = <
++				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x06000060
++			>;
++		};
++
++		/* Apalis USBH_OC# */
++		pinctrl_gpio_usbh_oc_n: gpiousbhocn {
++			fsl,pins = <
++				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x06000060
++			>;
++		};
++
++		/* Apalis USBO1_EN */
++		pinctrl_gpio_usbo1_en: gpiousbo1en {
++			fsl,pins = <
++				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000060
++			>;
++		};
++
++		/* Apalis USBO1_OC# */
++		pinctrl_gpio_usbo1_oc_n: gpiousbo1ocn {
++			fsl,pins = <
++				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x06000060
++			>;
++		};
++
++		pinctrl_usdhc1: usdhc1grp {
++			fsl,pins = <
++				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
++				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
++				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
++				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
++				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
++				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
++				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
++				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
++				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
++				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
++				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
++				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
++			>;
++		};
++
++		pinctrl_sata1_act: sata1actgrp {
++			fsl,pins = <
++				/* Apalis SATA1_ACT# */
++				SC_P_ESAI1_TX0_LSIO_GPIO2_IO08		0x00000021
++			>;
++		};
++
++		pinctrl_mmc1_cd: mmc1cdgrp {
++			fsl,pins = <
++				/* Apalis MMC1_CD# */
++				SC_P_ESAI1_TX1_LSIO_GPIO2_IO09		0x00000021
++			>;
++		};
++
++		pinctrl_usdhc2: usdhc2grp {
++			fsl,pins = <
++				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
++				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
++				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
++				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
++				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
++				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
++				SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4	0x00000021
++				SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5	0x00000021
++				SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6	0x00000021
++				SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7	0x00000021
++				/* On-module PMIC use */
++				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
++			>;
++		};
++
++		pinctrl_sd1_cd: sd1cdgrp {
++			fsl,pins = <
++				/* Apalis SD1_CD# */
++				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12	0x00000021
++			>;
++		};
++
++		pinctrl_usdhc3: usdhc3grp {
++			fsl,pins = <
++				SC_P_USDHC2_CLK_CONN_USDHC2_CLK		0x06000041
++				SC_P_USDHC2_CMD_CONN_USDHC2_CMD		0x00000021
++				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0	0x00000021
++				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1	0x00000021
++				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2	0x00000021
++				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3	0x00000021
++				/* On-module PMIC use */
++				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000021
++			>;
++		};
++	};
++};
++
++&fec1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_fec1>;
++	fsl,magic-packet;
++	phy-handle = <&ethphy0>;
++	phy-mode = "rgmii";
++	phy-reset-duration = <10>;
++	phy-reset-gpios = <&gpio1 11 1>;
++	status = "okay";
++
++	mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		ethphy0: ethernet-phy@7 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			reg = <7>;
++		};
++	};
++};
++
++/* Apalis I2C2 (DDC) */
++&i2c0 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lpi2c0>;
++	clock-frequency = <100000>;
++	status = "okay";
++};
++
++/* On-module I2C */
++&i2c1 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	clock-frequency = <100000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lpi2c1>;
++	status = "okay";
++};
++
++/* Apalis I2C1 */
++&i2c2 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	clock-frequency = <100000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lpi2c2>;
++	status = "okay";
++};
++
++/* Apalis I2C3 (CAM) */
++&i2c3 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	clock-frequency = <100000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lpi2c3>;
++	status = "okay";
++};
++
++/* Apalis UART3 */
++&lpuart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lpuart0>;
++	status = "okay";
++};
++
++/* Apalis UART1 */
++&lpuart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lpuart1>;
++	status = "okay";
++};
++
++/* Apalis UART4 */
++&lpuart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lpuart2>;
++	status = "okay";
++};
++
++/* Apalis UART2 */
++&lpuart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lpuart3>;
++	status = "okay";
++};
++
++/* eMMC */
++&usdhc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_usdhc1>;
++	bus-width = <8>;
++	non-removable;
++	status = "okay";
++};
++
++/* Apalis MMC1 */
++&usdhc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
++	bus-width = <8>;
++	cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
++	status = "okay";
++};
++
++/* Apalis SD1 */
++&usdhc3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
++	bus-width = <4>;
++	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
++	status = "okay";
++};
+diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
+index 90223aaefc..c87f77fee6 100644
+--- a/arch/arm/mach-imx/imx8/Kconfig
++++ b/arch/arm/mach-imx/imx8/Kconfig
+@@ -27,6 +27,11 @@ choice
+ 	prompt "i.MX8 board select"
+ 	optional
+ 
++config TARGET_APALIS_IMX8QM
++	bool "Support Apalis iMX8QM module"
++	select BOARD_LATE_INIT
++	select IMX8QM
++
+ config TARGET_COLIBRI_IMX8QXP
+ 	bool "Support Colibri iMX8QXP module"
+ 	select BOARD_LATE_INIT
+@@ -46,6 +51,7 @@ endchoice
+ 
+ source "board/freescale/imx8qm_mek/Kconfig"
+ source "board/freescale/imx8qxp_mek/Kconfig"
++source "board/toradex/apalis-imx8qm/Kconfig"
+ source "board/toradex/colibri-imx8qxp/Kconfig"
+ 
+ endif
+diff --git a/board/toradex/apalis-imx8qm/Kconfig b/board/toradex/apalis-imx8qm/Kconfig
+new file mode 100644
+index 0000000000..38b64cd6e6
+--- /dev/null
++++ b/board/toradex/apalis-imx8qm/Kconfig
+@@ -0,0 +1,30 @@
++if TARGET_APALIS_IMX8QM
++
++config SYS_BOARD
++	default "apalis-imx8qm"
++
++config SYS_VENDOR
++	default "toradex"
++
++config SYS_CONFIG_NAME
++	default "apalis-imx8qm"
++
++config TDX_CFG_BLOCK
++	default y
++
++config TDX_HAVE_MMC
++	default y
++
++config TDX_CFG_BLOCK_DEV
++	default "0"
++
++config TDX_CFG_BLOCK_PART
++	default "1"
++
++# Toradex config block in eMMC, at the end of 1st "boot sector"
++config TDX_CFG_BLOCK_OFFSET
++	default "-512"
++
++source "board/toradex/common/Kconfig"
++
++endif
+diff --git a/board/toradex/apalis-imx8qm/MAINTAINERS b/board/toradex/apalis-imx8qm/MAINTAINERS
+new file mode 100644
+index 0000000000..f2a61236b8
+--- /dev/null
++++ b/board/toradex/apalis-imx8qm/MAINTAINERS
+@@ -0,0 +1,9 @@
++Apalis iMX8QM
++M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
++W:	http://developer.toradex.com/software/linux/linux-software
++S:	Maintained
++F:	arch/arm/dts/fsl-imx8qm-apalis.dts
++F:	arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
++F:	board/toradex/apalis-imx8qm/
++F:	configs/apalis-imx8qm_defconfig
++F:	include/configs/apalis-imx8qm.h
+diff --git a/board/toradex/apalis-imx8qm/Makefile b/board/toradex/apalis-imx8qm/Makefile
+new file mode 100644
+index 0000000000..d606a866b4
+--- /dev/null
++++ b/board/toradex/apalis-imx8qm/Makefile
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0+
++#
++# Copyright 2019 Toradex
++#
++
++obj-y += apalis-imx8qm.o
+diff --git a/board/toradex/apalis-imx8qm/README b/board/toradex/apalis-imx8qm/README
+new file mode 100644
+index 0000000000..e6e3dcb367
+--- /dev/null
++++ b/board/toradex/apalis-imx8qm/README
+@@ -0,0 +1,66 @@
++U-Boot for the Toradex Apalis iMX8QM V1.0B Module
++
++Quick Start
++===========
++
++- Build the ARM trusted firmware binary
++- Get scfw_tcm.bin and ahab-container.img
++- Build U-Boot
++- Load U-Boot binary using uuu
++- Flash U-Boot binary into the eMMC
++- Boot
++
++Get and Build the ARM Trusted Firmware
++======================================
++
++$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
++$ cd imx-atf/
++$ make PLAT=imx8qm bl31
++
++Get scfw_tcm.bin and ahab-container.img
++=======================================
++
++$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true
++$ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin
++$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
++$ chmod +x firmware-imx-8.0.bin
++$ ./firmware-imx-8.0.bin
++
++Copy the following binaries to the U-Boot folder:
++
++$ cp imx-atf/build/imx8qm/release/bl31.bin .
++$ cp u-boot/u-boot.bin .
++
++Copy the following firmware to the U-Boot folder:
++
++$ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
++
++Build U-Boot
++============
++
++$ make apalis-imx8qm_defconfig
++$ make u-boot-dtb.imx
++
++Load the U-Boot Binary Using UUU
++================================
++
++Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
++
++https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
++
++Put the module into USB recovery aka serial downloader mode, connect USB device
++to your host and execute uuu:
++
++sudo ./uuu u-boot/u-boot-dtb.imx
++
++Flash the U-Boot Binary into the eMMC
++=====================================
++
++Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
++
++load mmc 1:1 $loadaddr u-boot-dtb.imx
++setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
++mmc dev 0 1
++mmc write ${loadaddr} 0x0 ${blkcnt}
++
++Boot
+diff --git a/board/toradex/apalis-imx8qm/apalis-imx8qm.c b/board/toradex/apalis-imx8qm/apalis-imx8qm.c
+new file mode 100644
+index 0000000000..f516e546a8
+--- /dev/null
++++ b/board/toradex/apalis-imx8qm/apalis-imx8qm.c
+@@ -0,0 +1,149 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2019 Toradex
++ */
++
++#include <common.h>
++
++#include <asm/arch/clock.h>
++#include <asm/arch/imx8-pins.h>
++#include <asm/arch/iomux.h>
++#include <asm/arch/sci/sci.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/gpio.h>
++#include <asm/io.h>
++#include <environment.h>
++#include <errno.h>
++#include <linux/libfdt.h>
++
++#include "../common/tdx-cfg-block.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
++			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
++			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
++			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
++
++static iomux_cfg_t uart1_pads[] = {
++	SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
++	SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
++};
++
++static void setup_iomux_uart(void)
++{
++	imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
++}
++
++int board_early_init_f(void)
++{
++	sc_pm_clock_rate_t rate;
++	sc_err_t err = 0;
++
++	/* Power up UART1 */
++	err = sc_pm_set_resource_power_mode(-1, SC_R_UART_1, SC_PM_PW_MODE_ON);
++	if (err != SC_ERR_NONE)
++		return 0;
++
++	/* Set UART3 clock root to 80 MHz */
++	rate = 80000000;
++	err = sc_pm_set_clock_rate(-1, SC_R_UART_1, SC_PM_CLK_PER, &rate);
++	if (err != SC_ERR_NONE)
++		return 0;
++
++	/* Enable UART1 clock root */
++	err = sc_pm_clock_enable(-1, SC_R_UART_1, SC_PM_CLK_PER, true, false);
++	if (err != SC_ERR_NONE)
++		return 0;
++
++	setup_iomux_uart();
++
++	return 0;
++}
++
++#if IS_ENABLED(CONFIG_DM_GPIO)
++static void board_gpio_init(void)
++{
++	/* TODO */
++}
++#else
++static inline void board_gpio_init(void) {}
++#endif
++
++#if IS_ENABLED(CONFIG_FEC_MXC)
++#include <miiphy.h>
++
++int board_phy_config(struct phy_device *phydev)
++{
++	if (phydev->drv->config)
++		phydev->drv->config(phydev);
++
++	return 0;
++}
++#endif
++
++void build_info(void)
++{
++	u32 sc_build = 0, sc_commit = 0;
++
++	/* Get SCFW build and commit id */
++	sc_misc_build_info(-1, &sc_build, &sc_commit);
++	if (!sc_build) {
++		printf("SCFW does not support build info\n");
++		sc_commit = 0; /* Display 0 if build info not supported */
++	}
++	printf("Build: SCFW %x\n", sc_commit);
++}
++
++int checkboard(void)
++{
++	puts("Model: Toradex Apalis iMX8\n");
++
++	build_info();
++	print_bootinfo();
++
++	return 0;
++}
++
++int board_init(void)
++{
++	board_gpio_init();
++
++	return 0;
++}
++
++void detail_board_ddr_info(void)
++{
++	puts("\nDDR    ");
++}
++
++/*
++ * Board specific reset that is system reset.
++ */
++void reset_cpu(ulong addr)
++{
++	/* TODO */
++}
++
++#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
++int ft_board_setup(void *blob, bd_t *bd)
++{
++	return ft_common_board_setup(blob, bd);
++}
++#endif
++
++int board_mmc_get_env_dev(int devno)
++{
++	return devno;
++}
++
++int board_late_init(void)
++{
++#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
++/* TODO move to common */
++	env_set("board_name", "Apalis iMX8QM");
++	env_set("board_rev", "v1.0");
++#endif
++
++	return 0;
++}
+diff --git a/board/toradex/apalis-imx8qm/imximage.cfg b/board/toradex/apalis-imx8qm/imximage.cfg
+new file mode 100644
+index 0000000000..71981f8c55
+--- /dev/null
++++ b/board/toradex/apalis-imx8qm/imximage.cfg
+@@ -0,0 +1,24 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2019 Toradex
++ *
++ * Refer doc/README.imx8image for more details about how-to configure
++ * and create imx8image boot image
++ */
++
++#define __ASSEMBLY__
++
++/* Boot from SD, sector size 0x400 */
++BOOT_FROM EMMC_FASTBOOT 0x400
++/* SoC type IMX8QM */
++SOC_TYPE IMX8QM
++/* Append seco container image */
++APPEND mx8qm-ahab-container.img
++/* Create the 2nd container */
++CONTAINER
++/* Add scfw image with exec attribute */
++IMAGE SCU mx8qm-apalis-scfw-tcm.bin
++/* Add ATF image with exec attribute */
++IMAGE A35 bl31.bin 0x80000000
++/* Add U-Boot image with load attribute */
++DATA A35 u-boot-dtb.bin 0x80020000
+diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig
+new file mode 100644
+index 0000000000..ae62b2d923
+--- /dev/null
++++ b/configs/apalis-imx8qm_defconfig
+@@ -0,0 +1,56 @@
++CONFIG_ARM=y
++CONFIG_ARCH_IMX8=y
++CONFIG_SYS_TEXT_BASE=0x80020000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_TARGET_APALIS_IMX8QM=y
++CONFIG_NR_DRAM_BANKS=3
++CONFIG_DISTRO_DEFAULTS=y
++CONFIG_FIT=y
++CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8qm/imximage.cfg"
++CONFIG_LOG=y
++CONFIG_VERSION_VARIABLE=y
++# CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_BOARD_EARLY_INIT_F=y
++CONFIG_CMD_CPU=y
++# CONFIG_CMD_IMPORTENV is not set
++CONFIG_CMD_MEMTEST=y
++CONFIG_CMD_CLK=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_FUSE=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_UUID=y
++CONFIG_CMD_EXT4_WRITE=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis"
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_CLK_IMX8=y
++CONFIG_CPU=y
++CONFIG_DM_GPIO=y
++CONFIG_MXC_GPIO=y
++CONFIG_DM_I2C=y
++CONFIG_SYS_I2C_IMX_LPI2C=y
++CONFIG_MISC=y
++CONFIG_DM_MMC=y
++CONFIG_PHYLIB=y
++CONFIG_PHY_ADDR_ENABLE=y
++CONFIG_PHY_MICREL=y
++CONFIG_PHY_MICREL_KSZ90X1=y
++CONFIG_DM_ETH=y
++CONFIG_FEC_MXC_SHARE_MDIO=y
++CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
++CONFIG_FEC_MXC=y
++CONFIG_MII=y
++CONFIG_PINCTRL=y
++CONFIG_PINCTRL_IMX8=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_IMX8_POWER_DOMAIN=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_SERIAL=y
++CONFIG_FSL_LPUART=y
++CONFIG_DM_THERMAL=y
++CONFIG_IMX_SCU_THERMAL=y
++# CONFIG_EFI_LOADER is not set
+diff --git a/include/configs/apalis-imx8qm.h b/include/configs/apalis-imx8qm.h
+new file mode 100644
+index 0000000000..f5cba2b1c1
+--- /dev/null
++++ b/include/configs/apalis-imx8qm.h
+@@ -0,0 +1,177 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2019 Toradex
++ */
++
++#ifndef __APALIS_IMX8QM_H
++#define __APALIS_IMX8QM_H
++
++#include <asm/arch/imx-regs.h>
++#include <linux/sizes.h>
++
++#define CONFIG_REMAKE_ELF
++
++#define CONFIG_DISPLAY_BOARDINFO_LATE
++
++#undef CONFIG_CMD_EXPORTENV
++#undef CONFIG_CMD_IMPORTENV
++#undef CONFIG_CMD_IMLS
++
++#undef CONFIG_CMD_CRC32
++#undef CONFIG_BOOTM_NETBSD
++
++#define CONFIG_FSL_ESDHC
++#define CONFIG_FSL_USDHC
++#define CONFIG_SYS_FSL_ESDHC_ADDR	0
++#define USDHC1_BASE_ADDR		0x5B010000
++#define USDHC2_BASE_ADDR		0x5B020000
++#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
++
++#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
++
++/* Networking */
++#define FEC_QUIRK_ENET_MAC
++
++#define CONFIG_IP_DEFRAG
++#define CONFIG_TFTP_BLOCKSIZE		SZ_4K
++#define CONFIG_TFTP_TSIZE
++
++#define CONFIG_IPADDR			192.168.10.2
++#define CONFIG_NETMASK			255.255.255.0
++#define CONFIG_SERVERIP			192.168.10.1
++
++#define MEM_LAYOUT_ENV_SETTINGS \
++	"fdt_addr_r=0x84000000\0" \
++	"kernel_addr_r=0x82000000\0" \
++	"ramdisk_addr_r=0x84100000\0"
++
++#define BOOT_TARGET_DEVICES(func) \
++	func(MMC, mmc, 0) \
++	func(MMC, mmc, 1) \
++	func(MMC, mmc, 2) \
++	func(DHCP, dhcp, na)
++#include <config_distro_bootcmd.h>
++#undef BOOTENV_RUN_NET_USB_START
++#define BOOTENV_RUN_NET_USB_START ""
++
++/* Initial environment variables */
++#define CONFIG_EXTRA_ENV_SETTINGS \
++	BOOTENV \
++	MEM_LAYOUT_ENV_SETTINGS \
++	"boot_fdt=try\0" \
++	"bootscript=echo Running bootscript from mmc ...; source\0" \
++	"console=ttyLP1 earlycon\0" \
++	"fdt_addr=0x83000000\0"	\
++	"fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \
++	"fdt_high=0xffffffffffffffff\0"	\
++	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
++	"image=Image\0" \
++	"initrd_addr=0x83800000\0" \
++	"initrd_high=0xffffffffffffffff\0" \
++	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
++		"${script};\0" \
++	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
++	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
++	"mmcargs=setenv bootargs console=${console},${baudrate} " \
++		"root=PARTUUID=${uuid} rootwait " \
++	"mmcautodetect=yes\0" \
++	"mmcboot=echo Booting from mmc ...; " \
++		"run finduuid; run mmcargs; " \
++		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
++			"if run loadfdt; then " \
++				"booti ${loadaddr} - ${fdt_addr}; " \
++			"else " \
++				"echo WARN: Cannot load the DT; " \
++			"fi; " \
++		"else " \
++			"echo wait for boot; " \
++		"fi;\0" \
++	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
++	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
++	"netargs=setenv bootargs console=${console},${baudrate} " \
++		"root=/dev/nfs " \
++		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
++	"netboot=echo Booting from net ...; " \
++		"run netargs; " \
++		"if test ${ip_dyn} = yes; then " \
++			"setenv get_cmd dhcp; " \
++		"else " \
++			"setenv get_cmd tftp; " \
++		"fi; " \
++		"${get_cmd} ${loadaddr} ${image}; " \
++		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
++			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
++				"booti ${loadaddr} - ${fdt_addr}; " \
++			"else " \
++				"echo WARN: Cannot load the DT; " \
++			"fi; " \
++		"else " \
++			"booti; " \
++		"fi;\0" \
++	"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
++		"apalis-imx8qm/${fdt_file}; booti ${loadaddr} - " \
++		"${fdt_addr}\0" \
++	"panel=NULL\0" \
++	"script=boot.scr\0"
++
++#undef CONFIG_BOOTCOMMAND
++#define CONFIG_BOOTCOMMAND \
++	   "mmc dev ${mmcdev}; if mmc rescan; then " \
++		   "if run loadbootscript; then " \
++			   "run bootscript; " \
++		   "else " \
++			   "if run loadimage; then " \
++				   "run mmcboot; " \
++			   "else run netboot; " \
++			   "fi; " \
++		   "fi; " \
++	   "else booti ${loadaddr} - ${fdt_addr}; fi"
++
++/* Link Definitions */
++#define CONFIG_LOADADDR			0x80280000
++
++#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
++
++#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
++
++#define CONFIG_SYS_MEMTEST_START	0x88000000
++#define CONFIG_SYS_MEMTEST_END		0x89000000
++
++/* Environment in eMMC, before config block at the end of 1st "boot sector" */
++#define CONFIG_ENV_SIZE			SZ_8K
++#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
++					 CONFIG_TDX_CFG_BLOCK_OFFSET)
++#define CONFIG_SYS_MMC_ENV_DEV		0	/* USDHC1 eMMC */
++#define CONFIG_SYS_MMC_ENV_PART		1
++
++#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
++
++/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
++#define CONFIG_SYS_FSL_USDHC_NUM	3
++
++/* Size of malloc() pool */
++#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
++
++#define CONFIG_SYS_SDRAM_BASE		0x80000000
++#define PHYS_SDRAM_1			0x80000000
++#define PHYS_SDRAM_2			0x880000000
++#define PHYS_SDRAM_1_SIZE		SZ_2G		/* 2 GB */
++#define PHYS_SDRAM_2_SIZE		SZ_2G		/* 2 GB */
++
++/* Serial */
++#define CONFIG_BAUDRATE			115200
++
++/* Monitor Command Prompt */
++#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
++#define CONFIG_SYS_CBSIZE		SZ_2K
++#define CONFIG_SYS_MAXARGS		64
++#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
++#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
++					sizeof(CONFIG_SYS_PROMPT) + 16)
++
++/* Generic Timer Definitions */
++#define COUNTER_FREQUENCY		8000000	/* 8MHz */
++
++#endif /* __APALIS_IMX8QM_H */
+-- 
+2.14.5
+
diff --git a/recipes-bsp/u-boot-mainline/files/colibri-imx6ull/fw_env.config b/recipes-bsp/u-boot-mainline/files/colibri-imx6ull/fw_env.config
new file mode 100644
index 0000000..930bcee
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/colibri-imx6ull/fw_env.config
@@ -0,0 +1,10 @@
+# Configuration file for fw_(printenv/setenv) utility.
+# Up to two entries are valid, in this case the redundant
+# environment sector is assumed present.
+# Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash.
+# Futhermore, if the Flash sector size is ommitted, this value is assumed to
+# be the same as the Environment size, which is valid for NOR and SPI-dataflash
+
+# MTD device name	Device offset	Env. size	Flash sector size	Number of sectors
+# Colibri iMX6ULL
+/dev/mtd3		0x00000000	0x00020000	0x20000			4
diff --git a/recipes-bsp/u-boot-mainline/files/colibri-imx7-emmc/fw_env.config b/recipes-bsp/u-boot-mainline/files/colibri-imx7-emmc/fw_env.config
new file mode 100644
index 0000000..00f21bf
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/colibri-imx7-emmc/fw_env.config
@@ -0,0 +1,15 @@
+# Configuration file for fw_(printenv/setenv) utility.
+# Up to two entries are valid, in this case the redundant
+# environment sector is assumed present.
+# Device offset must be prefixed with 0x to be parsed as a hexadecimal value.
+# On a block device a negative offset is treated as a backwards offset from the
+# end of the device/partition, rather than a forwards offset from the start.
+
+# Colibri iMX7 Dual 1GB (eMMC)
+# U-Boot environment is stored at the end of the first eMMC boot partition
+# hence use a negative value. The environment is just in front of the config
+# block which occupies the last sector (hence -0x200)
+
+# Block device name	Device offset	Env. size
+/dev/mmcblk0boot0	-0x2200		0x2000
+
diff --git a/recipes-bsp/u-boot-mainline/files/colibri-imx7/fw_env.config b/recipes-bsp/u-boot-mainline/files/colibri-imx7/fw_env.config
new file mode 100644
index 0000000..b59116d
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/colibri-imx7/fw_env.config
@@ -0,0 +1,10 @@
+# Configuration file for fw_(printenv/setenv) utility.
+# Up to two entries are valid, in this case the redundant
+# environment sector is assumed present.
+# Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash.
+# Futhermore, if the Flash sector size is ommitted, this value is assumed to
+# be the same as the Environment size, which is valid for NOR and SPI-dataflash
+
+# MTD device name	Device offset	Env. size	Flash sector size	Number of sectors
+# Colibri iMX7
+/dev/mtd3		0x00000000	0x00020000	0x20000			4
diff --git a/recipes-bsp/u-boot-mainline/files/fw_env.config b/recipes-bsp/u-boot-mainline/files/fw_env.config
new file mode 100644
index 0000000..e054ccb
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/fw_env.config
@@ -0,0 +1,22 @@
+# Configuration file for fw_(printenv/setenv) utility.
+# Up to two entries are valid, in this case the redundant
+# environment sector is assumed present.
+# Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash.
+# Futhermore, if the Flash sector size is ommitted, this value is assumed to
+# be the same as the Environment size, which is valid for NOR and SPI-dataflash
+
+# NOR example
+# MTD device name	Device offset	Env. size	Flash sector size	Number of sectors
+#/dev/mtd1		0x0000		0x4000		0x4000
+#/dev/mtd2		0x0000		0x4000		0x4000
+
+# MTD SPI-dataflash example
+# MTD device name	Device offset	Env. size	Flash sector size	Number of sectors
+#/dev/mtd5		0x4200		0x4200
+#/dev/mtd6		0x4200		0x4200
+
+# NAND example
+#/dev/mtd0		0x4000		0x4000		0x20000			2
+
+# Block device example
+#/dev/mmcblk0		0xc0000		0x20000
diff --git a/recipes-bsp/u-boot-mainline/files/mx6/fw_env.config b/recipes-bsp/u-boot-mainline/files/mx6/fw_env.config
new file mode 100644
index 0000000..a9e724e
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/mx6/fw_env.config
@@ -0,0 +1,17 @@
+# Configuration file for fw_(printenv/setenv) utility.
+# Up to two entries are valid, in this case the redundant
+# environment sector is assumed present.
+# Device offset must be prefixed with 0x to be parsed as a hexadecimal value.
+# On a block device a negative offset is treated as a backwards offset from the
+# end of the device/partition, rather than a forwards offset from the start.
+
+# Colibri iMX6/Apalis iMX6
+# U-Boot environment is stored at the end of the first eMMC boot partition
+# hence use a negative value. The environment is just in front of the config
+# block which occupies the last sector (hence -0x200)
+# Note that /dev/mmcblk0boot0 by default is read only
+# To use fw_setenv you have to first make it writeable, on the cmdline e.g. by
+# $ echo 0 > /sys/block/mmcblk0boot0/force_ro
+
+# Block device name	Device offset	Env. size
+/dev/mmcblk0boot0	-0x2200		0x2000
diff --git a/recipes-bsp/u-boot-mainline/files/mx8/fw_env.config b/recipes-bsp/u-boot-mainline/files/mx8/fw_env.config
new file mode 100644
index 0000000..a9e724e
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/files/mx8/fw_env.config
@@ -0,0 +1,17 @@
+# Configuration file for fw_(printenv/setenv) utility.
+# Up to two entries are valid, in this case the redundant
+# environment sector is assumed present.
+# Device offset must be prefixed with 0x to be parsed as a hexadecimal value.
+# On a block device a negative offset is treated as a backwards offset from the
+# end of the device/partition, rather than a forwards offset from the start.
+
+# Colibri iMX6/Apalis iMX6
+# U-Boot environment is stored at the end of the first eMMC boot partition
+# hence use a negative value. The environment is just in front of the config
+# block which occupies the last sector (hence -0x200)
+# Note that /dev/mmcblk0boot0 by default is read only
+# To use fw_setenv you have to first make it writeable, on the cmdline e.g. by
+# $ echo 0 > /sys/block/mmcblk0boot0/force_ro
+
+# Block device name	Device offset	Env. size
+/dev/mmcblk0boot0	-0x2200		0x2000
diff --git a/recipes-bsp/u-boot-mainline/u-boot-common.inc b/recipes-bsp/u-boot-mainline/u-boot-common.inc
new file mode 100644
index 0000000..94bc91e
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/u-boot-common.inc
@@ -0,0 +1,36 @@
+HOMEPAGE = "http://www.denx.de/wiki/U-Boot/WebHome"
+SECTION = "bootloaders"
+DEPENDS += "flex-native bison-native"
+
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e"
+PE = "1"
+
+# We use the revision in order to avoid having to fetch it from the
+# repo during parse
+SRCREV = "b4ee6daad7a2604ca9466b2ba48de86cc27d381f"
+
+SRC_URI = "git://git.denx.de/u-boot.git"
+
+SRC_URI += " \
+    file://0001-configs-colibri_imx6-don-t-configure-video-in-spl.patch \
+    file://0002-configs-apalis_imx6-don-t-configure-video-in-spl.patch \
+    file://0003-usb-limit-USB_MAX_XFER_BLK-to-256.patch \
+    file://0004-apalis_imx6-add-device-tree-to-makefile.patch \
+    file://0005-colibri-imx6ull-fix-usb-host-mode.patch \
+    file://0006-net-fec_mxc-not-access-reserved-register-on-i.MX8.patch \
+    file://0007-imx-fix-building-for-i.mx8-without-spl.patch \
+    file://0008-board-toradex-add-colibri-imx8qxp-2gb-wb-it-v1.0b-mo.patch \
+    file://0009-board-toradex-drop-support.arm-maintainer-email.patch \
+    file://0010-misc-imx8-add-sc_misc_get_temp.patch \
+    file://0011-thermal-add-i.MX8-thermal-driver.patch \
+    file://0012-imx8-cpu-get-temperature-when-print-cpu-desc.patch \
+    file://0013-imx-imx8dx-qxp-enable-thermal.patch \
+    file://0014-arm-dts-imx8qm-add-lpuart1-lpuart2-lpuart3-lpuart4.patch \
+    file://0015-arm-dts-imx8qm-add-support-for-i2c0-i2c1-i2c2-i2c3-a.patch \
+    file://0016-clk-imx8qm-fix-usdhc2-clocks.patch \
+    file://0017-imx8qm-fix-cpu-frequency-reporting.patch \
+    file://0018-imx8-fuse-fix-fuse-driver.patch \
+    file://0019-board-toradex-add-apalis-imx8qm-4gb-wb-it-v1.0b-modu.patch \
+"
+S = "${WORKDIR}/git"
diff --git a/recipes-bsp/u-boot-mainline/u-boot-fw-utils_2019.07plus.bb b/recipes-bsp/u-boot-mainline/u-boot-fw-utils_2019.07plus.bb
new file mode 100644
index 0000000..b5ce568
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/u-boot-fw-utils_2019.07plus.bb
@@ -0,0 +1,34 @@
+require u-boot-common.inc
+
+SUMMARY = "U-Boot bootloader fw_printenv/setenv utilities"
+DEPENDS += "mtd-utils"
+
+INSANE_SKIP_${PN} = "already-stripped"
+EXTRA_OEMAKE_class-target = 'CROSS_COMPILE=${TARGET_PREFIX} CC="${CC} ${CFLAGS} ${LDFLAGS}" HOSTCC="${BUILD_CC} ${BUILD_CFLAGS} ${BUILD_LDFLAGS}" V=1'
+EXTRA_OEMAKE_class-cross = 'HOSTCC="${CC} ${CFLAGS} ${LDFLAGS}" V=1'
+
+inherit uboot-config
+
+do_compile () {
+	oe_runmake ${UBOOT_MACHINE}
+	oe_runmake envtools
+}
+
+do_install () {
+	install -d ${D}${base_sbindir}
+	install -d ${D}${sysconfdir}
+	install -m 755 ${S}/tools/env/fw_printenv ${D}${base_sbindir}/fw_printenv
+	install -m 755 ${S}/tools/env/fw_printenv ${D}${base_sbindir}/fw_setenv
+	install -m 0644 ${S}/tools/env/fw_env.config ${D}${sysconfdir}/fw_env.config
+}
+
+do_install_class-cross () {
+	install -d ${D}${bindir_cross}
+	install -m 755 ${S}/tools/env/fw_printenv ${D}${bindir_cross}/fw_printenv
+	install -m 755 ${S}/tools/env/fw_printenv ${D}${bindir_cross}/fw_setenv
+}
+
+SYSROOT_DIRS_append_class-cross = " ${bindir_cross}"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+BBCLASSEXTEND = "cross"
diff --git a/recipes-bsp/u-boot-mainline/u-boot-tools_2019.07plus.bb b/recipes-bsp/u-boot-mainline/u-boot-tools_2019.07plus.bb
new file mode 100644
index 0000000..bede984
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/u-boot-tools_2019.07plus.bb
@@ -0,0 +1,67 @@
+require u-boot-common.inc
+
+SUMMARY = "U-Boot bootloader tools"
+DEPENDS += "openssl"
+
+PROVIDES = "${MLPREFIX}u-boot-mkimage ${MLPREFIX}u-boot-mkenvimage"
+PROVIDES_class-native = "u-boot-mkimage-native u-boot-mkenvimage-native"
+
+PACKAGES += "${PN}-mkimage ${PN}-mkenvimage"
+
+# Required for backward compatibility with "u-boot-mkimage-xxx.bb"
+RPROVIDES_${PN}-mkimage = "u-boot-mkimage"
+RREPLACES_${PN}-mkimage = "u-boot-mkimage"
+RCONFLICTS_${PN}-mkimage = "u-boot-mkimage"
+
+EXTRA_OEMAKE_class-target = 'CROSS_COMPILE="${TARGET_PREFIX}" CC="${CC} ${CFLAGS} ${LDFLAGS}" HOSTCC="${BUILD_CC} ${BUILD_CFLAGS} ${BUILD_LDFLAGS}" STRIP=true V=1'
+EXTRA_OEMAKE_class-native = 'CC="${BUILD_CC} ${BUILD_CFLAGS} ${BUILD_LDFLAGS}" HOSTCC="${BUILD_CC} ${BUILD_CFLAGS} ${BUILD_LDFLAGS}" STRIP=true V=1'
+EXTRA_OEMAKE_class-nativesdk = 'CROSS_COMPILE="${HOST_PREFIX}" CC="${CC} ${CFLAGS} ${LDFLAGS}" HOSTCC="${BUILD_CC} ${BUILD_CFLAGS} ${BUILD_LDFLAGS}" STRIP=true V=1'
+
+SED_CONFIG_EFI = '-e "s/CONFIG_EFI_LOADER=.*/# CONFIG_EFI_LOADER is not set/"'
+SED_CONFIG_EFI_x86 = ''
+SED_CONFIG_EFI_x86-64 = ''
+SED_CONFIG_EFI_arm = ''
+SED_CONFIG_EFI_armeb = ''
+SED_CONFIG_EFI_aarch64 = ''
+
+do_compile () {
+	oe_runmake sandbox_defconfig
+
+	# Disable CONFIG_CMD_LICENSE, license.h is not used by tools and
+	# generating it requires bin2header tool, which for target build
+	# is built with target tools and thus cannot be executed on host.
+	sed -i -e "s/CONFIG_CMD_LICENSE=.*/# CONFIG_CMD_LICENSE is not set/" ${SED_CONFIG_EFI} .config
+
+	oe_runmake cross_tools NO_SDL=1
+}
+
+do_install () {
+	install -d ${D}${bindir}
+
+	# mkimage
+	install -m 0755 tools/mkimage ${D}${bindir}/uboot-mkimage
+	ln -sf uboot-mkimage ${D}${bindir}/mkimage
+
+	# mkenvimage
+	install -m 0755 tools/mkenvimage ${D}${bindir}/uboot-mkenvimage
+	ln -sf uboot-mkenvimage ${D}${bindir}/mkenvimage
+
+	# dumpimage
+	install -m 0755 tools/dumpimage ${D}${bindir}/uboot-dumpimage
+	ln -sf uboot-dumpimage ${D}${bindir}/dumpimage
+
+	# fit_check_sign
+	install -m 0755 tools/fit_check_sign ${D}${bindir}/uboot-fit_check_sign
+	ln -sf uboot-fit_check_sign ${D}${bindir}/fit_check_sign
+}
+
+ALLOW_EMPTY_${PN} = "1"
+FILES_${PN} = ""
+FILES_${PN}-mkimage = "${bindir}/uboot-mkimage ${bindir}/mkimage ${bindir}/uboot-dumpimage ${bindir}/dumpimage ${bindir}/uboot-fit_check_sign ${bindir}/fit_check_sign"
+FILES_${PN}-mkenvimage = "${bindir}/uboot-mkenvimage ${bindir}/mkenvimage"
+
+RDEPENDS_${PN}-mkimage += "dtc"
+RDEPENDS_${PN} += "${PN}-mkimage ${PN}-mkenvimage"
+RDEPENDS_${PN}_class-native = ""
+
+BBCLASSEXTEND = "native nativesdk"
diff --git a/recipes-bsp/u-boot-mainline/u-boot.inc b/recipes-bsp/u-boot-mainline/u-boot.inc
new file mode 100644
index 0000000..9a754fd
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/u-boot.inc
@@ -0,0 +1,333 @@
+SUMMARY = "Universal Boot Loader for embedded devices"
+PROVIDES = "virtual/bootloader"
+
+B = "${WORKDIR}/build"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+DEPENDS += "kern-tools-native"
+
+inherit uboot-config uboot-extlinux-config uboot-sign deploy cml1
+
+DEPENDS += "swig-native python-native"
+
+EXTRA_OEMAKE = 'CROSS_COMPILE=${TARGET_PREFIX} CC="${TARGET_PREFIX}gcc ${TOOLCHAIN_OPTIONS}" V=1'
+EXTRA_OEMAKE += 'HOSTCC="${BUILD_CC} ${BUILD_CFLAGS} ${BUILD_LDFLAGS}"'
+EXTRA_OEMAKE += 'PYTHON2=nativepython STAGING_INCDIR=${STAGING_INCDIR_NATIVE} STAGING_LIBDIR=${STAGING_LIBDIR_NATIVE}'
+
+PACKAGECONFIG ??= "openssl"
+# u-boot will compile its own tools during the build, with specific
+# configurations (aka when CONFIG_FIT_SIGNATURE is enabled) openssl is needed as
+# a host build dependency.
+PACKAGECONFIG[openssl] = ",,openssl-native"
+
+# Allow setting an additional version string that will be picked up by the
+# u-boot build system and appended to the u-boot version.  If the .scmversion
+# file already exists it will not be overwritten.
+UBOOT_LOCALVERSION ?= ""
+
+# Some versions of u-boot use .bin and others use .img.  By default use .bin
+# but enable individual recipes to change this value.
+UBOOT_SUFFIX ??= "bin"
+UBOOT_IMAGE ?= "u-boot-${MACHINE}-${PV}-${PR}.${UBOOT_SUFFIX}"
+UBOOT_SYMLINK ?= "u-boot-${MACHINE}.${UBOOT_SUFFIX}"
+UBOOT_MAKE_TARGET ?= "all"
+
+# Output the ELF generated. Some platforms can use the ELF file and directly
+# load it (JTAG booting, QEMU) additionally the ELF can be used for debugging
+# purposes.
+UBOOT_ELF ?= ""
+UBOOT_ELF_SUFFIX ?= "elf"
+UBOOT_ELF_IMAGE ?= "u-boot-${MACHINE}-${PV}-${PR}.${UBOOT_ELF_SUFFIX}"
+UBOOT_ELF_BINARY ?= "u-boot.${UBOOT_ELF_SUFFIX}"
+UBOOT_ELF_SYMLINK ?= "u-boot-${MACHINE}.${UBOOT_ELF_SUFFIX}"
+
+# Some versions of u-boot build an SPL (Second Program Loader) image that
+# should be packaged along with the u-boot binary as well as placed in the
+# deploy directory.  For those versions they can set the following variables
+# to allow packaging the SPL.
+SPL_BINARY ?= ""
+SPL_BINARYNAME ?= "${@os.path.basename(d.getVar("SPL_BINARY"))}"
+SPL_IMAGE ?= "${SPL_BINARYNAME}-${MACHINE}-${PV}-${PR}"
+SPL_SYMLINK ?= "${SPL_BINARYNAME}-${MACHINE}"
+
+# Additional environment variables or a script can be installed alongside
+# u-boot to be used automatically on boot.  This file, typically 'uEnv.txt'
+# or 'boot.scr', should be packaged along with u-boot as well as placed in the
+# deploy directory.  Machine configurations needing one of these files should
+# include it in the SRC_URI and set the UBOOT_ENV parameter.
+UBOOT_ENV_SUFFIX ?= "txt"
+UBOOT_ENV ?= ""
+UBOOT_ENV_BINARY ?= "${UBOOT_ENV}.${UBOOT_ENV_SUFFIX}"
+UBOOT_ENV_IMAGE ?= "${UBOOT_ENV}-${MACHINE}-${PV}-${PR}.${UBOOT_ENV_SUFFIX}"
+UBOOT_ENV_SYMLINK ?= "${UBOOT_ENV}-${MACHINE}.${UBOOT_ENV_SUFFIX}"
+
+# U-Boot EXTLINUX variables. U-Boot searches for /boot/extlinux/extlinux.conf
+# to find EXTLINUX conf file.
+UBOOT_EXTLINUX_INSTALL_DIR ?= "/boot/extlinux"
+UBOOT_EXTLINUX_CONF_NAME ?= "extlinux.conf"
+UBOOT_EXTLINUX_SYMLINK ?= "${UBOOT_EXTLINUX_CONF_NAME}-${MACHINE}-${PR}"
+
+# returns all the elements from the src uri that are .cfg files
+def find_cfgs(d):
+    sources=src_patches(d, True)
+    sources_list=[]
+    for s in sources:
+        if s.endswith('.cfg'):
+            sources_list.append(s)
+
+    return sources_list
+
+do_configure () {
+    if [ -z "${UBOOT_CONFIG}" ]; then
+        if [ -n "${UBOOT_MACHINE}" ]; then
+            oe_runmake -C ${S} O=${B} ${UBOOT_MACHINE}
+        else
+            oe_runmake -C ${S} O=${B} oldconfig
+        fi
+        merge_config.sh -m .config ${@" ".join(find_cfgs(d))}
+        cml1_do_configure
+    fi
+}
+
+do_compile () {
+	if [ "${@bb.utils.filter('DISTRO_FEATURES', 'ld-is-gold', d)}" ]; then
+		sed -i 's/$(CROSS_COMPILE)ld$/$(CROSS_COMPILE)ld.bfd/g' ${S}/config.mk
+	fi
+
+	unset LDFLAGS
+	unset CFLAGS
+	unset CPPFLAGS
+
+	if [ ! -e ${B}/.scmversion -a ! -e ${S}/.scmversion ]
+	then
+		echo ${UBOOT_LOCALVERSION} > ${B}/.scmversion
+		echo ${UBOOT_LOCALVERSION} > ${S}/.scmversion
+	fi
+
+    if [ -n "${UBOOT_CONFIG}" ]
+    then
+        unset i j k
+        for config in ${UBOOT_MACHINE}; do
+            i=$(expr $i + 1);
+            for type in ${UBOOT_CONFIG}; do
+                j=$(expr $j + 1);
+                if [ $j -eq $i ]
+                then
+                    oe_runmake -C ${S} O=${B}/${config} ${config}
+                    oe_runmake -C ${S} O=${B}/${config} ${UBOOT_MAKE_TARGET}
+                    for binary in ${UBOOT_BINARIES}; do
+                        k=$(expr $k + 1);
+                        if [ $k -eq $i ]; then
+                            cp ${B}/${config}/${binary} ${B}/${config}/u-boot-${type}.${UBOOT_SUFFIX}
+                        fi
+                    done
+                    unset k
+                fi
+            done
+            unset  j
+        done
+        unset  i
+    else
+        oe_runmake -C ${S} O=${B} ${UBOOT_MAKE_TARGET}
+    fi
+
+}
+
+do_install () {
+    if [ -n "${UBOOT_CONFIG}" ]
+    then
+        for config in ${UBOOT_MACHINE}; do
+            i=$(expr $i + 1);
+            for type in ${UBOOT_CONFIG}; do
+                j=$(expr $j + 1);
+                if [ $j -eq $i ]
+                then
+                    install -d ${D}/boot
+                    install -m 644 ${B}/${config}/u-boot-${type}.${UBOOT_SUFFIX} ${D}/boot/u-boot-${type}-${PV}-${PR}.${UBOOT_SUFFIX}
+                    ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_SUFFIX} ${D}/boot/${UBOOT_BINARY}-${type}
+                    ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_SUFFIX} ${D}/boot/${UBOOT_BINARY}
+                fi
+            done
+            unset  j
+        done
+        unset  i
+    else
+        install -d ${D}/boot
+        install -m 644 ${B}/${UBOOT_BINARY} ${D}/boot/${UBOOT_IMAGE}
+        ln -sf ${UBOOT_IMAGE} ${D}/boot/${UBOOT_BINARY}
+    fi
+
+    if [ -n "${UBOOT_ELF}" ]
+    then
+        if [ -n "${UBOOT_CONFIG}" ]
+        then
+            for config in ${UBOOT_MACHINE}; do
+                i=$(expr $i + 1);
+                for type in ${UBOOT_CONFIG}; do
+                    j=$(expr $j + 1);
+                    if [ $j -eq $i ]
+                    then
+                        install -m 644 ${B}/${config}/${UBOOT_ELF} ${D}/boot/u-boot-${type}-${PV}-${PR}.${UBOOT_ELF_SUFFIX}
+                        ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_ELF_SUFFIX} ${D}/boot/${UBOOT_BINARY}-${type}
+                        ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_ELF_SUFFIX} ${D}/boot/${UBOOT_BINARY}
+                    fi
+                done
+                unset j
+            done
+            unset i
+        else
+            install -m 644 ${B}/${UBOOT_ELF} ${D}/boot/${UBOOT_ELF_IMAGE}
+            ln -sf ${UBOOT_ELF_IMAGE} ${D}/boot/${UBOOT_ELF_BINARY}
+        fi
+    fi
+
+    if [ -e ${WORKDIR}/fw_env.config ] ; then
+        install -d ${D}${sysconfdir}
+        install -m 644 ${WORKDIR}/fw_env.config ${D}${sysconfdir}/fw_env.config
+    fi
+
+    if [ -n "${SPL_BINARY}" ]
+    then
+        if [ -n "${UBOOT_CONFIG}" ]
+        then
+            for config in ${UBOOT_MACHINE}; do
+                i=$(expr $i + 1);
+                for type in ${UBOOT_CONFIG}; do
+                    j=$(expr $j + 1);
+                    if [ $j -eq $i ]
+                    then
+                         install -m 644 ${B}/${config}/${SPL_BINARY} ${D}/boot/${SPL_IMAGE}-${type}-${PV}-${PR}
+                         ln -sf ${SPL_IMAGE}-${type}-${PV}-${PR} ${D}/boot/${SPL_BINARYNAME}-${type}
+                         ln -sf ${SPL_IMAGE}-${type}-${PV}-${PR} ${D}/boot/${SPL_BINARYNAME}
+                    fi
+                done
+                unset  j
+            done
+            unset  i
+        else
+            install -m 644 ${B}/${SPL_BINARY} ${D}/boot/${SPL_IMAGE}
+            ln -sf ${SPL_IMAGE} ${D}/boot/${SPL_BINARYNAME}
+        fi
+    fi
+
+    if [ -n "${UBOOT_ENV}" ]
+    then
+        install -m 644 ${WORKDIR}/${UBOOT_ENV_BINARY} ${D}/boot/${UBOOT_ENV_IMAGE}
+        ln -sf ${UBOOT_ENV_IMAGE} ${D}/boot/${UBOOT_ENV_BINARY}
+    fi
+
+    if [ "${UBOOT_EXTLINUX}" = "1" ]
+    then
+        install -Dm 0644 ${UBOOT_EXTLINUX_CONFIG} ${D}/${UBOOT_EXTLINUX_INSTALL_DIR}/${UBOOT_EXTLINUX_CONF_NAME}
+    fi
+
+}
+
+FILES_${PN} = "/boot ${sysconfdir} ${datadir}"
+
+do_deploy () {
+    if [ -n "${UBOOT_CONFIG}" ]
+    then
+        for config in ${UBOOT_MACHINE}; do
+            i=$(expr $i + 1);
+            for type in ${UBOOT_CONFIG}; do
+                j=$(expr $j + 1);
+                if [ $j -eq $i ]
+                then
+                    install -d ${DEPLOYDIR}
+                    install -m 644 ${B}/${config}/u-boot-${type}.${UBOOT_SUFFIX} ${DEPLOYDIR}/u-boot-${type}-${PV}-${PR}.${UBOOT_SUFFIX}
+                    cd ${DEPLOYDIR}
+                    ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_SUFFIX} ${UBOOT_SYMLINK}-${type}
+                    ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_SUFFIX} ${UBOOT_SYMLINK}
+                    ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_SUFFIX} ${UBOOT_BINARY}-${type}
+                    ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_SUFFIX} ${UBOOT_BINARY}
+                fi
+            done
+            unset  j
+        done
+        unset  i
+    else
+        install -d ${DEPLOYDIR}
+        install -m 644 ${B}/${UBOOT_BINARY} ${DEPLOYDIR}/${UBOOT_IMAGE}
+        cd ${DEPLOYDIR}
+        rm -f ${UBOOT_BINARY} ${UBOOT_SYMLINK}
+        ln -sf ${UBOOT_IMAGE} ${UBOOT_SYMLINK}
+        ln -sf ${UBOOT_IMAGE} ${UBOOT_BINARY}
+    fi
+
+    if [ -n "${UBOOT_ELF}" ]
+    then
+        if [ -n "${UBOOT_CONFIG}" ]
+        then
+            for config in ${UBOOT_MACHINE}; do
+                i=$(expr $i + 1);
+                for type in ${UBOOT_CONFIG}; do
+                    j=$(expr $j + 1);
+                    if [ $j -eq $i ]
+                    then
+                        install -m 644 ${B}/${config}/${UBOOT_ELF} ${DEPLOYDIR}/u-boot-${type}-${PV}-${PR}.${UBOOT_ELF_SUFFIX}
+                        ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_ELF_SUFFIX} ${DEPLOYDIR}/${UBOOT_ELF_BINARY}-${type}
+                        ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_ELF_SUFFIX} ${DEPLOYDIR}/${UBOOT_ELF_BINARY}
+                        ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_ELF_SUFFIX} ${DEPLOYDIR}/${UBOOT_ELF_SYMLINK}-${type}
+                        ln -sf u-boot-${type}-${PV}-${PR}.${UBOOT_ELF_SUFFIX} ${DEPLOYDIR}/${UBOOT_ELF_SYMLINK}
+                    fi
+                done
+                unset j
+            done
+            unset i
+        else
+            install -m 644 ${B}/${UBOOT_ELF} ${DEPLOYDIR}/${UBOOT_ELF_IMAGE}
+            ln -sf ${UBOOT_ELF_IMAGE} ${DEPLOYDIR}/${UBOOT_ELF_BINARY}
+            ln -sf ${UBOOT_ELF_IMAGE} ${DEPLOYDIR}/${UBOOT_ELF_SYMLINK}
+        fi
+    fi
+
+
+     if [ -n "${SPL_BINARY}" ]
+     then
+        if [ -n "${UBOOT_CONFIG}" ]
+        then
+            for config in ${UBOOT_MACHINE}; do
+                i=$(expr $i + 1);
+                for type in ${UBOOT_CONFIG}; do
+                    j=$(expr $j + 1);
+                    if [ $j -eq $i ]
+                    then
+                        install -m 644 ${B}/${config}/${SPL_BINARY} ${DEPLOYDIR}/${SPL_IMAGE}-${type}-${PV}-${PR}
+                        rm -f ${DEPLOYDIR}/${SPL_BINARYNAME} ${DEPLOYDIR}/${SPL_SYMLINK}-${type}
+                        ln -sf ${SPL_IMAGE}-${type}-${PV}-${PR} ${DEPLOYDIR}/${SPL_BINARYNAME}-${type}
+                        ln -sf ${SPL_IMAGE}-${type}-${PV}-${PR} ${DEPLOYDIR}/${SPL_BINARYNAME}
+                        ln -sf ${SPL_IMAGE}-${type}-${PV}-${PR} ${DEPLOYDIR}/${SPL_SYMLINK}-${type}
+                        ln -sf ${SPL_IMAGE}-${type}-${PV}-${PR} ${DEPLOYDIR}/${SPL_SYMLINK}
+                    fi
+                done
+                unset  j
+            done
+            unset  i
+        else
+            install -m 644 ${B}/${SPL_BINARY} ${DEPLOYDIR}/${SPL_IMAGE}
+            rm -f ${DEPLOYDIR}/${SPL_BINARYNAME} ${DEPLOYDIR}/${SPL_SYMLINK}
+            ln -sf ${SPL_IMAGE} ${DEPLOYDIR}/${SPL_BINARYNAME}
+            ln -sf ${SPL_IMAGE} ${DEPLOYDIR}/${SPL_SYMLINK}
+        fi
+    fi
+
+
+    if [ -n "${UBOOT_ENV}" ]
+    then
+        install -m 644 ${WORKDIR}/${UBOOT_ENV_BINARY} ${DEPLOYDIR}/${UBOOT_ENV_IMAGE}
+        rm -f ${DEPLOYDIR}/${UBOOT_ENV_BINARY} ${DEPLOYDIR}/${UBOOT_ENV_SYMLINK}
+        ln -sf ${UBOOT_ENV_IMAGE} ${DEPLOYDIR}/${UBOOT_ENV_BINARY}
+        ln -sf ${UBOOT_ENV_IMAGE} ${DEPLOYDIR}/${UBOOT_ENV_SYMLINK}
+    fi
+
+    if [ "${UBOOT_EXTLINUX}" = "1" ]
+    then
+        install -m 644 ${UBOOT_EXTLINUX_CONFIG} ${DEPLOYDIR}/${UBOOT_EXTLINUX_SYMLINK}
+        ln -sf ${UBOOT_EXTLINUX_SYMLINK} ${DEPLOYDIR}/${UBOOT_EXTLINUX_CONF_NAME}-${MACHINE}
+        ln -sf ${UBOOT_EXTLINUX_SYMLINK} ${DEPLOYDIR}/${UBOOT_EXTLINUX_CONF_NAME}
+    fi
+}
+
+addtask deploy before do_build after do_compile
diff --git a/recipes-bsp/u-boot-mainline/u-boot_2019.07plus.bb b/recipes-bsp/u-boot-mainline/u-boot_2019.07plus.bb
new file mode 100644
index 0000000..c7368c4
--- /dev/null
+++ b/recipes-bsp/u-boot-mainline/u-boot_2019.07plus.bb
@@ -0,0 +1,5 @@
+require u-boot-common.inc
+require u-boot.inc
+require recipes-bsp/u-boot/u-boot-toradex-initial-env.inc
+
+DEPENDS += "bc-native dtc-native"
author	Max Krummenacher <max.krummenacher@toradex.com>	2019-05-13 14:52:49 +0200
committer	Max Krummenacher <max.krummenacher@toradex.com>	2019-05-13 19:32:22 +0200
commit	258adbe3d2ac9c7c8d31e5071c0689a4227dae09 (patch)
tree	79c9c1168904b56bc9a1611f39ff31c3aefe4795
parent	dc4a695bba8f4becb8b821515e16079453ccd135 (diff)