diff options
Diffstat (limited to 'recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch')
| -rw-r--r-- | recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch b/recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch new file mode 100644 index 0000000..5ef6305 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch @@ -0,0 +1,65 @@ +From 025a98d87d9e2274a438d3878428c04abf4fc717 Mon Sep 17 00:00:00 2001 +From: Marcel Ziswiler <marcel@ziswiler.com> +Date: Mon, 29 Apr 2019 17:57:24 +0200 +Subject: [PATCH 16/19] clk: imx8qm: fix usdhc2 clocks + +Trying to bring up uSDHC2 the following error message was observed: + +MMC: imx8_clk_set_rate(Invalid clk ID #60) +imx8_clk_set_rate(Invalid clk ID #60) +usdhc@5b030000 - probe failed: -22 + +This commit fixes this by properly setting resp. clocks. + +Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> +Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com> +--- + drivers/clk/imx/clk-imx8qm.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c +index 6b5561e178..a6b09d2109 100644 +--- a/drivers/clk/imx/clk-imx8qm.c ++++ b/drivers/clk/imx/clk-imx8qm.c +@@ -80,6 +80,12 @@ ulong imx8_clk_get_rate(struct clk *clk) + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; ++ case IMX8QM_SDHC2_IPG_CLK: ++ case IMX8QM_SDHC2_CLK: ++ case IMX8QM_SDHC2_DIV: ++ resource = SC_R_SDHC_2; ++ pm_clk = SC_PM_CLK_PER; ++ break; + case IMX8QM_UART0_IPG_CLK: + case IMX8QM_UART0_CLK: + resource = SC_R_UART_0; +@@ -185,6 +191,12 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; ++ case IMX8QM_SDHC2_IPG_CLK: ++ case IMX8QM_SDHC2_CLK: ++ case IMX8QM_SDHC2_DIV: ++ resource = SC_R_SDHC_2; ++ pm_clk = SC_PM_CLK_PER; ++ break; + case IMX8QM_ENET0_IPG_CLK: + case IMX8QM_ENET0_AHB_CLK: + case IMX8QM_ENET0_REF_DIV: +@@ -273,6 +285,12 @@ int __imx8_clk_enable(struct clk *clk, bool enable) + resource = SC_R_SDHC_1; + pm_clk = SC_PM_CLK_PER; + break; ++ case IMX8QM_SDHC2_IPG_CLK: ++ case IMX8QM_SDHC2_CLK: ++ case IMX8QM_SDHC2_DIV: ++ resource = SC_R_SDHC_2; ++ pm_clk = SC_PM_CLK_PER; ++ break; + case IMX8QM_ENET0_IPG_CLK: + case IMX8QM_ENET0_AHB_CLK: + case IMX8QM_ENET0_REF_DIV: +-- +2.14.5 + |