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Branch name: imx_4.14.98_2.0.0_ga
Build version: 3332
Commit ID: 0x0cb6f758b
Build date: May 20 2019
Build time: 10:58:51
Our SCFW git hash:
f74abf46
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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This fixes RAM issue as see on Apalis iMX8QP and updates to latest RPA
with all fixes and e.g. proper CBT enablement.
Branch name: imx_4.14.98_2.0.0_ga
Build version: 3332
Commit ID: 0x0cb6f758b
Build date: May 20 2019
Build time: 10:58:51
Our SCFW git hash:
e8090f2
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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SCFW implementing proof of concept 1 GB resp. 2 GB vs. 2 GB resp. 4 GB
DDR SKU handling based on fuses indicating SoC being i.MX 8QP resp. 8DX
vs. 8QM resp. 8QXP.
Branch name: imx_4.14.98_2.0.0_ga
Build version: 3332
Commit ID: 0x0cb6f758b
Build date: May 20 2019
Build time: 10:58:51
Our SCFW git hash:
71682f29
Note: this also requires a later U-Boot supporting SKU memory sizing.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Update to version based on NXP SCFW 1.2.2.
Branch name: imx_4.14.98_2.0.0_ga
Build version: 3332
Commit ID: 0x0cb6f758b
Build date: May 20 2019
Build time: 10:58:51
Our SCFW git hash:
56ee0444
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Changes:
Update to version based on NXP SCFW 1.1.2.
Branch name: imx_4.14.78_1.0.0_ga
Build version: 3014
Commit ID: 0x0f0226b37
Build date: Mar 27 2019
Build time: 14:47:32
Our SCFW git hash:
8f160f9
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Changes:
Apalis iMX8QM: Adapt for B0 DDR config and timings
Colibri iMX8QXP: Disable debug UART, so that it can be used for Cortex-M4
Our SCFW git hash:
7c04e56
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Version based on NXP SCFW 1.1.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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