From 71ad5dd6bbc05dc7aae5e7527716e3f95a0d5ba7 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Tue, 4 Jun 2019 16:07:51 +0200 Subject: u-boot: update to v2019.07-rc4+ Add patches currently on the ML targeting Toradex boards and fetch latest and greatest of master branch. Signed-off-by: Max Krummenacher --- ...onvenient-default-value-for-SYS_MALLOC_F_.patch | 42 - ...imx8-cpu-fix-warning-for-cpu_imx_get_temp.patch | 58 + .../0001-usb-limit-USB_MAX_XFER_BLK-to-256.patch | 67 + ...ideo-mxsfb-fix-mxsfb-fbdev-binding-issues.patch | 137 ++ ...ts-colibri_imx7-Fix-lcdif-node-definition.patch | 79 + .../0002-misc-imx8-add-sc_misc_get_temp.patch | 80 + ...-video-fsl_dcu_fb-refactor-init-functions.patch | 288 +++ ...0003-configs-colibri_imx7-enable-DM_VIDEO.patch | 27 + .../0003-thermal-add-i.MX8-thermal-driver.patch | 257 ++ .../0003-usb-limit-USB_MAX_XFER_BLK-to-256.patch | 67 - ...003-video-fsl_dcu_fb-add-DM_VIDEO-support.patch | 229 ++ .../0004-ARM-dts-colibri_vf-Add-dcu0-node.patch | 68 + ...4-apalis_imx6-add-device-tree-to-makefile.patch | 48 - ...-imx6ull-support-building-with-DM_VIDEO-y.patch | 44 + .../files/0004-imx-imx8dx-qxp-enable-thermal.patch | 103 + ...ARM-dts-colibri-imx6ull-extend-lcdif-node.patch | 68 + .../0005-colibri-imx6ull-fix-usb-host-mode.patch | 37 - .../files/0005-colibri_vf-enable-DM_VIDEO.patch | 28 + .../0005-misc-imx8-add-sc_rm_set_master_sid.patch | 63 + ...-14938-8-imx8-Add-SMMU-setup-to-Soc-codes.patch | 117 + ...006-colibri-apalis-tegra-drop-DFU-support.patch | 104 + ...onfigs-colibri-imx6ull-switch-to-DM_VIDEO.patch | 27 + ...mxc-not-access-reserved-register-on-i.MX8.patch | 29 - .../files/0007-apalis-imx8-enable-smmu-setup.patch | 25 + .../0007-colibri-apalis-imx-drop-DFU-support.patch | 92 + ...07-imx-fix-building-for-i.mx8-without-spl.patch | 37 - ...mx8qm-qxp-Disable-kernel-FDT-nodes-for-th.patch | 154 ++ ...ex-add-colibri-imx8qxp-2gb-wb-it-v1.0b-mo.patch | 1228 ---------- ...-imx8-Configure-sids-based-on-iommu-prope.patch | 120 + ...toradex-drop-support.arm-maintainer-email.patch | 42 - .../0010-apalis-imx8-enable-of_system_setup.patch | 25 + .../0010-misc-imx8-add-sc_misc_get_temp.patch | 80 - ...-video-imx-hdp-Adding-support-for-HDP-fir.patch | 2560 ++++++++++++++++++++ .../0011-thermal-add-i.MX8-thermal-driver.patch | 257 -- ...-video-imx-hdp-Adding-HDP-firmware-loadin.patch | 37 + ...8-cpu-get-temperature-when-print-cpu-desc.patch | 75 - ...-video-imx-hdp-Adding-configs-for-HDP-fir.patch | 54 + .../files/0013-imx-imx8dx-qxp-enable-thermal.patch | 103 - ...4-apalis-imx8-enable-hdp-firmware-loading.patch | 65 + ...mx8qm-add-lpuart1-lpuart2-lpuart3-lpuart4.patch | 122 - ...8qm-add-support-for-i2c0-i2c1-i2c2-i2c3-a.patch | 110 - .../files/0016-clk-imx8qm-fix-usdhc2-clocks.patch | 65 - .../0017-imx8qm-fix-cpu-frequency-reporting.patch | 40 - .../files/0018-imx8-fuse-fix-fuse-driver.patch | 35 - ...ex-add-apalis-imx8qm-4gb-wb-it-v1.0b-modu.patch | 1434 ----------- ...video_mxsfb_fix_mxsfb_fbdev_binding_issues.mbox | 1140 +++++++++ recipes-bsp/u-boot-mainline/u-boot-common.inc | 51 +- 47 files changed, 6148 insertions(+), 3870 deletions(-) delete mode 100644 recipes-bsp/u-boot-mainline/files/0001-imx-Use-a-convenient-default-value-for-SYS_MALLOC_F_.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0001-imx8-cpu-fix-warning-for-cpu_imx_get_temp.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0001-usb-limit-USB_MAX_XFER_BLK-to-256.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0001-video-mxsfb-fix-mxsfb-fbdev-binding-issues.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0002-ARM-dts-colibri_imx7-Fix-lcdif-node-definition.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0002-misc-imx8-add-sc_misc_get_temp.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0002-video-fsl_dcu_fb-refactor-init-functions.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0003-configs-colibri_imx7-enable-DM_VIDEO.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0003-thermal-add-i.MX8-thermal-driver.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0003-usb-limit-USB_MAX_XFER_BLK-to-256.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0003-video-fsl_dcu_fb-add-DM_VIDEO-support.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0004-ARM-dts-colibri_vf-Add-dcu0-node.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0004-apalis_imx6-add-device-tree-to-makefile.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0004-colibri-imx6ull-support-building-with-DM_VIDEO-y.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0004-imx-imx8dx-qxp-enable-thermal.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0005-ARM-dts-colibri-imx6ull-extend-lcdif-node.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0005-colibri-imx6ull-fix-usb-host-mode.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0005-colibri_vf-enable-DM_VIDEO.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0005-misc-imx8-add-sc_rm_set_master_sid.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0006-MLK-14938-8-imx8-Add-SMMU-setup-to-Soc-codes.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0006-colibri-apalis-tegra-drop-DFU-support.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0006-configs-colibri-imx6ull-switch-to-DM_VIDEO.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0006-net-fec_mxc-not-access-reserved-register-on-i.MX8.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0007-apalis-imx8-enable-smmu-setup.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0007-colibri-apalis-imx-drop-DFU-support.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0007-imx-fix-building-for-i.mx8-without-spl.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0008-MLK-16087-imx8qm-qxp-Disable-kernel-FDT-nodes-for-th.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0008-board-toradex-add-colibri-imx8qxp-2gb-wb-it-v1.0b-mo.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0009-MLK-16560-1-imx8-Configure-sids-based-on-iommu-prope.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0009-board-toradex-drop-support.arm-maintainer-email.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0010-apalis-imx8-enable-of_system_setup.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0010-misc-imx8-add-sc_misc_get_temp.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0011-MLK-17205-1-video-imx-hdp-Adding-support-for-HDP-fir.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0011-thermal-add-i.MX8-thermal-driver.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0012-MLK-17205-2-video-imx-hdp-Adding-HDP-firmware-loadin.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0012-imx8-cpu-get-temperature-when-print-cpu-desc.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0013-MLK-17205-3-video-imx-hdp-Adding-configs-for-HDP-fir.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0013-imx-imx8dx-qxp-enable-thermal.patch create mode 100644 recipes-bsp/u-boot-mainline/files/0014-apalis-imx8-enable-hdp-firmware-loading.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0014-arm-dts-imx8qm-add-lpuart1-lpuart2-lpuart3-lpuart4.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0015-arm-dts-imx8qm-add-support-for-i2c0-i2c1-i2c2-i2c3-a.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0017-imx8qm-fix-cpu-frequency-reporting.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0018-imx8-fuse-fix-fuse-driver.patch delete mode 100644 recipes-bsp/u-boot-mainline/files/0019-board-toradex-add-apalis-imx8qm-4gb-wb-it-v1.0b-modu.patch create mode 100644 recipes-bsp/u-boot-mainline/files/video_mxsfb_fix_mxsfb_fbdev_binding_issues.mbox diff --git a/recipes-bsp/u-boot-mainline/files/0001-imx-Use-a-convenient-default-value-for-SYS_MALLOC_F_.patch b/recipes-bsp/u-boot-mainline/files/0001-imx-Use-a-convenient-default-value-for-SYS_MALLOC_F_.patch deleted file mode 100644 index 0c7df2a..0000000 --- a/recipes-bsp/u-boot-mainline/files/0001-imx-Use-a-convenient-default-value-for-SYS_MALLOC_F_.patch +++ /dev/null @@ -1,42 +0,0 @@ -From d15d7403a8f511a1c8b4cd25410f351c46e3b8af Mon Sep 17 00:00:00 2001 -From: Fabio Estevam -Date: Fri, 3 May 2019 14:05:04 -0300 -Subject: [PATCH] imx: Use a convenient default value for SYS_MALLOC_F_LEN - -Commit 3a7c45f6a772 ("simple-bus: add DM_FLAG_PRE_RELOC flag to -simple-bus driver") causes some i.MX boards that were converted -to DM, such as warp7, to fail to boot. - -As explained by Lukas Auer: - -"With the patch, U-Boot probes the drivers for devices under simple-bus -device tree nodes in the pre-relocation device model. The default value -of CONFIG_SYS_MALLOC_F_LEN (0x400) leaves U-Boot with not enough memory to -do this, causing it to hang." - -Fix this problem by providing a convenient default value for -CONFIG_SYS_MALLOC_F_LEN. - -Reported-by: Pierre-Jean Texier -Suggested-by: Lukas Auer -Signed-off-by: Fabio Estevam ---- - Kconfig | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Kconfig b/Kconfig -index 7a5491bd67..fd4ff42c17 100644 ---- a/Kconfig -+++ b/Kconfig -@@ -138,6 +138,8 @@ config SYS_MALLOC_F_LEN - depends on SYS_MALLOC_F - default 0x1000 if AM33XX - default 0x2800 if SANDBOX -+ default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \ -+ ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5) - default 0x400 - help - Before relocation, memory is very limited on many platforms. Still, --- -2.13.6 - diff --git a/recipes-bsp/u-boot-mainline/files/0001-imx8-cpu-fix-warning-for-cpu_imx_get_temp.patch b/recipes-bsp/u-boot-mainline/files/0001-imx8-cpu-fix-warning-for-cpu_imx_get_temp.patch new file mode 100644 index 0000000..ee07aa8 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0001-imx8-cpu-fix-warning-for-cpu_imx_get_temp.patch @@ -0,0 +1,58 @@ +From ffa531adf16d6de2362cc95f5776bc4667dab94f Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Mon, 13 May 2019 17:56:55 +0300 +Subject: [PATCH 1/7] imx8: cpu: fix warning for cpu_imx_get_temp +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +cpu_imx_get_temp() definition is wrapped with a ifdef macro, which leads +to warnings if CONFIG_IMX_SCU_THERMAL isn't defined and there are still +references to this function, as, for example, in cpu_imx_get_desc(). +Drop ifdef as linker will automatically remove the function +in case CONFIG_IMX_SCU_THERMAL is not enabled. + +Fix warning: +arch/arm/mach-imx/imx8/cpu.c: In function ‘cpu_imx_get_desc’: +arch/arm/mach-imx/imx8/cpu.c:612:40: warning: implicit declaration of +function ‘cpu_imx_get_temp’; did you mean ‘cpu_imx_get_desc’? +[-Wimplicit-function-declaration] + ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp()); + ^~~~~~~~~~~~~~~~ + cpu_imx_get_desc + cpu_imx_get_desc + +Fixes: 82467cb217 ("imx8: cpu: get temperature when print cpu desc") +Signed-off-by: Igor Opaniuk +--- + arch/arm/mach-imx/imx8/cpu.c | 7 ------- + 1 file changed, 7 deletions(-) + +diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c +index 4eb15de93e..d30ffcde3a 100644 +--- a/arch/arm/mach-imx/imx8/cpu.c ++++ b/arch/arm/mach-imx/imx8/cpu.c +@@ -815,7 +815,6 @@ const char *get_core_name(void) + return "?"; + } + +-#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL) + static int cpu_imx_get_temp(void) + { + struct udevice *thermal_dev; +@@ -834,12 +833,6 @@ static int cpu_imx_get_temp(void) + + return cpu_tmp; + } +-#else +-static int cpu_imx_get_temp(void) +-{ +- return 0; +-} +-#endif + + int cpu_imx_get_desc(struct udevice *dev, char *buf, int size) + { +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0001-usb-limit-USB_MAX_XFER_BLK-to-256.patch b/recipes-bsp/u-boot-mainline/files/0001-usb-limit-USB_MAX_XFER_BLK-to-256.patch new file mode 100644 index 0000000..8ba235b --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0001-usb-limit-USB_MAX_XFER_BLK-to-256.patch @@ -0,0 +1,67 @@ +From 0af97bbc0f71f00f63d2ef94ec54ade62f927cba Mon Sep 17 00:00:00 2001 +From: Peng Fan +Date: Mon, 6 Jun 2016 13:53:43 +0800 +Subject: [PATCH 01/15] usb: limit USB_MAX_XFER_BLK to 256 + +For Some USB mass storage devices, such as: +" + - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA + - Class: (from Interface) Mass Storage + - PacketSize: 64 Configurations: 1 + - Vendor: 0x0930 Product 0x6545 Version 1.16 +" +When `usb read 0x80000000 0 0x2000`, we met +"EHCI timed out on TD - token=0x80008d80". + +The devices does not support scsi VPD page, we are not able +to get the maximum transfer length for READ(10)/WRITE(10). + +So we limit this to 256 blocks as READ(6). + +Signed-off-by: Peng Fan +Acked-by: Marcel Ziswiler +(cherry picked from commit df0052575b2bc9d66ae73584768e1a457ed5d914) + +Series-to: u-boot@lists.denx.de + +Series-prefix: RFC + +Series-version: 3 + +Series-changes: 2 +- Fixed spelling in comment as suggested by Igor. + +Series-changes: 3 +- Drop the reference to the NXP internal MLK-xxx tracking number as + suggested by Peng. + +Commit-notes: +This comes from NXP's downstream and has proven to tremendously improve +the situation with those odd USB mass storage aka memory sticks. This is +why I post it here asking whether or not this may be something +benefiting more people. Any feedback and suggestions are welcome. +END +--- + common/usb_storage.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/common/usb_storage.c b/common/usb_storage.c +index 8c889bb1a6..4e284645f5 100644 +--- a/common/usb_storage.c ++++ b/common/usb_storage.c +@@ -949,7 +949,11 @@ static void usb_stor_set_max_xfer_blk(struct usb_device *udev, + * there is enough free heap space left, but the SCSI READ(10) and + * WRITE(10) commands are limited to 65535 blocks. + */ +- blk = USHRT_MAX; ++ /* ++ * Some USB mass storage devices have issues, limiting this to 256 ++ * fixes this. ++ */ ++ blk = 256; + #else + blk = 20; + #endif +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0001-video-mxsfb-fix-mxsfb-fbdev-binding-issues.patch b/recipes-bsp/u-boot-mainline/files/0001-video-mxsfb-fix-mxsfb-fbdev-binding-issues.patch new file mode 100644 index 0000000..2d69e46 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0001-video-mxsfb-fix-mxsfb-fbdev-binding-issues.patch @@ -0,0 +1,137 @@ +From a2f8aefaddc33c83518b5abbca334a8e1c235ef9 Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Wed, 19 Jun 2019 11:47:05 +0300 +Subject: [PATCH 1/6] video: mxsfb: fix mxsfb fbdev binding issues + +Add support for display and bits-per-pixel properties. + +Signed-off-by: Igor Opaniuk +--- + drivers/video/mxsfb.c | 74 ++++++++++++++++++++++++++++++++++++++++++--------- + 1 file changed, 62 insertions(+), 12 deletions(-) + +diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c +index f02ba20138..6c9a7c05e8 100644 +--- a/drivers/video/mxsfb.c ++++ b/drivers/video/mxsfb.c +@@ -271,6 +271,42 @@ dealloc_fb: + } + #else /* ifndef CONFIG_DM_VIDEO */ + ++static int mxs_of_get_timings(struct udevice *dev, ++ struct display_timing *timings, ++ u32 *bpp) ++{ ++ int ret = 0; ++ u32 display_phandle; ++ ofnode display_node; ++ ++ ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle); ++ if (ret) { ++ dev_err(dev, "required display property isn't provided\n"); ++ return -EINVAL; ++ } ++ ++ display_node = ofnode_get_by_phandle(display_phandle); ++ if (!ofnode_valid(display_node)) { ++ dev_err(dev, "failed to find display subnode\n"); ++ return -EINVAL; ++ } ++ ++ ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp); ++ if (ret) { ++ dev_err(dev, ++ "required bits-per-pixel property isn't provided\n"); ++ return -EINVAL; ++ } ++ ++ ret = ofnode_decode_display_timing(display_node, 0, timings); ++ if (ret) { ++ dev_err(dev, "failed to get any display timings\n"); ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ + static int mxs_video_probe(struct udevice *dev) + { + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); +@@ -278,18 +314,16 @@ static int mxs_video_probe(struct udevice *dev) + + struct ctfb_res_modes mode; + struct display_timing timings; +- int bpp = -1; ++ u32 bpp = 0; + u32 fb_start, fb_end; + int ret; + + debug("%s() plat: base 0x%lx, size 0x%x\n", + __func__, plat->base, plat->size); + +- ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings); +- if (ret) { +- dev_err(dev, "failed to get any display timings\n"); +- return -EINVAL; +- } ++ ret = mxs_of_get_timings(dev, &timings, &bpp); ++ if (ret) ++ return ret; + + mode.xres = timings.hactive.typ; + mode.yres = timings.vactive.typ; +@@ -301,13 +335,12 @@ static int mxs_video_probe(struct udevice *dev) + mode.vsync_len = timings.vsync_len.typ; + mode.pixclock = HZ2PS(timings.pixelclock.typ); + +- bpp = BITS_PP; +- + ret = mxs_probe_common(&mode, bpp, plat->base); + if (ret) + return ret; + + switch (bpp) { ++ case 32: + case 24: + case 18: + uc_priv->bpix = VIDEO_BPP32; +@@ -341,15 +374,32 @@ static int mxs_video_bind(struct udevice *dev) + { + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct display_timing timings; ++ u32 bpp = 0; ++ u32 bytes_pp = 0; + int ret; + +- ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings); +- if (ret) { +- dev_err(dev, "failed to get any display timings\n"); ++ ret = mxs_of_get_timings(dev, &timings, &bpp); ++ if (ret) ++ return ret; ++ ++ switch (bpp) { ++ case 32: ++ case 24: ++ case 18: ++ bytes_pp = 4; ++ break; ++ case 16: ++ bytes_pp = 2; ++ break; ++ case 8: ++ bytes_pp = 1; ++ break; ++ default: ++ dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp); + return -EINVAL; + } + +- plat->size = timings.hactive.typ * timings.vactive.typ * BYTES_PP; ++ plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp; + + return 0; + } +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0002-ARM-dts-colibri_imx7-Fix-lcdif-node-definition.patch b/recipes-bsp/u-boot-mainline/files/0002-ARM-dts-colibri_imx7-Fix-lcdif-node-definition.patch new file mode 100644 index 0000000..e291876 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0002-ARM-dts-colibri_imx7-Fix-lcdif-node-definition.patch @@ -0,0 +1,79 @@ +From 88d87b1ac2b5f8a1aecc339f92a9fca57d366bcc Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Wed, 19 Jun 2019 11:47:06 +0300 +Subject: [PATCH 2/6] ARM: dts: colibri_imx7: Fix lcdif node definition + +Fix lcdif DT node and make it conform to the structure defined in the +Linux devicetree bindings [1]. Currently there is support only for +old style lcdif node definitions. + +[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/display/mxsfb.txt + +Signed-off-by: Igor Opaniuk +--- + arch/arm/dts/imx7-colibri.dtsi | 47 +++++++++++++++++++++++------------------- + 1 file changed, 26 insertions(+), 21 deletions(-) + +diff --git a/arch/arm/dts/imx7-colibri.dtsi b/arch/arm/dts/imx7-colibri.dtsi +index 81717c233d..308e0b2a63 100644 +--- a/arch/arm/dts/imx7-colibri.dtsi ++++ b/arch/arm/dts/imx7-colibri.dtsi +@@ -113,29 +113,34 @@ + }; + + &lcdif { +- u-boot,dm-pre-reloc; + status = "okay"; ++ display = <&display0>; ++ u-boot,dm-pre-reloc; + +- display-timings { +- native-mode = <&timing_vga>; +- +- /* Standard VGA timing */ +- timing_vga: 640x480 { +- u-boot,dm-pre-reloc; +- clock-frequency = <25175000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <48>; +- hfront-porch = <16>; +- vback-porch = <33>; +- vfront-porch = <10>; +- hsync-len = <96>; +- vsync-len = <2>; +- +- de-active = <1>; +- hsync-active = <0>; +- vsync-active = <0>; +- pixelclk-active = <0>; ++ display0: display0 { ++ bits-per-pixel = <18>; ++ bus-width = <24>; ++ status = "okay"; ++ ++ display-timings { ++ native-mode = <&timing_vga>; ++ timing_vga: 640x480 { ++ u-boot,dm-pre-reloc; ++ clock-frequency = <25175000>; ++ hactive = <640>; ++ vactive = <480>; ++ hback-porch = <48>; ++ hfront-porch = <16>; ++ vback-porch = <33>; ++ vfront-porch = <10>; ++ hsync-len = <96>; ++ vsync-len = <2>; ++ ++ de-active = <1>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ pixelclk-active = <0>; ++ }; + }; + }; + }; +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0002-misc-imx8-add-sc_misc_get_temp.patch b/recipes-bsp/u-boot-mainline/files/0002-misc-imx8-add-sc_misc_get_temp.patch new file mode 100644 index 0000000..da7e19d --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0002-misc-imx8-add-sc_misc_get_temp.patch @@ -0,0 +1,80 @@ +From d8ee868c17170e39d36e61fb0bb77def1786724b Mon Sep 17 00:00:00 2001 +From: Peng Fan +Date: Sun, 5 May 2019 13:23:51 +0000 +Subject: [PATCH 02/15] misc: imx8: add sc_misc_get_temp + +Add sc_misc_get_temp to support get temperature + +Signed-off-by: Peng Fan +--- + arch/arm/include/asm/arch-imx8/sci/sci.h | 2 ++ + arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 1 + + drivers/misc/imx8/scu_api.c | 28 +++++++++++++++++++++++ + 3 files changed, 31 insertions(+) + +diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h +index 97377697f0..901b90d705 100644 +--- a/arch/arm/include/asm/arch-imx8/sci/sci.h ++++ b/arch/arm/include/asm/arch-imx8/sci/sci.h +@@ -72,6 +72,8 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); + void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); + void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); + int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); ++int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, ++ s16 *celsius, s8 *tenths); + + /* RM API */ + sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); +diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h +index 5d17b553d7..3629eb68d7 100644 +--- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h ++++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h +@@ -26,5 +26,6 @@ + #define SC_MISC_REL_CONTAINER 2U /* Release container */ + + typedef u8 sc_misc_boot_status_t; ++typedef u8 sc_misc_temp_t; + + #endif /* SC_MISC_API_H */ +diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c +index d9c4d5d784..031bc0048b 100644 +--- a/drivers/misc/imx8/scu_api.c ++++ b/drivers/misc/imx8/scu_api.c +@@ -273,6 +273,34 @@ int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val) + return 0; + } + ++int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, ++ s16 *celsius, s8 *tenths) ++{ ++ struct udevice *dev = gd->arch.scu_dev; ++ int size = sizeof(struct sc_rpc_msg_s); ++ struct sc_rpc_msg_s msg; ++ int ret; ++ ++ RPC_VER(&msg) = SC_RPC_VERSION; ++ RPC_SVC(&msg) = (u8)SC_RPC_SVC_MISC; ++ RPC_FUNC(&msg) = (u8)MISC_FUNC_GET_TEMP; ++ RPC_U16(&msg, 0U) = (u16)resource; ++ RPC_U8(&msg, 2U) = (u8)temp; ++ RPC_SIZE(&msg) = 2U; ++ ++ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); ++ if (ret < 0) ++ return ret; ++ ++ if (celsius) ++ *celsius = RPC_I16(&msg, 0U); ++ ++ if (tenths) ++ *tenths = RPC_I8(&msg, 2U); ++ ++ return 0; ++} ++ + /* RM */ + sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) + { +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0002-video-fsl_dcu_fb-refactor-init-functions.patch b/recipes-bsp/u-boot-mainline/files/0002-video-fsl_dcu_fb-refactor-init-functions.patch new file mode 100644 index 0000000..c9ff05e --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0002-video-fsl_dcu_fb-refactor-init-functions.patch @@ -0,0 +1,288 @@ +From 8882f63a9c5d15e54587fa3ab791759584049098 Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Mon, 10 Jun 2019 14:47:49 +0300 +Subject: [PATCH 2/7] video: fsl_dcu_fb: refactor init functions + +Move dcu-related code to fsl_dcu_probe_common, keep in video_hw_init() +only legacy video stack (filling GraphicPanel struct etc.). + +Add wrappers for all init functions, that will let to provide +struct fb_info as an additional param (needed for further moving it from +the global scope to driver private data struct in DM converted driver). + +Signed-off-by: Igor Opaniuk +--- + board/freescale/ls1021aqds/dcu.c | 6 ++- + board/toradex/colibri_vf/dcu.c | 6 ++- + drivers/video/fsl_dcu_fb.c | 107 ++++++++++++++++++++++----------------- + include/fsl_dcu_fb.h | 12 +++-- + 4 files changed, 77 insertions(+), 54 deletions(-) + +diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c +index 14855ea1d9..c4eac5e302 100644 +--- a/board/freescale/ls1021aqds/dcu.c ++++ b/board/freescale/ls1021aqds/dcu.c +@@ -39,7 +39,9 @@ unsigned int dcu_set_pixel_clock(unsigned int pixclock) + return div; + } + +-int platform_dcu_init(unsigned int xres, unsigned int yres, ++int platform_dcu_init(struct fb_info *fbinfo, ++ unsigned int xres, ++ unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode) + { +@@ -85,7 +87,7 @@ int platform_dcu_init(unsigned int xres, unsigned int yres, + printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); + + pixel_format = 32; +- fsl_dcu_init(xres, yres, pixel_format); ++ fsl_dcu_init(fbinfo, xres, yres, pixel_format); + + return 0; + } +diff --git a/board/toradex/colibri_vf/dcu.c b/board/toradex/colibri_vf/dcu.c +index c36e90cd22..c688ed79ff 100644 +--- a/board/toradex/colibri_vf/dcu.c ++++ b/board/toradex/colibri_vf/dcu.c +@@ -26,11 +26,13 @@ unsigned int dcu_set_pixel_clock(unsigned int pixclock) + return div; + } + +-int platform_dcu_init(unsigned int xres, unsigned int yres, ++int platform_dcu_init(struct fb_info *fbinfo, ++ unsigned int xres, ++ unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode) + { +- fsl_dcu_init(xres, yres, 32); ++ fsl_dcu_init(fbinfo, xres, yres, 32); + + return 0; + } +diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c +index 9f6e7f83b0..f789ec597d 100644 +--- a/drivers/video/fsl_dcu_fb.c ++++ b/drivers/video/fsl_dcu_fb.c +@@ -1,6 +1,7 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2014 Freescale Semiconductor, Inc. ++ * Copyright 2019 Toradex AG + * + * FSL DCU Framebuffer driver + */ +@@ -240,20 +241,22 @@ static void reset_total_layers(void) + } + } + +-static int layer_ctrldesc_init(int index, u32 pixel_format) ++static int layer_ctrldesc_init(struct fb_info fbinfo, ++ int index, u32 pixel_format) + { + struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; + unsigned int bpp = BPP_24_RGB888; + + dcu_write32(®s->ctrldescl[index][0], +- DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) | +- DCU_CTRLDESCLN_1_WIDTH(info.var.xres)); ++ DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) | ++ DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres)); + + dcu_write32(®s->ctrldescl[index][1], + DCU_CTRLDESCLN_2_POSY(0) | + DCU_CTRLDESCLN_2_POSX(0)); + +- dcu_write32(®s->ctrldescl[index][2], (unsigned int)info.screen_base); ++ dcu_write32(®s->ctrldescl[index][2], ++ (unsigned int)fbinfo.screen_base); + + switch (pixel_format) { + case 16: +@@ -294,42 +297,42 @@ static int layer_ctrldesc_init(int index, u32 pixel_format) + return 0; + } + +-int fsl_dcu_init(unsigned int xres, unsigned int yres, +- unsigned int pixel_format) ++int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres, ++ unsigned int yres, unsigned int pixel_format) + { + struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; + unsigned int div, mode; + +- info.screen_size = +- info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8); ++ fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres * ++ (fbinfo->var.bits_per_pixel / 8); + +- if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) { +- info.screen_size = 0; ++ if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) { ++ fbinfo->screen_size = 0; + return -ENOMEM; + } + + /* Reserve framebuffer at the end of memory */ + gd->fb_base = gd->bd->bi_dram[0].start + +- gd->bd->bi_dram[0].size - info.screen_size; +- info.screen_base = (char *)gd->fb_base; ++ gd->bd->bi_dram[0].size - fbinfo->screen_size; ++ fbinfo->screen_base = (char *)gd->fb_base; + +- memset(info.screen_base, 0, info.screen_size); ++ memset(fbinfo->screen_base, 0, fbinfo->screen_size); + + reset_total_layers(); + + dcu_write32(®s->disp_size, +- DCU_DISP_SIZE_DELTA_Y(info.var.yres) | +- DCU_DISP_SIZE_DELTA_X(info.var.xres / 16)); ++ DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) | ++ DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16)); + + dcu_write32(®s->hsyn_para, +- DCU_HSYN_PARA_BP(info.var.left_margin) | +- DCU_HSYN_PARA_PW(info.var.hsync_len) | +- DCU_HSYN_PARA_FP(info.var.right_margin)); ++ DCU_HSYN_PARA_BP(fbinfo->var.left_margin) | ++ DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) | ++ DCU_HSYN_PARA_FP(fbinfo->var.right_margin)); + + dcu_write32(®s->vsyn_para, +- DCU_VSYN_PARA_BP(info.var.upper_margin) | +- DCU_VSYN_PARA_PW(info.var.vsync_len) | +- DCU_VSYN_PARA_FP(info.var.lower_margin)); ++ DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) | ++ DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) | ++ DCU_VSYN_PARA_FP(fbinfo->var.lower_margin)); + + dcu_write32(®s->synpol, + DCU_SYN_POL_INV_PXCK_FALL | +@@ -352,9 +355,9 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, + mode = dcu_read32(®s->mode); + dcu_write32(®s->mode, mode | DCU_MODE_NORMAL); + +- layer_ctrldesc_init(0, pixel_format); ++ layer_ctrldesc_init(*fbinfo, 0, pixel_format); + +- div = dcu_set_pixel_clock(info.var.pixclock); ++ div = dcu_set_pixel_clock(fbinfo->var.pixclock); + dcu_write32(®s->div_ratio, (div - 1)); + + dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); +@@ -367,24 +370,26 @@ ulong board_get_usable_ram_top(ulong total_size) + return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB; + } + +-void *video_hw_init(void) ++int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x, ++ unsigned int *win_y) + { +- static GraphicDevice ctfb; + const char *options; + unsigned int depth = 0, freq = 0; ++ + struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272; + +- if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq, ++ if (!video_get_video_mode(win_x, win_y, &depth, &freq, + &options)) +- return NULL; ++ return -EINVAL; + + /* Find the monitor port, which is a required option */ + if (!options) +- return NULL; ++ return -EINVAL; ++ + if (strncmp(options, "monitor=", 8) != 0) +- return NULL; ++ return -EINVAL; + +- switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) { ++ switch (RESOLUTION(*win_x, *win_y)) { + case RESOLUTION(480, 272): + fsl_dcu_mode_db = &fsl_dcu_mode_480_272; + break; +@@ -402,25 +407,33 @@ void *video_hw_init(void) + break; + default: + printf("unsupported resolution %ux%u\n", +- ctfb.winSizeX, ctfb.winSizeY); ++ *win_x, *win_y); + } + +- info.var.xres = fsl_dcu_mode_db->xres; +- info.var.yres = fsl_dcu_mode_db->yres; +- info.var.bits_per_pixel = 32; +- info.var.pixclock = fsl_dcu_mode_db->pixclock; +- info.var.left_margin = fsl_dcu_mode_db->left_margin; +- info.var.right_margin = fsl_dcu_mode_db->right_margin; +- info.var.upper_margin = fsl_dcu_mode_db->upper_margin; +- info.var.lower_margin = fsl_dcu_mode_db->lower_margin; +- info.var.hsync_len = fsl_dcu_mode_db->hsync_len; +- info.var.vsync_len = fsl_dcu_mode_db->vsync_len; +- info.var.sync = fsl_dcu_mode_db->sync; +- info.var.vmode = fsl_dcu_mode_db->vmode; +- info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8; +- +- if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY, +- options + 8, fsl_dcu_mode_db) < 0) ++ fbinfo->var.xres = fsl_dcu_mode_db->xres; ++ fbinfo->var.yres = fsl_dcu_mode_db->yres; ++ fbinfo->var.bits_per_pixel = 32; ++ fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock; ++ fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin; ++ fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin; ++ fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin; ++ fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin; ++ fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len; ++ fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len; ++ fbinfo->var.sync = fsl_dcu_mode_db->sync; ++ fbinfo->var.vmode = fsl_dcu_mode_db->vmode; ++ fbinfo->fix.line_length = fbinfo->var.xres * ++ fbinfo->var.bits_per_pixel / 8; ++ ++ return platform_dcu_init(fbinfo, *win_x, *win_y, ++ options + 8, fsl_dcu_mode_db); ++} ++ ++void *video_hw_init(void) ++{ ++ static GraphicDevice ctfb; ++ ++ if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0) + return NULL; + + ctfb.frameAdrs = (unsigned int)info.screen_base; +diff --git a/include/fsl_dcu_fb.h b/include/fsl_dcu_fb.h +index 2dd5f54c3e..7a5347a924 100644 +--- a/include/fsl_dcu_fb.h ++++ b/include/fsl_dcu_fb.h +@@ -6,11 +6,17 @@ + */ + #include + +-int fsl_dcu_init(unsigned int xres, unsigned int yres, ++int fsl_dcu_init(struct fb_info *fbinfo, ++ unsigned int xres, ++ unsigned int yres, + unsigned int pixel_format); ++ + int fsl_dcu_fixedfb_setup(void *blob); + + /* Prototypes for external board-specific functions */ +-int platform_dcu_init(unsigned int xres, unsigned int yres, +- const char *port, struct fb_videomode *dcu_fb_videomode); ++int platform_dcu_init(struct fb_info *fbinfo, ++ unsigned int xres, ++ unsigned int yres, ++ const char *port, ++ struct fb_videomode *dcu_fb_videomode); + unsigned int dcu_set_pixel_clock(unsigned int pixclock); +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0003-configs-colibri_imx7-enable-DM_VIDEO.patch b/recipes-bsp/u-boot-mainline/files/0003-configs-colibri_imx7-enable-DM_VIDEO.patch new file mode 100644 index 0000000..740e4c6 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0003-configs-colibri_imx7-enable-DM_VIDEO.patch @@ -0,0 +1,27 @@ +From b566fdf72a80849ef0e98fc743b8222f21d0688c Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Wed, 19 Jun 2019 11:47:07 +0300 +Subject: [PATCH 3/6] configs: colibri_imx7: enable DM_VIDEO + +Enable DM_VIDEO support for Colibri iMX7 NAND version. + +Signed-off-by: Igor Opaniuk +--- + configs/colibri_imx7_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig +index 5b0d091569..686ff235d8 100644 +--- a/configs/colibri_imx7_defconfig ++++ b/configs/colibri_imx7_defconfig +@@ -73,6 +73,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 + CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 + CONFIG_CI_UDC=y + CONFIG_USB_GADGET_DOWNLOAD=y +-CONFIG_VIDEO=y ++CONFIG_DM_VIDEO=y + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_FDT_FIXUP_PARTITIONS=y +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0003-thermal-add-i.MX8-thermal-driver.patch b/recipes-bsp/u-boot-mainline/files/0003-thermal-add-i.MX8-thermal-driver.patch new file mode 100644 index 0000000..93c7bbd --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0003-thermal-add-i.MX8-thermal-driver.patch @@ -0,0 +1,257 @@ +From 9151a1401de39c05cbad1270517c31c41bfb576b Mon Sep 17 00:00:00 2001 +From: Peng Fan +Date: Sun, 5 May 2019 13:23:54 +0000 +Subject: [PATCH 03/15] thermal: add i.MX8 thermal driver + +Add i.MX8 thermal driver to support get temperature from SCU. + +Signed-off-by: Peng Fan +--- + drivers/thermal/Kconfig | 9 ++ + drivers/thermal/Makefile | 1 + + drivers/thermal/imx_scu_thermal.c | 203 ++++++++++++++++++++++++++++++++++++++ + 3 files changed, 213 insertions(+) + create mode 100644 drivers/thermal/imx_scu_thermal.c + +diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig +index a71b9be5fb..bdf8dc6fef 100644 +--- a/drivers/thermal/Kconfig ++++ b/drivers/thermal/Kconfig +@@ -17,6 +17,15 @@ config IMX_THERMAL + cpufreq is used as the cooling device to throttle CPUs when the + passive trip is crossed. + ++config IMX_SCU_THERMAL ++ bool "Temperature sensor driver for NXP i.MX8" ++ depends on ARCH_IMX8 ++ help ++ Support for Temperature sensors on NXP i.MX8. ++ It supports one critical trip point and one passive trip point. The ++ boot is hold to the cool device to throttle CPUs when the passive ++ trip is crossed ++ + config TI_DRA7_THERMAL + bool "Temperature sensor driver for TI dra7xx SOCs" + help +diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile +index cc75e387e4..ef2929d180 100644 +--- a/drivers/thermal/Makefile ++++ b/drivers/thermal/Makefile +@@ -5,4 +5,5 @@ + + obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o + obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o ++obj-$(CONFIG_IMX_SCU_THERMAL) += imx_scu_thermal.o + obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o +diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c +new file mode 100644 +index 0000000000..7e17377b69 +--- /dev/null ++++ b/drivers/thermal/imx_scu_thermal.c +@@ -0,0 +1,203 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright 2019 NXP ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++struct imx_sc_thermal_plat { ++ int critical; ++ int alert; ++ int polling_delay; ++ int id; ++ bool zone_node; ++}; ++ ++static int read_temperature(struct udevice *dev, int *temp) ++{ ++ s16 celsius; ++ s8 tenths; ++ int ret; ++ ++ sc_rsrc_t *sensor_rsrc = (sc_rsrc_t *)dev_get_driver_data(dev); ++ ++ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); ++ ++ if (!temp) ++ return -EINVAL; ++ ++ ret = sc_misc_get_temp(-1, sensor_rsrc[pdata->id], SC_C_TEMP, ++ &celsius, &tenths); ++ if (ret) { ++ printf("Error: get temperature failed! (error = %d)\n", ret); ++ return ret; ++ } ++ ++ *temp = celsius * 1000 + tenths * 100; ++ ++ return 0; ++} ++ ++int imx_sc_thermal_get_temp(struct udevice *dev, int *temp) ++{ ++ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); ++ int cpu_temp = 0; ++ int ret; ++ ++ ret = read_temperature(dev, &cpu_temp); ++ if (ret) ++ return ret; ++ ++ while (cpu_temp >= pdata->alert) { ++ printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)", ++ cpu_temp, pdata->alert, pdata->critical); ++ puts(" waiting...\n"); ++ mdelay(pdata->polling_delay); ++ ret = read_temperature(dev, &cpu_temp); ++ if (ret) ++ return ret; ++ } ++ ++ *temp = cpu_temp / 1000; ++ ++ return 0; ++} ++ ++static const struct dm_thermal_ops imx_sc_thermal_ops = { ++ .get_temp = imx_sc_thermal_get_temp, ++}; ++ ++static int imx_sc_thermal_probe(struct udevice *dev) ++{ ++ debug("%s dev name %s\n", __func__, dev->name); ++ return 0; ++} ++ ++static int imx_sc_thermal_bind(struct udevice *dev) ++{ ++ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); ++ int reg, ret; ++ int offset; ++ const char *name; ++ const void *prop; ++ ++ debug("%s dev name %s\n", __func__, dev->name); ++ ++ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "compatible", ++ NULL); ++ if (!prop) ++ return 0; ++ ++ pdata->zone_node = 1; ++ ++ reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "tsens-num", 0); ++ if (reg == 0) { ++ printf("%s: no temp sensor number provided!\n", __func__); ++ return -EINVAL; ++ } ++ ++ offset = fdt_subnode_offset(gd->fdt_blob, 0, "thermal-zones"); ++ fdt_for_each_subnode(offset, gd->fdt_blob, offset) { ++ /* Bind the subnode to this driver */ ++ name = fdt_get_name(gd->fdt_blob, offset, NULL); ++ ++ ret = device_bind_with_driver_data(dev, dev->driver, name, ++ dev->driver_data, ++ offset_to_ofnode(offset), ++ NULL); ++ if (ret) ++ printf("Error binding driver '%s': %d\n", ++ dev->driver->name, ret); ++ } ++ return 0; ++} ++ ++static int imx_sc_thermal_ofdata_to_platdata(struct udevice *dev) ++{ ++ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); ++ struct fdtdec_phandle_args args; ++ const char *type; ++ int ret; ++ int trips_np; ++ ++ debug("%s dev name %s\n", __func__, dev->name); ++ ++ if (pdata->zone_node) ++ return 0; ++ ++ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev), ++ "thermal-sensors", ++ "#thermal-sensor-cells", ++ 0, 0, &args); ++ if (ret) ++ return ret; ++ ++ if (args.node != dev_of_offset(dev->parent)) ++ return -EFAULT; ++ ++ if (args.args_count >= 1) ++ pdata->id = args.args[0]; ++ else ++ pdata->id = 0; ++ ++ debug("args.args_count %d, id %d\n", args.args_count, pdata->id); ++ ++ pdata->polling_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), ++ "polling-delay", 1000); ++ ++ trips_np = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev), ++ "trips"); ++ fdt_for_each_subnode(trips_np, gd->fdt_blob, trips_np) { ++ type = fdt_getprop(gd->fdt_blob, trips_np, "type", NULL); ++ if (type) { ++ if (strcmp(type, "critical") == 0) { ++ pdata->critical = fdtdec_get_int(gd->fdt_blob, ++ trips_np, ++ "temperature", ++ 85); ++ } else if (strcmp(type, "passive") == 0) { ++ pdata->alert = fdtdec_get_int(gd->fdt_blob, ++ trips_np, ++ "temperature", ++ 80); ++ } ++ } ++ } ++ ++ debug("id %d polling_delay %d, critical %d, alert %d\n", pdata->id, ++ pdata->polling_delay, pdata->critical, pdata->alert); ++ ++ return 0; ++} ++ ++static const sc_rsrc_t imx8qxp_sensor_rsrc[] = { ++ SC_R_SYSTEM, SC_R_DRC_0, SC_R_PMIC_0, ++ SC_R_PMIC_1, SC_R_PMIC_2, ++}; ++ ++static const struct udevice_id imx_sc_thermal_ids[] = { ++ { .compatible = "nxp,imx8qxp-sc-tsens", .data = ++ (ulong)&imx8qxp_sensor_rsrc, }, ++ { } ++}; ++ ++U_BOOT_DRIVER(imx_sc_thermal) = { ++ .name = "imx_sc_thermal", ++ .id = UCLASS_THERMAL, ++ .ops = &imx_sc_thermal_ops, ++ .of_match = imx_sc_thermal_ids, ++ .bind = imx_sc_thermal_bind, ++ .probe = imx_sc_thermal_probe, ++ .ofdata_to_platdata = imx_sc_thermal_ofdata_to_platdata, ++ .platdata_auto_alloc_size = sizeof(struct imx_sc_thermal_plat), ++ .flags = DM_FLAG_PRE_RELOC, ++}; +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0003-usb-limit-USB_MAX_XFER_BLK-to-256.patch b/recipes-bsp/u-boot-mainline/files/0003-usb-limit-USB_MAX_XFER_BLK-to-256.patch deleted file mode 100644 index 58526af..0000000 --- a/recipes-bsp/u-boot-mainline/files/0003-usb-limit-USB_MAX_XFER_BLK-to-256.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 70e00d1f20c331a1da991abc7b36f0f6a20751dc Mon Sep 17 00:00:00 2001 -From: Peng Fan -Date: Mon, 6 Jun 2016 13:53:43 +0800 -Subject: [PATCH 03/19] usb: limit USB_MAX_XFER_BLK to 256 - -For Some USB mass storage devices, such as: -" - - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA - - Class: (from Interface) Mass Storage - - PacketSize: 64 Configurations: 1 - - Vendor: 0x0930 Product 0x6545 Version 1.16 -" -When `usb read 0x80000000 0 0x2000`, we met -"EHCI timed out on TD - token=0x80008d80". - -The devices does not support scsi VPD page, we are not able -to get the maximum transfer length for READ(10)/WRITE(10). - -So we limit this to 256 blocks as READ(6). - -Signed-off-by: Peng Fan -Acked-by: Marcel Ziswiler -(cherry picked from commit df0052575b2bc9d66ae73584768e1a457ed5d914) - -Series-to: u-boot@lists.denx.de - -Series-prefix: RFC - -Series-version: 3 - -Series-changes: 2 -- Fixed spelling in comment as suggested by Igor. - -Series-changes: 3 -- Drop the reference to the NXP internal MLK-xxx tracking number as - suggested by Peng. - -Commit-notes: -This comes from NXP's downstream and has proven to tremendously improve -the situation with those odd USB mass storage aka memory sticks. This is -why I post it here asking whether or not this may be something -benefiting more people. Any feedback and suggestions are welcome. -END ---- - common/usb_storage.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/common/usb_storage.c b/common/usb_storage.c -index 8c889bb1a6..4e284645f5 100644 ---- a/common/usb_storage.c -+++ b/common/usb_storage.c -@@ -949,7 +949,11 @@ static void usb_stor_set_max_xfer_blk(struct usb_device *udev, - * there is enough free heap space left, but the SCSI READ(10) and - * WRITE(10) commands are limited to 65535 blocks. - */ -- blk = USHRT_MAX; -+ /* -+ * Some USB mass storage devices have issues, limiting this to 256 -+ * fixes this. -+ */ -+ blk = 256; - #else - blk = 20; - #endif --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0003-video-fsl_dcu_fb-add-DM_VIDEO-support.patch b/recipes-bsp/u-boot-mainline/files/0003-video-fsl_dcu_fb-add-DM_VIDEO-support.patch new file mode 100644 index 0000000..200bd27 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0003-video-fsl_dcu_fb-add-DM_VIDEO-support.patch @@ -0,0 +1,229 @@ +From da8fee6e8e96c0737d842f6a3f988670ca35bb83 Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Mon, 10 Jun 2019 14:47:50 +0300 +Subject: [PATCH 3/7] video: fsl_dcu_fb: add DM_VIDEO support + +Extend the driver to build with DM_VIDEO enabled. DTS files +must additionally include 'u-boot,dm-pre-reloc' property in +soc and child nodes to enable driver binding to fsl_dcu_fb device. + +Currently display timings aren't obtained from DT. + +Signed-off-by: Igor Opaniuk +--- + board/toradex/colibri_vf/colibri_vf.c | 4 +- + drivers/video/Kconfig | 2 +- + drivers/video/fsl_dcu_fb.c | 112 ++++++++++++++++++++++++++++------ + 3 files changed, 97 insertions(+), 21 deletions(-) + +diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c +index 9d63fbf3bd..dad754b31f 100644 +--- a/board/toradex/colibri_vf/colibri_vf.c ++++ b/board/toradex/colibri_vf/colibri_vf.c +@@ -430,7 +430,9 @@ int checkboard(void) + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) + int ft_board_setup(void *blob, bd_t *bd) + { ++#ifndef CONFIG_DM_VIDEO + int ret = 0; ++#endif + #ifdef CONFIG_FDT_FIXUP_PARTITIONS + static const struct node_info nodes[] = { + { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */ +@@ -440,7 +442,7 @@ int ft_board_setup(void *blob, bd_t *bd) + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + #endif +-#ifdef CONFIG_VIDEO_FSL_DCU_FB ++#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO) + ret = fsl_dcu_fixedfb_setup(blob); + if (ret) + return ret; +diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig +index a40df01500..f6f00c2830 100644 +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -484,7 +484,7 @@ config VIDEO_IVYBRIDGE_IGD + + config VIDEO_FSL_DCU_FB + bool "Enable Freescale Display Control Unit" +- depends on VIDEO ++ depends on VIDEO || DM_VIDEO + help + This enables support for Freescale Display Control Unit (DCU4) + module found on Freescale Vybrid and QorIQ family of SoCs. +diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c +index f789ec597d..add64b85b5 100644 +--- a/drivers/video/fsl_dcu_fb.c ++++ b/drivers/video/fsl_dcu_fb.c +@@ -8,10 +8,12 @@ + + #include + #include ++#include + #include + #include + #include + #include ++#include + #include + #include "videomodes.h" + +@@ -219,8 +221,6 @@ struct dcu_reg { + u32 ctrldescl[DCU_LAYER_MAX_NUM][16]; + }; + +-static struct fb_info info; +- + static void reset_total_layers(void) + { + struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; +@@ -302,7 +302,11 @@ int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres, + { + struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; + unsigned int div, mode; +- ++/* ++ * When DM_VIDEO is enabled reservation of framebuffer is done ++ * in advance during bind() call. ++ */ ++#if !CONFIG_IS_ENABLED(DM_VIDEO) + fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres * + (fbinfo->var.bits_per_pixel / 8); + +@@ -310,13 +314,13 @@ int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres, + fbinfo->screen_size = 0; + return -ENOMEM; + } +- + /* Reserve framebuffer at the end of memory */ + gd->fb_base = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - fbinfo->screen_size; + fbinfo->screen_base = (char *)gd->fb_base; + + memset(fbinfo->screen_base, 0, fbinfo->screen_size); ++#endif + + reset_total_layers(); + +@@ -429,6 +433,32 @@ int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x, + options + 8, fsl_dcu_mode_db); + } + ++#ifndef CONFIG_DM_VIDEO ++static struct fb_info info; ++ ++#if defined(CONFIG_OF_BOARD_SETUP) ++int fsl_dcu_fixedfb_setup(void *blob) ++{ ++ u64 start, size; ++ int ret; ++ ++ start = gd->bd->bi_dram[0].start; ++ size = gd->bd->bi_dram[0].size - info.screen_size; ++ ++ /* ++ * Align size on section size (1 MiB). ++ */ ++ size &= 0xfff00000; ++ ret = fdt_fixup_memory_banks(blob, &start, &size, 1); ++ if (ret) { ++ eprintf("Cannot setup fb: Error reserving memory\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++#endif ++ + void *video_hw_init(void) + { + static GraphicDevice ctfb; +@@ -448,25 +478,69 @@ void *video_hw_init(void) + return &ctfb; + } + +-#if defined(CONFIG_OF_BOARD_SETUP) +-int fsl_dcu_fixedfb_setup(void *blob) ++#else /* ifndef CONFIG_DM_VIDEO */ ++ ++static int fsl_dcu_video_probe(struct udevice *dev) + { +- u64 start, size; +- int ret; ++ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); ++ struct video_priv *uc_priv = dev_get_uclass_priv(dev); ++ struct fb_info fbinfo = { 0 }; ++ unsigned int win_x; ++ unsigned int win_y; ++ u32 fb_start, fb_end; ++ int ret = 0; ++ ++ fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); ++ fb_end = plat->base + plat->size; ++ fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); ++ ++ fbinfo.screen_base = (char *)fb_start; ++ fbinfo.screen_size = plat->size; ++ ++ ret = fsl_probe_common(&fbinfo, &win_x, &win_y); ++ if (ret < 0) ++ return ret; + +- start = gd->bd->bi_dram[0].start; +- size = gd->bd->bi_dram[0].size - info.screen_size; ++ uc_priv->bpix = VIDEO_BPP32; ++ uc_priv->xsize = win_x; ++ uc_priv->ysize = win_y; + +- /* +- * Align size on section size (1 MiB). +- */ +- size &= 0xfff00000; +- ret = fdt_fixup_memory_banks(blob, &start, &size, 1); +- if (ret) { +- eprintf("Cannot setup fb: Error reserving memory\n"); ++ /* Enable dcache for the frame buffer */ ++ mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, ++ DCACHE_WRITEBACK); ++ video_set_flush_dcache(dev, true); ++ return ret; ++} ++ ++static int fsl_dcu_video_bind(struct udevice *dev) ++{ ++ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); ++ unsigned int win_x; ++ unsigned int win_y; ++ unsigned int depth = 0, freq = 0; ++ const char *options; ++ int ret = 0; ++ ++ ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options); ++ if (ret < 0) + return ret; +- } ++ ++ plat->size = win_x * win_y * 32; + + return 0; + } +-#endif ++ ++static const struct udevice_id fsl_dcu_video_ids[] = { ++ { .compatible = "fsl,vf610-dcu" }, ++ { /* sentinel */ } ++}; ++ ++U_BOOT_DRIVER(fsl_dcu_video) = { ++ .name = "fsl_dcu_video", ++ .id = UCLASS_VIDEO, ++ .of_match = fsl_dcu_video_ids, ++ .bind = fsl_dcu_video_bind, ++ .probe = fsl_dcu_video_probe, ++ .flags = DM_FLAG_PRE_RELOC, ++}; ++#endif /* ifndef CONFIG_DM_VIDEO */ +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0004-ARM-dts-colibri_vf-Add-dcu0-node.patch b/recipes-bsp/u-boot-mainline/files/0004-ARM-dts-colibri_vf-Add-dcu0-node.patch new file mode 100644 index 0000000..493f562 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0004-ARM-dts-colibri_vf-Add-dcu0-node.patch @@ -0,0 +1,68 @@ +From e3a6bd1f14d6115c8c4a690dce9f7756f3c0dbda Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Mon, 10 Jun 2019 14:47:51 +0300 +Subject: [PATCH 4/7] ARM: dts: colibri_vf: Add dcu0 node + +Add dumb node for NXP Display Control Unit0(DCU), which permits DM_ENABLED +converted driver to be probed. Currently no display timings are provided +in this node. + +Signed-off-by: Igor Opaniuk +--- + arch/arm/dts/vf-colibri-u-boot.dtsi | 4 ++++ + arch/arm/dts/vf-colibri.dtsi | 5 +++++ + arch/arm/dts/vf.dtsi | 6 ++++++ + 3 files changed, 15 insertions(+) + +diff --git a/arch/arm/dts/vf-colibri-u-boot.dtsi b/arch/arm/dts/vf-colibri-u-boot.dtsi +index db86739805..2294ee9551 100644 +--- a/arch/arm/dts/vf-colibri-u-boot.dtsi ++++ b/arch/arm/dts/vf-colibri-u-boot.dtsi +@@ -21,3 +21,7 @@ + &uart0 { + u-boot,dm-pre-reloc; + }; ++ ++&dcu0 { ++ u-boot,dm-pre-reloc; ++}; +diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi +index 91ca4e4ddd..9de4b28e87 100644 +--- a/arch/arm/dts/vf-colibri.dtsi ++++ b/arch/arm/dts/vf-colibri.dtsi +@@ -14,6 +14,7 @@ + + aliases { + usb0 = &ehci0; /* required for ums */ ++ display1 = &dcu0; + }; + + reg_usbh_vbus: regulator-usbh-vbus { +@@ -241,3 +242,7 @@ + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; + }; ++ ++&dcu0 { ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi +index 5e3b2c5b9d..5f69d0fd6e 100644 +--- a/arch/arm/dts/vf.dtsi ++++ b/arch/arm/dts/vf.dtsi +@@ -145,6 +145,12 @@ + #gpio-cells = <2>; + }; + ++ dcu0: dcu@40058000 { ++ compatible = "fsl,vf610-dcu"; ++ reg = <0x40058000 0x1200>; ++ status = "disabled"; ++ }; ++ + ehci0: ehci@40034000 { + compatible = "fsl,vf610-usb"; + reg = <0x40034000 0x800>; +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0004-apalis_imx6-add-device-tree-to-makefile.patch b/recipes-bsp/u-boot-mainline/files/0004-apalis_imx6-add-device-tree-to-makefile.patch deleted file mode 100644 index 7f285fd..0000000 --- a/recipes-bsp/u-boot-mainline/files/0004-apalis_imx6-add-device-tree-to-makefile.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 949abc726eab7477cee095d7696eca57247c8572 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Sun, 24 Mar 2019 03:31:04 +0100 -Subject: [PATCH 04/19] apalis_imx6: add device tree to makefile - -Add device tree to Makefile to avoid newly introduced error: - -Device Tree Source is not correctly specified. -Please define 'CONFIG_DEFAULT_DEVICE_TREE' -or build with 'DEVICE_TREE=' argument - -make[1]: *** [dts/Makefile:28: arch/arm/dts/imx6-apalis.dtb] Error 1 -make: *** [Makefile:1009: dts/dt.dtb] Error 2 - -Signed-off-by: Marcel Ziswiler -Reviewed-by: Igor Opaniuk - -Series-to: u-boot@lists.denx.de -Series-cc: Stefano Babic - -Series-version: 3 - -Series-changes: 2 -- Drop adding the colibri-imx6 device tree as Stefano already pulled v1 - 75992d0e7dfc ("apalis/colibri_imx6: add device trees to makefile") but - somehow dropped adding the apalis-imx6 one as well. - -Series-changes: 3 -- Added Igor's reviewed-by tag. ---- - arch/arm/dts/Makefile | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index dfa5b02958..e56a39e0b1 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -561,6 +561,7 @@ dtb-$(CONFIG_MX6ULL) += \ - imx6ull-dart-6ul.dtb - - dtb-$(CONFIG_ARCH_MX6) += \ -+ imx6-apalis.dtb \ - imx6-colibri.dtb - - dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0004-colibri-imx6ull-support-building-with-DM_VIDEO-y.patch b/recipes-bsp/u-boot-mainline/files/0004-colibri-imx6ull-support-building-with-DM_VIDEO-y.patch new file mode 100644 index 0000000..c3014fa --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0004-colibri-imx6ull-support-building-with-DM_VIDEO-y.patch @@ -0,0 +1,44 @@ +From 501c39b579c901989d6ef6f4463bb5ea1572fa09 Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Wed, 19 Jun 2019 11:47:08 +0300 +Subject: [PATCH 4/6] colibri-imx6ull: support building with DM_VIDEO=y + +1. This fixes linking issues when building with DM_VIDEO enabled mxsfb +driver. +2. Provide proper defines for both VIDEO=y and DM_VIDEO=y. + +Signed-off-by: Igor Opaniuk +--- + arch/arm/mach-imx/mx6/soc.c | 2 +- + include/configs/colibri-imx6ull.h | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c +index e80f1d484b..86a9eeba0c 100644 +--- a/arch/arm/mach-imx/mx6/soc.c ++++ b/arch/arm/mach-imx/mx6/soc.c +@@ -549,7 +549,7 @@ const struct boot_mode soc_boot_modes[] = { + void reset_misc(void) + { + #ifndef CONFIG_SPL_BUILD +-#ifdef CONFIG_VIDEO_MXS ++#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO) + lcdif_power_down(); + #endif + #endif +diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h +index b221e118fa..37bd78ea2e 100644 +--- a/include/configs/colibri-imx6ull.h ++++ b/include/configs/colibri-imx6ull.h +@@ -172,7 +172,7 @@ + #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M + #define DFU_DEFAULT_POLL_TIMEOUT 300 + +-#ifdef CONFIG_VIDEO ++#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) + #define CONFIG_VIDEO_MXS + #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR + #define CONFIG_VIDEO_LOGO +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0004-imx-imx8dx-qxp-enable-thermal.patch b/recipes-bsp/u-boot-mainline/files/0004-imx-imx8dx-qxp-enable-thermal.patch new file mode 100644 index 0000000..0b6e4f2 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0004-imx-imx8dx-qxp-enable-thermal.patch @@ -0,0 +1,103 @@ +From cdd878eee2db385e97ffa4dd11d9dce77e44c615 Mon Sep 17 00:00:00 2001 +From: Peng Fan +Date: Sun, 5 May 2019 13:24:00 +0000 +Subject: [PATCH 04/15] imx: imx8dx/qxp: enable thermal + +Add thermal dts node +Enable thermal in defconfig + +Signed-off-by: Peng Fan +--- + arch/arm/dts/fsl-imx8dx.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++++ + configs/imx8qxp_mek_defconfig | 2 ++ + 2 files changed, 58 insertions(+) + +diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi +index 715abb413d..4fc87a9fc8 100644 +--- a/arch/arm/dts/fsl-imx8dx.dtsi ++++ b/arch/arm/dts/fsl-imx8dx.dtsi +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + + / { + model = "Freescale i.MX8DX"; +@@ -543,6 +544,61 @@ + power-domains = <&pd_conn_enet1>; + status = "disabled"; + }; ++ ++ tsens: thermal-sensor { ++ compatible = "nxp,imx8qxp-sc-tsens"; ++ /* number of the temp sensor on the chip */ ++ tsens-num = <2>; ++ #thermal-sensor-cells = <1>; ++ }; ++ ++ thermal_zones: thermal-zones { ++ /* cpu thermal */ ++ cpu-thermal0 { ++ polling-delay-passive = <250>; ++ polling-delay = <2000>; ++ /*the slope and offset of the temp sensor */ ++ thermal-sensors = <&tsens 0>; ++ trips { ++ cpu_alert0: trip0 { ++ temperature = <107000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ cpu_crit0: trip1 { ++ temperature = <127000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert0>; ++ cooling-device = ++ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ drc-thermal0 { ++ polling-delay-passive = <250>; ++ polling-delay = <2000>; ++ thermal-sensors = <&tsens 1>; ++ status = "disabled"; ++ trips { ++ drc_alert0: trip0 { ++ temperature = <107000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ drc_crit0: trip1 { ++ temperature = <127000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; + }; + + &A35_0 { +diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig +index d735d34b8b..076f9acd6c 100644 +--- a/configs/imx8qxp_mek_defconfig ++++ b/configs/imx8qxp_mek_defconfig +@@ -77,5 +77,7 @@ CONFIG_DM_REGULATOR_GPIO=y + CONFIG_SPL_DM_REGULATOR_GPIO=y + CONFIG_DM_SERIAL=y + CONFIG_FSL_LPUART=y ++CONFIG_DM_THERMAL=y ++CONFIG_IMX_SCU_THERMAL=y + CONFIG_SPL_TINY_MEMSET=y + # CONFIG_EFI_LOADER is not set +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0005-ARM-dts-colibri-imx6ull-extend-lcdif-node.patch b/recipes-bsp/u-boot-mainline/files/0005-ARM-dts-colibri-imx6ull-extend-lcdif-node.patch new file mode 100644 index 0000000..79c4a2a --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0005-ARM-dts-colibri-imx6ull-extend-lcdif-node.patch @@ -0,0 +1,68 @@ +From ad78bd90ece3ddf909d243c77b6e2ebd2c8e9a40 Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Wed, 19 Jun 2019 11:47:09 +0300 +Subject: [PATCH 5/6] ARM: dts: colibri-imx6ull: extend lcdif node + +Provide proper display timings for lcdif node, used by mxsfb DM_VIDEO +enabled framebuffer driver. + +Signed-off-by: Igor Opaniuk +--- + arch/arm/dts/imx6ull-colibri.dts | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts +index 6c847ab792..262205ac5e 100644 +--- a/arch/arm/dts/imx6ull-colibri.dts ++++ b/arch/arm/dts/imx6ull-colibri.dts +@@ -12,8 +12,10 @@ + compatible = "toradex,colibri-imx6ull", "fsl,imx6ull"; + + aliases { ++ u-boot,dm-pre-reloc; + mmc0 = &usdhc1; + usb0 = &usbotg1; /* required for ums */ ++ display0 = &lcdif; + }; + + chosen { +@@ -156,6 +158,36 @@ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; ++ status = "okay"; ++ display = <&display0>; ++ u-boot,dm-pre-reloc; ++ ++ display0: display0 { ++ bits-per-pixel = <18>; ++ bus-width = <24>; ++ status = "okay"; ++ ++ display-timings { ++ native-mode = <&timing_vga>; ++ timing_vga: 640x480 { ++ u-boot,dm-pre-reloc; ++ clock-frequency = <25175000>; ++ hactive = <640>; ++ vactive = <480>; ++ hback-porch = <48>; ++ hfront-porch = <16>; ++ vback-porch = <33>; ++ vfront-porch = <10>; ++ hsync-len = <96>; ++ vsync-len = <2>; ++ ++ de-active = <1>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ pixelclk-active = <0>; ++ }; ++ }; ++ }; + }; + + /* PWM */ +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0005-colibri-imx6ull-fix-usb-host-mode.patch b/recipes-bsp/u-boot-mainline/files/0005-colibri-imx6ull-fix-usb-host-mode.patch deleted file mode 100644 index efbce00..0000000 --- a/recipes-bsp/u-boot-mainline/files/0005-colibri-imx6ull-fix-usb-host-mode.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 853800ced8e96bfd2b57851226e528e342ec30e7 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Thu, 28 Mar 2019 18:40:47 +0100 -Subject: [PATCH 05/19] colibri-imx6ull: fix usb host mode - -This fixes an issue with USB host mode. - -Signed-off-by: Marcel Ziswiler -Reviewed-by: Igor Opaniuk - -Series-to: u-boot@lists.denx.de -Series-cc: Stefano Babic - -Commit-notes: -I believe this is the one and only v3 change we missed as Stefano -pulled v2 instead. -END ---- - arch/arm/dts/imx6ull-colibri.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts -index 4196cbdf22..6c847ab792 100644 ---- a/arch/arm/dts/imx6ull-colibri.dts -+++ b/arch/arm/dts/imx6ull-colibri.dts -@@ -220,7 +220,7 @@ - - /* Colibri USBC */ - &usbotg1 { -- dr_mode = "otg"; -+ dr_mode = "host"; - srp-disable; - hnp-disable; - adp-disable; --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0005-colibri_vf-enable-DM_VIDEO.patch b/recipes-bsp/u-boot-mainline/files/0005-colibri_vf-enable-DM_VIDEO.patch new file mode 100644 index 0000000..5a31cc6 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0005-colibri_vf-enable-DM_VIDEO.patch @@ -0,0 +1,28 @@ +From 71ae7689ce50b0b66ead1f7ec28f99e78381b31d Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Mon, 10 Jun 2019 14:47:52 +0300 +Subject: [PATCH 5/7] colibri_vf: enable DM_VIDEO + +Enable DM_VIDEO for Colibri VF. + +Signed-off-by: Igor Opaniuk +--- + configs/colibri_vf_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig +index 75498fddb3..2b66d09901 100644 +--- a/configs/colibri_vf_defconfig ++++ b/configs/colibri_vf_defconfig +@@ -89,7 +89,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 + CONFIG_CI_UDC=y + CONFIG_USB_GADGET_DOWNLOAD=y + CONFIG_VIDEO_FSL_DCU_FB=y +-CONFIG_VIDEO=y ++CONFIG_DM_VIDEO=y + CONFIG_SYS_CONSOLE_FG_COL=0x00 + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_FDT_FIXUP_PARTITIONS=y +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0005-misc-imx8-add-sc_rm_set_master_sid.patch b/recipes-bsp/u-boot-mainline/files/0005-misc-imx8-add-sc_rm_set_master_sid.patch new file mode 100644 index 0000000..7edd837 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0005-misc-imx8-add-sc_rm_set_master_sid.patch @@ -0,0 +1,63 @@ +From 611fb0b83ccf05b05d9dfce6722349a182f60890 Mon Sep 17 00:00:00 2001 +From: Marcel Ziswiler +Date: Thu, 30 May 2019 16:57:19 +0300 +Subject: [PATCH 05/15] misc: imx8: add sc_rm_set_master_sid + +Add sc_rm_set_master_sid to support setting stream IDs. + +Signed-off-by: Marcel Ziswiler +--- + arch/arm/include/asm/arch-imx8/sci/sci.h | 2 ++ + drivers/misc/imx8/scu_api.c | 26 ++++++++++++++++++++++++++ + 2 files changed, 28 insertions(+) + +diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h +index 901b90d705..d24993690b 100644 +--- a/arch/arm/include/asm/arch-imx8/sci/sci.h ++++ b/arch/arm/include/asm/arch-imx8/sci/sci.h +@@ -80,6 +80,8 @@ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); + int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, + sc_faddr_t *addr_end); + sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); ++sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, ++ sc_rm_sid_t sid); + + /* PAD API */ + int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val); +diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c +index 031bc0048b..f2abae3f34 100644 +--- a/drivers/misc/imx8/scu_api.c ++++ b/drivers/misc/imx8/scu_api.c +@@ -393,3 +393,29 @@ sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource) + + return !!result; + } ++ ++sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid) ++{ ++ struct udevice *dev = gd->arch.scu_dev; ++ int size = sizeof(struct sc_rpc_msg_s); ++ struct sc_rpc_msg_s msg; ++ int ret; ++ u8 result; ++ ++ if (!dev) ++ hang(); ++ ++ RPC_VER(&msg) = SC_RPC_VERSION; ++ RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; ++ RPC_FUNC(&msg) = (u8)RM_FUNC_SET_MASTER_SID; ++ RPC_U16(&msg, 0U) = (u16)resource; ++ RPC_U16(&msg, 2U) = (u16)sid; ++ RPC_SIZE(&msg) = 2U; ++ ++ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); ++ if (ret) ++ printf("%s: res:%d res:%d\n", __func__, resource, ++ RPC_R8(&msg)); ++ result = RPC_R8(&msg); ++ return (sc_err_t) result; ++} +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0006-MLK-14938-8-imx8-Add-SMMU-setup-to-Soc-codes.patch b/recipes-bsp/u-boot-mainline/files/0006-MLK-14938-8-imx8-Add-SMMU-setup-to-Soc-codes.patch new file mode 100644 index 0000000..d365185 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0006-MLK-14938-8-imx8-Add-SMMU-setup-to-Soc-codes.patch @@ -0,0 +1,117 @@ +From 70ff91215f9969dfa9f8640b36ef4695d5b2d3f9 Mon Sep 17 00:00:00 2001 +From: Ye Li +Date: Wed, 17 May 2017 02:19:25 -0500 +Subject: [PATCH 06/15] MLK-14938-8 imx8: Add SMMU setup to Soc codes + +We setup SMMU in arch_preboot_os to avoid breaking u-boot driver. +Add a kconfig entry CONFIG_IMX_SMMU to enable it. +So far, the USDHC0-USDHC1 and FEC0-FEC1 are added into sid. + +Signed-off-by: Peng Fan +Signed-off-by: Ye Li +(cherry picked from downstream commit 7da6345919ee59a26cf65b4bc29072eea2fc0909) +(cherry picked from downstream commit 45308e7da90f342c2de7fbec1f8c5b8bd3f1b8e5) +--- + arch/arm/include/asm/arch-imx8/sid.h | 14 ++++++++++++ + arch/arm/mach-imx/imx8/Kconfig | 5 +++++ + arch/arm/mach-imx/imx8/cpu.c | 41 ++++++++++++++++++++++++++++++++++++ + 3 files changed, 60 insertions(+) + create mode 100644 arch/arm/include/asm/arch-imx8/sid.h + +diff --git a/arch/arm/include/asm/arch-imx8/sid.h b/arch/arm/include/asm/arch-imx8/sid.h +new file mode 100644 +index 0000000000..2250efa06b +--- /dev/null ++++ b/arch/arm/include/asm/arch-imx8/sid.h +@@ -0,0 +1,14 @@ ++/* ++ * Copyright 2017 NXP ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++#include ++ ++struct smmu_sid { ++ sc_rsrc_t rsrc; ++ sc_rm_sid_t sid; ++ char dev_name[32]; ++}; ++ ++sc_err_t imx8_config_smmu_sid(struct smmu_sid *dev_sids, int size); +diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig +index bbe323d5ca..d577b0f077 100644 +--- a/arch/arm/mach-imx/imx8/Kconfig ++++ b/arch/arm/mach-imx/imx8/Kconfig +@@ -1,5 +1,10 @@ + if ARCH_IMX8 + ++config IMX_SMMU ++ bool "Enable SMMU on i.MX8" ++ help ++ Enable the SMMU for peripherals on i.MX8 ++ + config IMX8 + bool + +diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c +index f2fa262ac8..72404d9eb6 100644 +--- a/arch/arm/mach-imx/imx8/cpu.c ++++ b/arch/arm/mach-imx/imx8/cpu.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -513,6 +514,46 @@ err: + printf("%s: fuse %d, err: %d\n", __func__, word[i], ret); + } + ++#ifdef CONFIG_IMX_SMMU ++struct smmu_sid dev_sids[] = { ++ { SC_R_SDHC_0, 0x11, "SDHC0" }, ++ { SC_R_SDHC_1, 0x11, "SDHC1" }, ++ { SC_R_SDHC_2, 0x11, "SDHC2" }, ++ { SC_R_ENET_0, 0x12, "FEC0" }, ++ { SC_R_ENET_1, 0x12, "FEC1" }, ++}; ++ ++sc_err_t imx8_config_smmu_sid(struct smmu_sid *dev_sids, int size) ++{ ++ int i; ++ sc_err_t sciErr = SC_ERR_NONE; ++ ++ if ((dev_sids == NULL) || (size <= 0)) ++ return SC_ERR_NONE; ++ ++ for (i = 0; i < size; i++) { ++ sciErr = sc_rm_set_master_sid(-1, ++ dev_sids[i].rsrc, ++ dev_sids[i].sid); ++ if (sciErr != SC_ERR_NONE) { ++ printf("set master sid error\n"); ++ return sciErr; ++ } ++ } ++ ++ return SC_ERR_NONE; ++} ++#endif ++ ++void arch_preboot_os(void) ++{ ++#ifdef CONFIG_IMX_SMMU ++ sc_pm_set_resource_power_mode(-1, SC_R_SMMU, SC_PM_PW_MODE_ON); ++ ++ imx8_config_smmu_sid(dev_sids, ARRAY_SIZE(dev_sids)); ++#endif ++} ++ + u32 get_cpu_rev(void) + { + u32 id = 0, rev = 0; +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0006-colibri-apalis-tegra-drop-DFU-support.patch b/recipes-bsp/u-boot-mainline/files/0006-colibri-apalis-tegra-drop-DFU-support.patch new file mode 100644 index 0000000..2609d96 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0006-colibri-apalis-tegra-drop-DFU-support.patch @@ -0,0 +1,104 @@ +From 1686d60e877fcf86a0eaf564a47639cf7b563454 Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Fri, 14 Jun 2019 10:59:10 +0300 +Subject: [PATCH 6/7] colibri/apalis tegra: drop DFU support + +We never really added a sensible DFU configuration for platforms +based on eMMC. Most of the things one might want to do can also be done +with UMS or fastboot, so drop the DFU configuration. + +Signed-off-by: Igor Opaniuk +--- + configs/apalis-tk1_defconfig | 3 --- + configs/apalis_t30_defconfig | 3 --- + configs/colibri_t20_defconfig | 3 --- + configs/colibri_t30_defconfig | 3 --- + 4 files changed, 12 deletions(-) + +diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig +index 946858e48e..e62cef713a 100644 +--- a/configs/apalis-tk1_defconfig ++++ b/configs/apalis-tk1_defconfig +@@ -17,7 +17,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_SYS_PROMPT="Apalis TK1 # " + # CONFIG_CMD_IMI is not set +-CONFIG_CMD_DFU=y + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -32,8 +31,6 @@ CONFIG_CMD_EXT4_WRITE=y + CONFIG_OF_LIVE=y + CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis" + CONFIG_SPL_DM=y +-CONFIG_DFU_MMC=y +-CONFIG_DFU_RAM=y + CONFIG_SYS_I2C_TEGRA=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y +diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig +index d231ccdb49..a4af07cfc7 100644 +--- a/configs/apalis_t30_defconfig ++++ b/configs/apalis_t30_defconfig +@@ -14,7 +14,6 @@ CONFIG_ARCH_MISC_INIT=y + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_SYS_PROMPT="Apalis T30 # " + # CONFIG_CMD_IMI is not set +-CONFIG_CMD_DFU=y + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -29,8 +28,6 @@ CONFIG_CMD_EXT4_WRITE=y + CONFIG_OF_LIVE=y + CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis" + CONFIG_SPL_DM=y +-CONFIG_DFU_MMC=y +-CONFIG_DFU_RAM=y + CONFIG_SYS_I2C_TEGRA=y + CONFIG_E1000=y + CONFIG_PCI=y +diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig +index e652ebc5a5..199241000c 100644 +--- a/configs/colibri_t20_defconfig ++++ b/configs/colibri_t20_defconfig +@@ -13,7 +13,6 @@ CONFIG_ARCH_MISC_INIT=y + CONFIG_SPL_TEXT_BASE=0x00108000 + CONFIG_SYS_PROMPT="Colibri T20 # " + # CONFIG_CMD_IMI is not set +-CONFIG_CMD_DFU=y + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -37,8 +36,6 @@ CONFIG_OF_LIVE=y + CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri" + CONFIG_ENV_IS_IN_NAND=y + CONFIG_SPL_DM=y +-CONFIG_DFU_MMC=y +-CONFIG_DFU_RAM=y + CONFIG_SYS_I2C_TEGRA=y + CONFIG_MTD=y + CONFIG_MTD_UBI_FASTMAP=y +diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig +index 99be27823d..f9f337457d 100644 +--- a/configs/colibri_t30_defconfig ++++ b/configs/colibri_t30_defconfig +@@ -14,7 +14,6 @@ CONFIG_ARCH_MISC_INIT=y + CONFIG_SPL_TEXT_BASE=0x80108000 + CONFIG_SYS_PROMPT="Colibri T30 # " + # CONFIG_CMD_IMI is not set +-CONFIG_CMD_DFU=y + # CONFIG_CMD_FLASH is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y +@@ -28,8 +27,6 @@ CONFIG_CMD_EXT4_WRITE=y + CONFIG_OF_LIVE=y + CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri" + CONFIG_SPL_DM=y +-CONFIG_DFU_MMC=y +-CONFIG_DFU_RAM=y + CONFIG_SYS_I2C_TEGRA=y + CONFIG_SYS_NS16550=y + CONFIG_USB=y +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0006-configs-colibri-imx6ull-switch-to-DM_VIDEO.patch b/recipes-bsp/u-boot-mainline/files/0006-configs-colibri-imx6ull-switch-to-DM_VIDEO.patch new file mode 100644 index 0000000..b082215 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0006-configs-colibri-imx6ull-switch-to-DM_VIDEO.patch @@ -0,0 +1,27 @@ +From 80dde745c0f0a382e7e6b71ba24bef35b81e5eec Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Wed, 19 Jun 2019 11:47:10 +0300 +Subject: [PATCH 6/6] configs: colibri-imx6ull: switch to DM_VIDEO + +Use CONFIG_DM_VIDEO=y by default for Colibri iMX6ULL. + +Signed-off-by: Igor Opaniuk +--- + configs/colibri-imx6ull_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig +index 8f09f1b3d6..bb9d6b5707 100644 +--- a/configs/colibri-imx6ull_defconfig ++++ b/configs/colibri-imx6ull_defconfig +@@ -77,6 +77,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 + CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 + CONFIG_CI_UDC=y + CONFIG_USB_GADGET_DOWNLOAD=y +-CONFIG_VIDEO=y ++CONFIG_DM_VIDEO=y + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_FDT_FIXUP_PARTITIONS=y +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0006-net-fec_mxc-not-access-reserved-register-on-i.MX8.patch b/recipes-bsp/u-boot-mainline/files/0006-net-fec_mxc-not-access-reserved-register-on-i.MX8.patch deleted file mode 100644 index ae74e32..0000000 --- a/recipes-bsp/u-boot-mainline/files/0006-net-fec_mxc-not-access-reserved-register-on-i.MX8.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 94e374129741c5e3b1fc248445f1acd0ce1564c2 Mon Sep 17 00:00:00 2001 -From: Peng Fan -Date: Mon, 15 Apr 2019 05:18:33 +0000 -Subject: [PATCH 06/19] net: fec_mxc: not access reserved register on i.MX8 - -We should not access reserved register on i.MX8, otherwise met SERROR - -Signed-off-by: Peng Fan -Acked-by: Joe Hershberger ---- - drivers/net/fec_mxc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c -index a672250e16..d7c080943a 100644 ---- a/drivers/net/fec_mxc.c -+++ b/drivers/net/fec_mxc.c -@@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd) - writel(0x00000000, &fec->eth->gaddr2); - - /* Do not access reserved register */ -- if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) { -+ if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) { - /* clear MIB RAM */ - for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) - writel(0, i); --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0007-apalis-imx8-enable-smmu-setup.patch b/recipes-bsp/u-boot-mainline/files/0007-apalis-imx8-enable-smmu-setup.patch new file mode 100644 index 0000000..400cf48 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0007-apalis-imx8-enable-smmu-setup.patch @@ -0,0 +1,25 @@ +From 18d42de50e1787b533b6d35894d853ac51f977bc Mon Sep 17 00:00:00 2001 +From: Marcel Ziswiler +Date: Thu, 30 May 2019 17:00:06 +0300 +Subject: [PATCH 07/15] apalis-imx8: enable smmu setup + +Signed-off-by: Marcel Ziswiler +--- + configs/apalis-imx8qm_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig +index f3dbaf0101..5e6b89ad9d 100644 +--- a/configs/apalis-imx8qm_defconfig ++++ b/configs/apalis-imx8qm_defconfig +@@ -2,6 +2,7 @@ CONFIG_ARM=y + CONFIG_ARCH_IMX8=y + CONFIG_SYS_TEXT_BASE=0x80020000 + CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_IMX_SMMU=y + CONFIG_TARGET_APALIS_IMX8=y + CONFIG_NR_DRAM_BANKS=3 + CONFIG_DISTRO_DEFAULTS=y +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0007-colibri-apalis-imx-drop-DFU-support.patch b/recipes-bsp/u-boot-mainline/files/0007-colibri-apalis-imx-drop-DFU-support.patch new file mode 100644 index 0000000..78a9984 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0007-colibri-apalis-imx-drop-DFU-support.patch @@ -0,0 +1,92 @@ +From 21b2944415831281eb0c2d18bf265de5feff7aed Mon Sep 17 00:00:00 2001 +From: Igor Opaniuk +Date: Fri, 14 Jun 2019 10:59:11 +0300 +Subject: [PATCH 7/7] colibri/apalis imx: drop DFU support + +We never really added a sensible DFU configuration for platforms +based on eMMC. Most of the things one might want to do can also be done +with UMS or fastboot, so drop the DFU configuration. + +Signed-off-by: Igor Opaniuk +--- + configs/apalis_imx6_defconfig | 2 -- + configs/colibri-imx6ull_defconfig | 1 - + configs/colibri_imx6_defconfig | 2 -- + configs/colibri_imx7_emmc_defconfig | 2 -- + 4 files changed, 7 deletions(-) + +diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig +index 6f36f7b82e..dcf6c100dc 100644 +--- a/configs/apalis_imx6_defconfig ++++ b/configs/apalis_imx6_defconfig +@@ -38,7 +38,6 @@ CONFIG_CMD_ASKENV=y + CONFIG_CRC32_VERIFY=y + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y +-CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y +@@ -57,7 +56,6 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_IP_DEFRAG=y + CONFIG_TFTP_BLOCKSIZE=4096 + CONFIG_DWC_AHSATA=y +-CONFIG_DFU_MMC=y + CONFIG_DM_GPIO=y + CONFIG_DM_I2C=y + CONFIG_DM_MMC=y +diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig +index 5c89439f7b..e3a95ee16f 100644 +--- a/configs/colibri-imx6ull_defconfig ++++ b/configs/colibri-imx6ull_defconfig +@@ -48,7 +48,6 @@ CONFIG_ENV_IS_IN_NAND=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_IP_DEFRAG=y + CONFIG_TFTP_BLOCKSIZE=16352 +-CONFIG_DFU_MMC=y + CONFIG_DFU_NAND=y + CONFIG_DM_GPIO=y + CONFIG_DM_I2C=y +diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig +index a60d6951c9..f3df827e16 100644 +--- a/configs/colibri_imx6_defconfig ++++ b/configs/colibri_imx6_defconfig +@@ -37,7 +37,6 @@ CONFIG_CMD_ASKENV=y + CONFIG_CRC32_VERIFY=y + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y +-CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y +@@ -56,7 +55,6 @@ CONFIG_ENV_IS_IN_MMC=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_IP_DEFRAG=y + CONFIG_TFTP_BLOCKSIZE=16352 +-CONFIG_DFU_MMC=y + CONFIG_DM_GPIO=y + CONFIG_DM_I2C=y + CONFIG_DM_MMC=y +diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig +index 89f43e5fb9..a430d43e17 100644 +--- a/configs/colibri_imx7_emmc_defconfig ++++ b/configs/colibri_imx7_emmc_defconfig +@@ -25,7 +25,6 @@ CONFIG_SYS_PROMPT="Colibri iMX7 # " + CONFIG_CMD_ASKENV=y + CONFIG_CRC32_VERIFY=y + CONFIG_CMD_MEMTEST=y +-CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + # CONFIG_RANDOM_UUID is not set +@@ -44,7 +43,6 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_IP_DEFRAG=y + CONFIG_TFTP_BLOCKSIZE=16352 + CONFIG_FSL_CAAM=y +-CONFIG_DFU_MMC=y + CONFIG_DM_GPIO=y + CONFIG_DM_I2C=y + CONFIG_DM_MMC=y +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0007-imx-fix-building-for-i.mx8-without-spl.patch b/recipes-bsp/u-boot-mainline/files/0007-imx-fix-building-for-i.mx8-without-spl.patch deleted file mode 100644 index b4ebfad..0000000 --- a/recipes-bsp/u-boot-mainline/files/0007-imx-fix-building-for-i.mx8-without-spl.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 961ca9ed15a4f2c1f590f4dc02f69b93c773a90f Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Fri, 26 Apr 2019 10:56:13 +0200 -Subject: [PATCH 07/19] imx: fix building for i.mx8 without spl - -Building with Travis CI complained and stopped with the following error: -+cc1: fatal error: opening output file spl/u-boot-spl.cfgout: No such -file or directory -+compilation terminated. - -This fixes commit caceb739ea07 ("imx: build flash.bin for i.MX8") which -took SPL being enabled on i.MX8 for granted. - -Reported-by: Stefano Babic -Signed-off-by: Marcel Ziswiler -Reviewed-by: Peng Fan ---- - arch/arm/mach-imx/Makefile | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile -index 37675d0558..6531c67fc6 100644 ---- a/arch/arm/mach-imx/Makefile -+++ b/arch/arm/mach-imx/Makefile -@@ -107,7 +107,9 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%) - ifeq ($(CONFIG_ARCH_IMX8), y) - CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh - IMAGE_TYPE := imx8image -+ifeq ($(CONFIG_SPL_BUILD),y) - SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi) -+endif - DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) - else ifeq ($(CONFIG_ARCH_IMX8M), y) - IMAGE_TYPE := imx8mimage --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0008-MLK-16087-imx8qm-qxp-Disable-kernel-FDT-nodes-for-th.patch b/recipes-bsp/u-boot-mainline/files/0008-MLK-16087-imx8qm-qxp-Disable-kernel-FDT-nodes-for-th.patch new file mode 100644 index 0000000..919a777 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0008-MLK-16087-imx8qm-qxp-Disable-kernel-FDT-nodes-for-th.patch @@ -0,0 +1,154 @@ +From db6acd1b9a0c4ee3819c5546d033be4710233084 Mon Sep 17 00:00:00 2001 +From: Ye Li +Date: Mon, 16 Apr 2018 00:05:24 -0700 +Subject: [PATCH 08/15] MLK-16087 imx8qm/qxp: Disable kernel FDT nodes for the + resources are not owned + +Before starting the kernel, need to check if the enabled nodes (resources) in FDT +are owned by current partition. If it is not owned, need to disable it because A core +can't access it. +We use the node's power-domain property to get the PD node which has the SCFW resource +id in its reg property. Then we can check it with SCFW. + +Signed-off-by: Ye Li +(cherry picked from downstream commit 358372674b29685788a4007b0944ab03b7fafc13) +--- + arch/arm/mach-imx/imx8/cpu.c | 115 +++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 115 insertions(+) + +diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c +index 72404d9eb6..7f2dd2166b 100644 +--- a/arch/arm/mach-imx/imx8/cpu.c ++++ b/arch/arm/mach-imx/imx8/cpu.c +@@ -11,6 +11,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -193,6 +195,119 @@ int mmc_get_env_dev(void) + } + #endif + ++#ifdef CONFIG_OF_SYSTEM_SETUP ++static bool check_owned_resource(sc_rsrc_t rsrc_id) ++{ ++ sc_ipc_t ipcHndl = 0; ++ bool owned; ++ ++ ipcHndl = -1; ++ ++ owned = sc_rm_is_resource_owned(ipcHndl, rsrc_id); ++ ++ return owned; ++} ++ ++static int disable_fdt_node(void *blob, int nodeoffset) ++{ ++ int rc, ret; ++ const char *status = "disabled"; ++ ++ do { ++ rc = fdt_setprop(blob, nodeoffset, "status", status, strlen(status) + 1); ++ if (rc) { ++ if (rc == -FDT_ERR_NOSPACE) { ++ ret = fdt_increase_size(blob, 512); ++ if (ret) ++ return ret; ++ } ++ } ++ } while (rc == -FDT_ERR_NOSPACE); ++ ++ return rc; ++} ++ ++static void update_fdt_with_owned_resources(void *blob) ++{ ++ /* Traverses the fdt nodes, ++ * check its power domain and use the resource id in the power domain ++ * for checking whether it is owned by current partition ++ */ ++ ++ int offset = 0, next_off, addr; ++ int depth, next_depth; ++ unsigned int rsrc_id; ++ const fdt32_t *php; ++ const char *name; ++ int rc; ++ ++ for (offset = fdt_next_node(blob, offset, &depth); offset > 0; ++ offset = fdt_next_node(blob, offset, &depth)) { ++ ++ debug("Node name: %s, depth %d\n", fdt_get_name(blob, offset, NULL), depth); ++ ++ if (!fdtdec_get_is_enabled(blob, offset)) { ++ debug(" - ignoring disabled device\n"); ++ continue; ++ } ++ ++ if (!fdt_node_check_compatible(blob, offset, "nxp,imx8-pd")) { ++ /* Skip to next depth=1 node*/ ++ next_off = offset; ++ next_depth = depth; ++ do { ++ offset = next_off; ++ depth = next_depth; ++ next_off = fdt_next_node(blob, offset, &next_depth); ++ if (next_off < 0 || next_depth < 1) ++ break; ++ ++ debug("PD name: %s, offset %d, depth %d\n", ++ fdt_get_name(blob, next_off, NULL), next_off, next_depth); ++ } while (next_depth > 1); ++ ++ continue; ++ } ++ ++ php = fdt_getprop(blob, offset, "power-domains", NULL); ++ if (!php) { ++ debug(" - ignoring no power-domains\n"); ++ } else { ++ addr = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*php)); ++ rsrc_id = fdtdec_get_uint(blob, addr, "reg", 0); ++ ++ if (rsrc_id == SC_R_LAST) { ++ name = fdt_get_name(blob, offset, NULL); ++ printf("%s's power domain use SC_R_LAST\n", name); ++ continue; ++ } ++ ++ debug("power-domains phandle 0x%x, addr 0x%x, resource id %u\n", ++ fdt32_to_cpu(*php), addr, rsrc_id); ++ ++ if (!check_owned_resource(rsrc_id)) { ++ ++ /* If the resource is not owned, disable it in FDT */ ++ rc = disable_fdt_node(blob, offset); ++ if (!rc) ++ printf("Disable %s, resource id %u, pd phandle 0x%x\n", ++ fdt_get_name(blob, offset, NULL), rsrc_id, fdt32_to_cpu(*php)); ++ else ++ printf("Unable to disable %s, err=%s\n", ++ fdt_get_name(blob, offset, NULL), fdt_strerror(rc)); ++ } ++ } ++ } ++} ++ ++int ft_system_setup(void *blob, bd_t *bd) ++{ ++ update_fdt_with_owned_resources(blob); ++ ++ return 0; ++} ++#endif ++ + #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */ + + static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0008-board-toradex-add-colibri-imx8qxp-2gb-wb-it-v1.0b-mo.patch b/recipes-bsp/u-boot-mainline/files/0008-board-toradex-add-colibri-imx8qxp-2gb-wb-it-v1.0b-mo.patch deleted file mode 100644 index 2b54935..0000000 --- a/recipes-bsp/u-boot-mainline/files/0008-board-toradex-add-colibri-imx8qxp-2gb-wb-it-v1.0b-mo.patch +++ /dev/null @@ -1,1228 +0,0 @@ -From 52c2bae8472f47c6cb0b9d4877168160e0b7636a Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Sat, 6 Apr 2019 13:42:24 +0200 -Subject: [PATCH 08/19] board: toradex: add colibri imx8qxp 2gb wb it v1.0b - module support - -This commit adds initial support for the Toradex Colibri iMX8QXP 2GB WB -IT V1.0B module. Unlike the V1.0A early access samples exclusively -booting from SD card, they are now strapped to boot from eFuses which -are factory fused to properly boot from their on-module eMMC. U-Boot -supports either booting from the on-module eMMC or may be used for -recovery purpose using the universal update utility (uuu) aka mfgtools -3.0. - -Functionality wise the following is known to be working: -- eMMC and MMC/SD card -- Ethernet -- GPIOs -- I2C - -Unfortunately, there is no USB functionality for the i.MX 8QXP as of -yet. - -Signed-off-by: Marcel Ziswiler -Reviewed-by: Igor Opaniuk - -Series-to: u-boot@lists.denx.de -Series-cc: Igor Opaniuk -Series-cc: Stefano Babic -Series-cc: Peng Fan - -Series-version: 6 - -Series-changes: 2 -- Changed imx-atf git clone command to include initial branch - information as suggested by Igor. -- Sorted board file includes alphabetically as suggested by Igor. -- Got rid of SPL configuration in legacy header file as suggested by - Igor and the whole use of SPL on i.MX 8X anyway neither works well - nor makes any much sense at all. - -Series-changes: 3 -- Added Igor's reviewed-by tag. - -Series-changes: 4 -- Fixed SPDX as well as using SZ_ macros where applicable as suggested - by Igor. -- Fixed superfluous trailing line continuation introduced by commit - 0d331c035a09 ("imx: support i.MX8QM MEK board") in the Makefile plus - sorted stuff alphabetically again. -- Applied changes similar to commit 3b9ac5415084 ("imx: 8qxp_mek: fix - fdt_file and console"). However, note that using ${baudrate} in - console= like that won't actually work! -- Applied changes similar to commit e5b8f7e665aa ("imx8qxp: mek: enable - dm-spl for pm"). - -Series-changes: 5 -- Keep alphabetical order of device trees in Makefile. -- Order targets in Kconfig alphabetically. -- Fix indentation in SPDX. -- Remove stale includes from board file. -- Take into account ahab-container being platform specific. -- Use vidargs instead of multiple discrete video= in configuration. -- Fix console baudrate specification. -- Remove redundant CONFIG_SYS_MMC_ENV_DEV define and add some clarifying - comment. -- Fix product name being Colibri iMX8X in a comment. -- Remove obsolete CONFIG_NR_DRAM_BANKS. - -Series-changes: 6 -- Use firmware-imx-8.0 matching NXP's sumo-4.14.78-1.0.0_ga BSP as - suggested by Max during review of Apalis iMX8QM. -- Drop anyway commented out board_gpio_init() stuff. -- Drop Qualcomm (formwerly Atheros) AR8031 specific board_phy_config() - stuff not applicable to the Micrel PHY we are using as suggested by - Max during review of Apalis iMX8QM. - -Cover-letter: -colibri imx8qxp 2gb wb it v1.0b module support - -This series fixes building for i.MX8 without SPL and adds support for -more lpuart instances, cleans-up and extends the Toradex SKU handling -and last but not least introduces support for the Toradex Colibri -iMX8QXP 2GB WB IT V1.0B module. - -This series is available together with the last few clean-up patches -on our git server [1] as well. - -[1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next -END ---- - arch/arm/dts/Makefile | 3 +- - arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 117 +++++++++ - arch/arm/dts/fsl-imx8qxp-colibri.dts | 328 ++++++++++++++++++++++++ - arch/arm/mach-imx/imx8/Kconfig | 12 +- - board/toradex/colibri-imx8qxp/Kconfig | 30 +++ - board/toradex/colibri-imx8qxp/MAINTAINERS | 9 + - board/toradex/colibri-imx8qxp/Makefile | 6 + - board/toradex/colibri-imx8qxp/README | 66 +++++ - board/toradex/colibri-imx8qxp/colibri-imx8qxp.c | 160 ++++++++++++ - board/toradex/colibri-imx8qxp/imximage.cfg | 24 ++ - configs/colibri-imx8qxp_defconfig | 53 ++++ - include/configs/colibri-imx8qxp.h | 210 +++++++++++++++ - 12 files changed, 1014 insertions(+), 4 deletions(-) - create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi - create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts - create mode 100644 board/toradex/colibri-imx8qxp/Kconfig - create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS - create mode 100644 board/toradex/colibri-imx8qxp/Makefile - create mode 100644 board/toradex/colibri-imx8qxp/README - create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c - create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg - create mode 100644 configs/colibri-imx8qxp_defconfig - create mode 100644 include/configs/colibri-imx8qxp.h - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index e56a39e0b1..598dc213e3 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -576,8 +576,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ - dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb - - dtb-$(CONFIG_ARCH_IMX8) += \ -- fsl-imx8qxp-mek.dtb \ - fsl-imx8qm-mek.dtb \ -+ fsl-imx8qxp-colibri.dtb \ -+ fsl-imx8qxp-mek.dtb - - dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb - -diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi -new file mode 100644 -index 0000000000..5b061f94ba ---- /dev/null -+++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi -@@ -0,0 +1,117 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR X11 -+/* -+ * Copyright 2019 Toradex AG -+ */ -+ -+&{/imx8qx-pm} { -+ -+ u-boot,dm-spl; -+}; -+ -+&mu { -+ u-boot,dm-spl; -+}; -+ -+&clk { -+ u-boot,dm-spl; -+}; -+ -+&iomuxc { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio0 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio1 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio2 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio3 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio4 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio5 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio6 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio7 { -+ u-boot,dm-spl; -+}; -+ -+&pd_conn { -+ u-boot,dm-spl; -+}; -+ -+&pd_conn_sdch0 { -+ u-boot,dm-spl; -+}; -+ -+&pd_conn_sdch1 { -+ u-boot,dm-spl; -+}; -+ -+&pd_conn_sdch2 { -+ u-boot,dm-spl; -+}; -+ -+&gpio0 { -+ u-boot,dm-spl; -+}; -+ -+&gpio1 { -+ u-boot,dm-spl; -+}; -+ -+&gpio2 { -+ u-boot,dm-spl; -+}; -+ -+&gpio3 { -+ u-boot,dm-spl; -+}; -+ -+&gpio4 { -+ u-boot,dm-spl; -+}; -+ -+&gpio5 { -+ u-boot,dm-spl; -+}; -+ -+&gpio6 { -+ u-boot,dm-spl; -+}; -+ -+&gpio7 { -+ u-boot,dm-spl; -+}; -+ -+&lpuart3 { -+ u-boot,dm-spl; -+}; -+ -+&usdhc1 { -+ u-boot,dm-spl; -+}; -+ -+&usdhc2 { -+ u-boot,dm-spl; -+}; -diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts -new file mode 100644 -index 0000000000..0c20edf2cf ---- /dev/null -+++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts -@@ -0,0 +1,328 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR X11 -+/* -+ * Copyright 2019 Toradex AG -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-imx8qxp.dtsi" -+#include "fsl-imx8qxp-colibri-u-boot.dtsi" -+ -+/ { -+ model = "Toradex Colibri iMX8QXP"; -+ compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp"; -+ -+ chosen { -+ bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200"; -+ stdout-path = &lpuart3; -+ }; -+ -+ reg_usbh_vbus: regulator-usbh-vbus { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbh1_reg>; -+ regulator-name = "usbh_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>; -+ -+ colibri-imx8qxp { -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 -+ SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart3: lpuart3grp { -+ fsl,pins = < -+ SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 -+ SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { -+ fsl,pins = < -+ SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */ -+ SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x00000020 /* CTS */ -+ SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x00000020 /* RTS */ -+ SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x00000020 /* DSR */ -+ SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000020 /* DCD */ -+ SC_P_CSI_EN_LSIO_GPIO3_IO02 0x00000020 /* RI */ -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */ -+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */ -+ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 -+ SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 -+ SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 -+ SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 -+ SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 -+ SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 -+ SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 -+ SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061 -+ >; -+ }; -+ -+ pinctrl_gpio_bl_on: gpio-bl-on { -+ fsl,pins = < -+ SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x00000040 -+ >; -+ }; -+ -+ pinctrl_hog0: hog0grp { -+ fsl,pins = < -+ SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ -+ >; -+ }; -+ -+ pinctrl_hog1: hog1grp { -+ fsl,pins = < -+ SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x00000020 /* 45 */ -+ SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* 65 */ -+ SC_P_CSI_D07_CI_PI_D09 0x00000061 -+ SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x00000020 /* 69 */ -+ SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000020 /* 73 */ -+ SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x00000020 /* 79 */ -+ SC_P_CSI_D02_CI_PI_D04 0x00000061 -+ SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* 85 */ -+ SC_P_CSI_D06_CI_PI_D08 0x00000061 -+ SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x00000020 /* 95 */ -+ SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x00000020 /* 97 */ -+ SC_P_CSI_D03_CI_PI_D05 0x00000061 -+ SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x00000020 /* 99 */ -+ SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x00000020 /* 101 */ -+ SC_P_CSI_D00_CI_PI_D02 0x00000061 -+ SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x00000020 /* 103 */ -+ SC_P_CSI_D01_CI_PI_D03 0x00000061 -+ SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x00000020 /* 105 */ -+ SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x00000020 /* 107 */ -+ SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x00000020 /* 127 */ -+ SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x00000020 /* 131 */ -+ SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000020 /* 133 */ -+ SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x00000020 /* 96 */ -+ SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x00000020 /* 98 */ -+ SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000020 /* 100 */ -+ SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000020 /* 102 */ -+ SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x00000020 /* 104 */ -+ SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000020 /* 106 */ -+ >; -+ }; -+ -+ pinctrl_hog2: hog2grp { -+ fsl,pins = < -+ SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x00000020 /* 75 */ -+ SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x00000020 /* 77 */ -+ SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000020 /* 89 */ -+ SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x00000020 /* 93 */ -+ >; -+ }; -+ -+ /* Off Module I2C */ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 -+ SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 -+ >; -+ }; -+ -+ /*INT*/ -+ pinctrl_usb3503a: usb3503a-grp { -+ fsl,pins = < -+ SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061 -+ >; -+ }; -+ -+ pinctrl_usbc_det: usbc-det { -+ fsl,pins = < -+ SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 -+ >; -+ }; -+ -+ pinctrl_usbh1_reg: usbh1-reg { -+ fsl,pins = < -+ SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { -+ fsl,pins = < -+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { -+ fsl,pins = < -+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 -+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_gpio: usdhc2gpiogrp { -+ fsl,pins = < -+ SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz { -+ fsl,pins = < -+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz { -+ fsl,pins = < -+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ }; -+}; -+ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+&lpuart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; -+ status = "okay"; -+}; -+ -+&gpio0 { -+ status = "okay"; -+}; -+ -+&gpio1 { -+ status = "okay"; -+}; -+ -+&gpio3 { -+ status = "okay"; -+}; -+ -+&gpio4 { -+ status = "okay"; -+}; -+ -+&fec1 { -+ phy-handle = <ðphy0>; -+ phy-mode = "rmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ max-speed = <100>; -+ reg = <2>; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+}; -+ -+&usdhc1 { -+ bus-width = <8>; -+ non-removable; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ bus-width = <4>; -+ cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; -+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; -+ status = "okay"; -+}; -diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig -index c32f7dbb61..90223aaefc 100644 ---- a/arch/arm/mach-imx/imx8/Kconfig -+++ b/arch/arm/mach-imx/imx8/Kconfig -@@ -27,8 +27,8 @@ choice - prompt "i.MX8 board select" - optional - --config TARGET_IMX8QXP_MEK -- bool "Support i.MX8QXP MEK board" -+config TARGET_COLIBRI_IMX8QXP -+ bool "Support Colibri iMX8QXP module" - select BOARD_LATE_INIT - select IMX8QXP - -@@ -37,9 +37,15 @@ config TARGET_IMX8QM_MEK - select BOARD_LATE_INIT - select IMX8QM - -+config TARGET_IMX8QXP_MEK -+ bool "Support i.MX8QXP MEK board" -+ select BOARD_LATE_INIT -+ select IMX8QXP -+ - endchoice - --source "board/freescale/imx8qxp_mek/Kconfig" - source "board/freescale/imx8qm_mek/Kconfig" -+source "board/freescale/imx8qxp_mek/Kconfig" -+source "board/toradex/colibri-imx8qxp/Kconfig" - - endif -diff --git a/board/toradex/colibri-imx8qxp/Kconfig b/board/toradex/colibri-imx8qxp/Kconfig -new file mode 100644 -index 0000000000..340fe72816 ---- /dev/null -+++ b/board/toradex/colibri-imx8qxp/Kconfig -@@ -0,0 +1,30 @@ -+if TARGET_COLIBRI_IMX8QXP -+ -+config SYS_BOARD -+ default "colibri-imx8qxp" -+ -+config SYS_VENDOR -+ default "toradex" -+ -+config SYS_CONFIG_NAME -+ default "colibri-imx8qxp" -+ -+config TDX_CFG_BLOCK -+ default y -+ -+config TDX_HAVE_MMC -+ default y -+ -+config TDX_CFG_BLOCK_DEV -+ default "0" -+ -+config TDX_CFG_BLOCK_PART -+ default "1" -+ -+# Toradex config block in eMMC, at the end of 1st "boot sector" -+config TDX_CFG_BLOCK_OFFSET -+ default "-512" -+ -+source "board/toradex/common/Kconfig" -+ -+endif -diff --git a/board/toradex/colibri-imx8qxp/MAINTAINERS b/board/toradex/colibri-imx8qxp/MAINTAINERS -new file mode 100644 -index 0000000000..39a9eb79b7 ---- /dev/null -+++ b/board/toradex/colibri-imx8qxp/MAINTAINERS -@@ -0,0 +1,9 @@ -+Colibri iMX8QXP -+M: Marcel Ziswiler -+W: http://developer.toradex.com/software/linux/linux-software -+S: Maintained -+F: arch/arm/dts/fsl-imx8qxp-colibri.dts -+F: arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi -+F: board/toradex/colibri-imx8qxp/ -+F: configs/colibri-imx8qxp_defconfig -+F: include/configs/colibri-imx8qxp.h -diff --git a/board/toradex/colibri-imx8qxp/Makefile b/board/toradex/colibri-imx8qxp/Makefile -new file mode 100644 -index 0000000000..db5a718416 ---- /dev/null -+++ b/board/toradex/colibri-imx8qxp/Makefile -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+# Copyright 2019 Toradex -+# -+ -+obj-y += colibri-imx8qxp.o -diff --git a/board/toradex/colibri-imx8qxp/README b/board/toradex/colibri-imx8qxp/README -new file mode 100644 -index 0000000000..708bb3e51c ---- /dev/null -+++ b/board/toradex/colibri-imx8qxp/README -@@ -0,0 +1,66 @@ -+U-Boot for the Toradex Colibri iMX8QXP V1.0B Module -+ -+Quick Start -+=========== -+ -+- Build the ARM trusted firmware binary -+- Get scfw_tcm.bin and ahab-container.img -+- Build U-Boot -+- Load U-Boot binary using uuu -+- Flash U-Boot binary into the eMMC -+- Boot -+ -+Get and Build the ARM Trusted Firmware -+====================================== -+ -+$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf -+$ cd imx-atf/ -+$ make PLAT=imx8qxp bl31 -+ -+Get scfw_tcm.bin and ahab-container.img -+======================================= -+ -+$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true -+$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin -+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin -+$ chmod +x firmware-imx-8.0.bin -+$ ./firmware-imx-8.0.bin -+ -+Copy the following binaries to the U-Boot folder: -+ -+$ cp imx-atf/build/imx8qxp/release/bl31.bin . -+$ cp u-boot/u-boot.bin . -+ -+Copy the following firmware to the U-Boot folder: -+ -+$ cp firmware-imx-8.0/firmware/seco/ahab-container.img . -+ -+Build U-Boot -+============ -+ -+$ make colibri-imx8qxp_defconfig -+$ make u-boot-dtb.imx -+ -+Load the U-Boot Binary Using UUU -+================================ -+ -+Get the latest version of the universal update utility (uuu) aka mfgtools 3.0: -+ -+https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases -+ -+Put the module into USB recovery aka serial downloader mode, connect USB device -+to your host and execute uuu: -+ -+sudo ./uuu u-boot/u-boot-dtb.imx -+ -+Flash the U-Boot Binary into the eMMC -+===================================== -+ -+Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition: -+ -+load mmc 1:1 $loadaddr u-boot-dtb.imx -+setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 -+mmc dev 0 1 -+mmc write ${loadaddr} 0x0 ${blkcnt} -+ -+Boot -diff --git a/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c -new file mode 100644 -index 0000000000..aa8eaa0ea1 ---- /dev/null -+++ b/board/toradex/colibri-imx8qxp/colibri-imx8qxp.c -@@ -0,0 +1,160 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 Toradex -+ */ -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../common/tdx-cfg-block.h" -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ -+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ -+ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ -+ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) -+ -+static iomux_cfg_t uart3_pads[] = { -+ SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), -+ SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), -+ /* Transceiver FORCEOFF# signal, mux to use pull-up */ -+ SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL), -+}; -+ -+static void setup_iomux_uart(void) -+{ -+ imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); -+} -+ -+int board_early_init_f(void) -+{ -+ sc_pm_clock_rate_t rate; -+ sc_err_t err = 0; -+ -+ /* -+ * This works around that having only UART3 up the baudrate is 1.2M -+ * instead of 115.2k. Set UART0 clock root to 80 MHz -+ */ -+ rate = 80000000; -+ err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); -+ if (err != SC_ERR_NONE) -+ return 0; -+ -+ /* Power up UART3 */ -+ err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3, SC_PM_PW_MODE_ON); -+ if (err != SC_ERR_NONE) -+ return 0; -+ -+ /* Set UART3 clock root to 80 MHz */ -+ rate = 80000000; -+ err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER, &rate); -+ if (err != SC_ERR_NONE) -+ return 0; -+ -+ /* Enable UART3 clock root */ -+ err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER, true, false); -+ if (err != SC_ERR_NONE) -+ return 0; -+ -+ setup_iomux_uart(); -+ -+ return 0; -+} -+ -+#if IS_ENABLED(CONFIG_DM_GPIO) -+static void board_gpio_init(void) -+{ -+ /* TODO */ -+} -+#else -+static inline void board_gpio_init(void) {} -+#endif -+ -+#if IS_ENABLED(CONFIG_FEC_MXC) -+#include -+ -+int board_phy_config(struct phy_device *phydev) -+{ -+ if (phydev->drv->config) -+ phydev->drv->config(phydev); -+ -+ return 0; -+} -+#endif -+ -+void build_info(void) -+{ -+ u32 sc_build = 0, sc_commit = 0; -+ -+ /* Get SCFW build and commit id */ -+ sc_misc_build_info(-1, &sc_build, &sc_commit); -+ if (!sc_build) { -+ printf("SCFW does not support build info\n"); -+ sc_commit = 0; /* Display 0 if build info not supported */ -+ } -+ printf("Build: SCFW %x\n", sc_commit); -+} -+ -+int checkboard(void) -+{ -+ puts("Model: Toradex Colibri iMX8X\n"); -+ -+ build_info(); -+ print_bootinfo(); -+ -+ return 0; -+} -+ -+int board_init(void) -+{ -+ board_gpio_init(); -+ -+ return 0; -+} -+ -+void detail_board_ddr_info(void) -+{ -+ puts("\nDDR "); -+} -+ -+/* -+ * Board specific reset that is system reset. -+ */ -+void reset_cpu(ulong addr) -+{ -+ /* TODO */ -+} -+ -+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -+int ft_board_setup(void *blob, bd_t *bd) -+{ -+ return ft_common_board_setup(blob, bd); -+} -+#endif -+ -+int board_mmc_get_env_dev(int devno) -+{ -+ return devno; -+} -+ -+int board_late_init(void) -+{ -+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -+/* TODO move to common */ -+ env_set("board_name", "Colibri iMX8QXP"); -+ env_set("board_rev", "v1.0"); -+#endif -+ -+ return 0; -+} -diff --git a/board/toradex/colibri-imx8qxp/imximage.cfg b/board/toradex/colibri-imx8qxp/imximage.cfg -new file mode 100644 -index 0000000000..1dcd13271d ---- /dev/null -+++ b/board/toradex/colibri-imx8qxp/imximage.cfg -@@ -0,0 +1,24 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2019 Toradex -+ * -+ * Refer doc/README.imx8image for more details about how-to configure -+ * and create imx8image boot image -+ */ -+ -+#define __ASSEMBLY__ -+ -+/* Boot from SD, sector size 0x400 */ -+BOOT_FROM EMMC_FASTBOOT 0x400 -+/* SoC type IMX8QX */ -+SOC_TYPE IMX8QX -+/* Append seco container image */ -+APPEND mx8qx-ahab-container.img -+/* Create the 2nd container */ -+CONTAINER -+/* Add scfw image with exec attribute */ -+IMAGE SCU mx8qx-colibri-scfw-tcm.bin -+/* Add ATF image with exec attribute */ -+IMAGE A35 bl31.bin 0x80000000 -+/* Add U-Boot image with load attribute */ -+DATA A35 u-boot-dtb.bin 0x80020000 -diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig -new file mode 100644 -index 0000000000..6dee0be35a ---- /dev/null -+++ b/configs/colibri-imx8qxp_defconfig -@@ -0,0 +1,53 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_IMX8=y -+CONFIG_SYS_TEXT_BASE=0x80020000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_TARGET_COLIBRI_IMX8QXP=y -+CONFIG_DISTRO_DEFAULTS=y -+CONFIG_NR_DRAM_BANKS=3 -+CONFIG_FIT=y -+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8qxp/imximage.cfg" -+CONFIG_LOG=y -+CONFIG_VERSION_VARIABLE=y -+# CONFIG_DISPLAY_BOARDINFO is not set -+CONFIG_BOARD_EARLY_INIT_F=y -+CONFIG_CMD_CPU=y -+# CONFIG_CMD_IMPORTENV is not set -+CONFIG_CMD_MEMTEST=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_UUID=y -+CONFIG_CMD_EXT4_WRITE=y -+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_CLK_IMX8=y -+CONFIG_CPU=y -+CONFIG_DM_GPIO=y -+CONFIG_MXC_GPIO=y -+CONFIG_DM_I2C=y -+CONFIG_SYS_I2C_IMX_LPI2C=y -+CONFIG_MISC=y -+CONFIG_DM_MMC=y -+CONFIG_PHYLIB=y -+CONFIG_PHY_ADDR_ENABLE=y -+CONFIG_PHY_MICREL=y -+CONFIG_DM_ETH=y -+CONFIG_FEC_MXC_SHARE_MDIO=y -+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 -+CONFIG_FEC_MXC=y -+CONFIG_MII=y -+CONFIG_PINCTRL=y -+CONFIG_PINCTRL_IMX8=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_IMX8_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_SERIAL=y -+CONFIG_FSL_LPUART=y -+CONFIG_DM_THERMAL=y -+# CONFIG_EFI_LOADER is not set -diff --git a/include/configs/colibri-imx8qxp.h b/include/configs/colibri-imx8qxp.h -new file mode 100644 -index 0000000000..1bfeea6ab2 ---- /dev/null -+++ b/include/configs/colibri-imx8qxp.h -@@ -0,0 +1,210 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2019 Toradex -+ */ -+ -+#ifndef __COLIBRI_IMX8QXP_H -+#define __COLIBRI_IMX8QXP_H -+ -+#include -+#include -+ -+#define CONFIG_REMAKE_ELF -+ -+#define CONFIG_DISPLAY_BOARDINFO_LATE -+ -+#undef CONFIG_CMD_EXPORTENV -+#undef CONFIG_CMD_IMPORTENV -+#undef CONFIG_CMD_IMLS -+ -+#undef CONFIG_CMD_CRC32 -+#undef CONFIG_BOOTM_NETBSD -+ -+#define CONFIG_FSL_ESDHC -+#define CONFIG_FSL_USDHC -+#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -+#define USDHC1_BASE_ADDR 0x5B010000 -+#define USDHC2_BASE_ADDR 0x5B020000 -+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -+ -+#define CONFIG_ENV_OVERWRITE -+ -+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -+ -+/* Networking */ -+#define FEC_QUIRK_ENET_MAC -+ -+#define CONFIG_IP_DEFRAG -+#define CONFIG_TFTP_BLOCKSIZE SZ_4K -+#define CONFIG_TFTP_TSIZE -+ -+#define CONFIG_IPADDR 192.168.10.2 -+#define CONFIG_NETMASK 255.255.255.0 -+#define CONFIG_SERVERIP 192.168.10.1 -+ -+#define MEM_LAYOUT_ENV_SETTINGS \ -+ "fdt_addr_r=0x84000000\0" \ -+ "kernel_addr_r=0x82000000\0" \ -+ "ramdisk_addr_r=0x84100000\0" -+ -+#ifdef CONFIG_AHAB_BOOT -+#define AHAB_ENV "sec_boot=yes\0" -+#else -+#define AHAB_ENV "sec_boot=no\0" -+#endif -+ -+/* Boot M4 */ -+#define M4_BOOT_ENV \ -+ "m4_0_image=m4_0.bin\0" \ -+ "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ -+ "${m4_0_image}\0" \ -+ "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ -+ -+#define MFG_NAND_PARTITION "" -+ -+#define BOOT_TARGET_DEVICES(func) \ -+ func(MMC, mmc, 0) \ -+ func(MMC, mmc, 1) \ -+ func(DHCP, dhcp, na) -+#include -+#undef BOOTENV_RUN_NET_USB_START -+#define BOOTENV_RUN_NET_USB_START "" -+ -+#define CONFIG_MFG_ENV_SETTINGS \ -+ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ -+ "rdinit=/linuxrc g_mass_storage.stall=0 " \ -+ "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ -+ "g_mass_storage.idProduct=0x37FF " \ -+ "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \ -+ "${vidargs} clk_ignore_unused\0" \ -+ "initrd_addr=0x83800000\0" \ -+ "initrd_high=0xffffffff\0" \ -+ "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ -+ "${fdt_addr};\0" \ -+ -+/* Initial environment variables */ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ AHAB_ENV \ -+ BOOTENV \ -+ CONFIG_MFG_ENV_SETTINGS \ -+ M4_BOOT_ENV \ -+ MEM_LAYOUT_ENV_SETTINGS \ -+ "boot_fdt=try\0" \ -+ "bootscript=echo Running bootscript from mmc ...; source\0" \ -+ "console=ttyLP3 earlycon\0" \ -+ "fdt_addr=0x83000000\0" \ -+ "fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ -+ "fdt_high=0xffffffffffffffff\0" \ -+ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ -+ "image=Image\0" \ -+ "initrd_addr=0x83800000\0" \ -+ "initrd_high=0xffffffffffffffff\0" \ -+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ -+ "${script};\0" \ -+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ -+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ -+ "mmcargs=setenv bootargs console=${console},${baudrate} " \ -+ "root=PARTUUID=${uuid} rootwait " \ -+ "mmcautodetect=yes\0" \ -+ "mmcboot=echo Booting from mmc ...; " \ -+ "run finduuid; run mmcargs; " \ -+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ -+ "if run loadfdt; then " \ -+ "booti ${loadaddr} - ${fdt_addr}; " \ -+ "else " \ -+ "echo WARN: Cannot load the DT; " \ -+ "fi; " \ -+ "else " \ -+ "echo wait for boot; " \ -+ "fi;\0" \ -+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ -+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ -+ "netargs=setenv bootargs console=${console},${baudrate} " \ -+ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ -+ "${vidargs}\0" \ -+ "netboot=echo Booting from net ...; " \ -+ "run netargs; " \ -+ "if test ${ip_dyn} = yes; then " \ -+ "setenv get_cmd dhcp; " \ -+ "else " \ -+ "setenv get_cmd tftp; " \ -+ "fi; " \ -+ "${get_cmd} ${loadaddr} ${image}; " \ -+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ -+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ -+ "booti ${loadaddr} - ${fdt_addr}; " \ -+ "else " \ -+ "echo WARN: Cannot load the DT; " \ -+ "fi; " \ -+ "else " \ -+ "booti; " \ -+ "fi;\0" \ -+ "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ -+ "colibri-imx8qxp/${fdt_file}; booti ${loadaddr} - " \ -+ "${fdt_addr}\0" \ -+ "panel=NULL\0" \ -+ "script=boot.scr\0" \ -+ "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" -+ -+#undef CONFIG_BOOTCOMMAND -+#define CONFIG_BOOTCOMMAND \ -+ "mmc dev ${mmcdev}; if mmc rescan; then " \ -+ "if run loadbootscript; then " \ -+ "run bootscript; " \ -+ "else " \ -+ "if run loadimage; then " \ -+ "run mmcboot; " \ -+ "else run netboot; " \ -+ "fi; " \ -+ "fi; " \ -+ "else booti ${loadaddr} - ${fdt_addr}; fi" -+ -+/* Link Definitions */ -+#define CONFIG_LOADADDR 0x80280000 -+ -+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -+ -+#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 -+ -+#define CONFIG_SYS_MEMTEST_START 0x88000000 -+#define CONFIG_SYS_MEMTEST_END 0x89000000 -+ -+/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -+#define CONFIG_ENV_SIZE SZ_8K -+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ -+ CONFIG_TDX_CFG_BLOCK_OFFSET) -+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ -+#define CONFIG_SYS_MMC_ENV_PART 1 -+ -+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -+ -+/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ -+#define CONFIG_SYS_FSL_USDHC_NUM 2 -+ -+/* Size of malloc() pool */ -+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) -+ -+#define CONFIG_SYS_SDRAM_BASE 0x80000000 -+#define PHYS_SDRAM_1 0x80000000 -+#define PHYS_SDRAM_2 0x880000000 -+#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ -+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ -+ -+/* Serial */ -+#define CONFIG_BAUDRATE 115200 -+ -+/* Monitor Command Prompt */ -+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -+#define CONFIG_SYS_CBSIZE SZ_2K -+#define CONFIG_SYS_MAXARGS 64 -+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ -+ sizeof(CONFIG_SYS_PROMPT) + 16) -+ -+/* Generic Timer Definitions */ -+#define COUNTER_FREQUENCY 8000000 /* 8MHz */ -+ -+#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 -+#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ -+ -+#endif /* __COLIBRI_IMX8QXP_H */ --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0009-MLK-16560-1-imx8-Configure-sids-based-on-iommu-prope.patch b/recipes-bsp/u-boot-mainline/files/0009-MLK-16560-1-imx8-Configure-sids-based-on-iommu-prope.patch new file mode 100644 index 0000000..94a54cc --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0009-MLK-16560-1-imx8-Configure-sids-based-on-iommu-prope.patch @@ -0,0 +1,120 @@ +From dd44f99dc42905f17bc72832b9b2de391441e78b Mon Sep 17 00:00:00 2001 +From: Ye Li +Date: Mon, 16 Apr 2018 00:27:31 -0700 +Subject: [PATCH 09/15] MLK-16560-1: imx8: Configure sids based on iommu + properties in dtb + +Use streamids specified in dtb because they need to match anyway. This +removes the need to rebuild uboot for stream id assignments. + +Signed-off-by: Leonard Crestez +Reviewed-by: Ye Li +Acked-by: Peng Fan +(cherry picked from downstream commit 3caa05e6dc973b8710642f27f834bf022fbb65b4) +--- + arch/arm/mach-imx/imx8/cpu.c | 85 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 85 insertions(+) + +diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c +index 7f2dd2166b..4eb15de93e 100644 +--- a/arch/arm/mach-imx/imx8/cpu.c ++++ b/arch/arm/mach-imx/imx8/cpu.c +@@ -299,10 +299,95 @@ static void update_fdt_with_owned_resources(void *blob) + } + } + } ++#endif ++ ++#ifdef CONFIG_IMX_SMMU ++static int get_srsc_from_fdt_node_power_domain(void *blob, int device_offset) ++{ ++ const fdt32_t *prop; ++ int pdnode_offset; ++ ++ prop = fdt_getprop(blob, device_offset, "power-domains", NULL); ++ if (!prop) { ++ debug("node %s has no power-domains\n", ++ fdt_get_name(blob, device_offset, NULL)); ++ return -ENOENT; ++ } ++ ++ pdnode_offset = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*prop)); ++ if (pdnode_offset < 0) { ++ pr_err("failed to fetch node %s power-domain", ++ fdt_get_name(blob, device_offset, NULL)); ++ return pdnode_offset; ++ } ++ ++ return fdtdec_get_uint(blob, pdnode_offset, "reg", -ENOENT); ++} ++ ++static int config_smmu_resource_sid(int rsrc, int sid) ++{ ++ sc_err_t err; ++ ++ err = sc_rm_set_master_sid(-1, rsrc, sid); ++ debug("set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err); ++ if (err != SC_ERR_NONE) { ++ pr_err("fail set_master_sid rsrc=%d sid=0x%x err=%d", rsrc, sid, err); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int config_smmu_fdt_device_sid(void *blob, int device_offset, int sid) ++{ ++ int rsrc; ++ const char *name = fdt_get_name(blob, device_offset, NULL); + ++ rsrc = get_srsc_from_fdt_node_power_domain(blob, device_offset); ++ debug("configure node %s sid 0x%x rsrc=%d\n", name, sid, rsrc); ++ if (rsrc < 0) { ++ debug("failed to determine SC_R_* for node %s\n", name); ++ return rsrc; ++ } ++ ++ return config_smmu_resource_sid(rsrc, sid); ++} ++ ++/* assign master sid based on iommu properties in fdt */ ++static int config_smmu_fdt(void *blob) ++{ ++ int offset, proplen; ++ const fdt32_t *prop; ++ const char *name; ++ ++ offset = 0; ++ while ((offset = fdt_next_node(blob, offset, NULL)) > 0) ++ { ++ name = fdt_get_name(blob, offset, NULL); ++ prop = fdt_getprop(blob, offset, "iommus", &proplen); ++ if (!prop) ++ continue; ++ debug("node %s iommus proplen %d\n", name, proplen); ++ ++ if (proplen == 12) { ++ int sid = fdt32_to_cpu(prop[1]); ++ config_smmu_fdt_device_sid(blob, offset, sid); ++ } else if (proplen != 4) { ++ debug("node %s ignore unexpected iommus proplen=%d\n", name, proplen); ++ } ++ } ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_OF_SYSTEM_SETUP + int ft_system_setup(void *blob, bd_t *bd) + { + update_fdt_with_owned_resources(blob); ++#ifdef CONFIG_IMX_SMMU ++ config_smmu_fdt(blob); ++#endif + + return 0; + } +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0009-board-toradex-drop-support.arm-maintainer-email.patch b/recipes-bsp/u-boot-mainline/files/0009-board-toradex-drop-support.arm-maintainer-email.patch deleted file mode 100644 index 2fdca85..0000000 --- a/recipes-bsp/u-boot-mainline/files/0009-board-toradex-drop-support.arm-maintainer-email.patch +++ /dev/null @@ -1,42 +0,0 @@ -From f381404c0c1bdeb981c515f62b3a6fde1ceaa73d Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Tue, 23 Apr 2019 12:55:30 +0200 -Subject: [PATCH 09/19] board: toradex: drop support.arm maintainer email - -Drop Toradex ARM Support from maintainer email -list as this just clogs our support ticketing system. - -Signed-off-by: Marcel Ziswiler -Acked-by: Stefan Agner - -Series-to: u-boot@lists.denx.de ---- - board/toradex/colibri-imx6ull/MAINTAINERS | 1 - - board/toradex/colibri_imx7/MAINTAINERS | 1 - - 2 files changed, 2 deletions(-) - -diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS -index 7cda555984..626c1f94f9 100644 ---- a/board/toradex/colibri-imx6ull/MAINTAINERS -+++ b/board/toradex/colibri-imx6ull/MAINTAINERS -@@ -1,6 +1,5 @@ - Colibri iMX6ULL - M: Stefan Agner --M: Toradex ARM Support - W: http://developer.toradex.com/software/linux/linux-software - W: https://www.toradex.com/community - S: Maintained -diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS -index f55f8045f4..cd0f9c9b2d 100644 ---- a/board/toradex/colibri_imx7/MAINTAINERS -+++ b/board/toradex/colibri_imx7/MAINTAINERS -@@ -1,6 +1,5 @@ - Colibri iMX7 - M: Stefan Agner --M: Toradex ARM Support - W: http://developer.toradex.com/software/linux/linux-software - W: https://www.toradex.com/community - S: Maintained --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0010-apalis-imx8-enable-of_system_setup.patch b/recipes-bsp/u-boot-mainline/files/0010-apalis-imx8-enable-of_system_setup.patch new file mode 100644 index 0000000..755fea9 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0010-apalis-imx8-enable-of_system_setup.patch @@ -0,0 +1,25 @@ +From f028b7765dab1855cc26bca88c19feac7196358f Mon Sep 17 00:00:00 2001 +From: Marcel Ziswiler +Date: Thu, 30 May 2019 18:55:05 +0300 +Subject: [PATCH 10/15] apalis-imx8: enable of_system_setup + +Signed-off-by: Marcel Ziswiler +--- + configs/apalis-imx8qm_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig +index 5e6b89ad9d..d7dfc4a27b 100644 +--- a/configs/apalis-imx8qm_defconfig ++++ b/configs/apalis-imx8qm_defconfig +@@ -7,6 +7,7 @@ CONFIG_TARGET_APALIS_IMX8=y + CONFIG_NR_DRAM_BANKS=3 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_FIT=y ++CONFIG_OF_SYSTEM_SETUP=y + CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg" + CONFIG_LOG=y + CONFIG_VERSION_VARIABLE=y +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0010-misc-imx8-add-sc_misc_get_temp.patch b/recipes-bsp/u-boot-mainline/files/0010-misc-imx8-add-sc_misc_get_temp.patch deleted file mode 100644 index fd50211..0000000 --- a/recipes-bsp/u-boot-mainline/files/0010-misc-imx8-add-sc_misc_get_temp.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 286d5ccf4ab601c8b93be40acaaeb4af6f6b2d49 Mon Sep 17 00:00:00 2001 -From: Peng Fan -Date: Fri, 12 Apr 2019 07:55:00 +0000 -Subject: [PATCH 10/19] misc: imx8: add sc_misc_get_temp - -Add sc_misc_get_temp to support get temperature - -Signed-off-by: Peng Fan ---- - arch/arm/include/asm/arch-imx8/sci/sci.h | 2 ++ - arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 1 + - drivers/misc/imx8/scu_api.c | 28 +++++++++++++++++++++++ - 3 files changed, 31 insertions(+) - -diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h -index 97377697f0..901b90d705 100644 ---- a/arch/arm/include/asm/arch-imx8/sci/sci.h -+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h -@@ -72,6 +72,8 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); - void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); - void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); - int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); -+int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, -+ s16 *celsius, s8 *tenths); - - /* RM API */ - sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); -diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h -index 5d17b553d7..3629eb68d7 100644 ---- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h -+++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h -@@ -26,5 +26,6 @@ - #define SC_MISC_REL_CONTAINER 2U /* Release container */ - - typedef u8 sc_misc_boot_status_t; -+typedef u8 sc_misc_temp_t; - - #endif /* SC_MISC_API_H */ -diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c -index d9c4d5d784..031bc0048b 100644 ---- a/drivers/misc/imx8/scu_api.c -+++ b/drivers/misc/imx8/scu_api.c -@@ -273,6 +273,34 @@ int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val) - return 0; - } - -+int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, -+ s16 *celsius, s8 *tenths) -+{ -+ struct udevice *dev = gd->arch.scu_dev; -+ int size = sizeof(struct sc_rpc_msg_s); -+ struct sc_rpc_msg_s msg; -+ int ret; -+ -+ RPC_VER(&msg) = SC_RPC_VERSION; -+ RPC_SVC(&msg) = (u8)SC_RPC_SVC_MISC; -+ RPC_FUNC(&msg) = (u8)MISC_FUNC_GET_TEMP; -+ RPC_U16(&msg, 0U) = (u16)resource; -+ RPC_U8(&msg, 2U) = (u8)temp; -+ RPC_SIZE(&msg) = 2U; -+ -+ ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); -+ if (ret < 0) -+ return ret; -+ -+ if (celsius) -+ *celsius = RPC_I16(&msg, 0U); -+ -+ if (tenths) -+ *tenths = RPC_I8(&msg, 2U); -+ -+ return 0; -+} -+ - /* RM */ - sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) - { --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0011-MLK-17205-1-video-imx-hdp-Adding-support-for-HDP-fir.patch b/recipes-bsp/u-boot-mainline/files/0011-MLK-17205-1-video-imx-hdp-Adding-support-for-HDP-fir.patch new file mode 100644 index 0000000..956ebe5 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0011-MLK-17205-1-video-imx-hdp-Adding-support-for-HDP-fir.patch @@ -0,0 +1,2560 @@ +From 94ed34cb71d660718acae960328c510f71fbf3dc Mon Sep 17 00:00:00 2001 +From: Oliver Brown +Date: Wed, 13 Dec 2017 17:09:14 -0600 +Subject: [PATCH 11/15] MLK-17205-1 video: imx: hdp: Adding support for HDP + firmware loading + +This adds a command to load the HDP firmware and supporting libraries. + +Signed-off-by: Oliver Brown +(cherry picked from downstream commit 94c9c7022c5b6cffb74bb2e34336cffc2790d0d8) +(cherry picked from downstream commit 21edff320e763585ebc6ab2d997c994561b69292) +--- + drivers/video/Makefile | 3 + + drivers/video/imx/Makefile | 1 + + drivers/video/imx/hdp/API_General.c | 477 ++++++++++++++++++++++++++++++++ + drivers/video/imx/hdp/API_General.h | 302 ++++++++++++++++++++ + drivers/video/imx/hdp/Makefile | 1 + + drivers/video/imx/hdp/address.h | 109 ++++++++ + drivers/video/imx/hdp/apb_cfg.h | 185 +++++++++++++ + drivers/video/imx/hdp/externs.h | 81 ++++++ + drivers/video/imx/hdp/general_handler.h | 162 +++++++++++ + drivers/video/imx/hdp/opcodes.h | 115 ++++++++ + drivers/video/imx/hdp/test_base_sw.c | 181 ++++++++++++ + drivers/video/imx/hdp/util.c | 329 ++++++++++++++++++++++ + drivers/video/imx/hdp/util.h | 278 +++++++++++++++++++ + drivers/video/imx/hdp_load.c | 107 +++++++ + drivers/video/imx/scfw_utils.h | 90 ++++++ + 15 files changed, 2421 insertions(+) + create mode 100644 drivers/video/imx/hdp/API_General.c + create mode 100644 drivers/video/imx/hdp/API_General.h + create mode 100644 drivers/video/imx/hdp/Makefile + create mode 100644 drivers/video/imx/hdp/address.h + create mode 100644 drivers/video/imx/hdp/apb_cfg.h + create mode 100644 drivers/video/imx/hdp/externs.h + create mode 100644 drivers/video/imx/hdp/general_handler.h + create mode 100644 drivers/video/imx/hdp/opcodes.h + create mode 100644 drivers/video/imx/hdp/test_base_sw.c + create mode 100644 drivers/video/imx/hdp/util.c + create mode 100644 drivers/video/imx/hdp/util.h + create mode 100644 drivers/video/imx/hdp_load.c + create mode 100644 drivers/video/imx/scfw_utils.h + +diff --git a/drivers/video/Makefile b/drivers/video/Makefile +index 349a207035..fdc57c71da 100644 +--- a/drivers/video/Makefile ++++ b/drivers/video/Makefile +@@ -65,3 +65,6 @@ obj-$(CONFIG_VIDEO_VESA) += vesa.o + + obj-y += bridge/ + obj-y += sunxi/ ++ ++UBOOTINCLUDE += -I$(srctree)/drivers/video/imx/hdp ++obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += imx/hdp_load.o imx/hdp/ +diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile +index 179ea651fe..0f9d85f917 100644 +--- a/drivers/video/imx/Makefile ++++ b/drivers/video/imx/Makefile +@@ -4,3 +4,4 @@ + # Wolfgang Denk, DENX Software Engineering, wd@denx.de. + + obj-y += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o ++obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += hdp_load.o hdp/ +diff --git a/drivers/video/imx/hdp/API_General.c b/drivers/video/imx/hdp/API_General.c +new file mode 100644 +index 0000000000..83458d7fae +--- /dev/null ++++ b/drivers/video/imx/hdp/API_General.c +@@ -0,0 +1,477 @@ ++/****************************************************************************** ++ * ++ * Copyright (C) 2016-2017 Cadence Design Systems, Inc. ++ * All rights reserved worldwide. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * ++ * 3. Neither the name of the copyright holder nor the names of its contributors ++ * may be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ++ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", ++ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED ++ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Copyright 2017 NXP ++ * ++ ****************************************************************************** ++ * ++ * API_General.c ++ * ++ ****************************************************************************** ++ */ ++ ++#include "API_General.h" ++#include "util.h" ++#ifndef __UBOOT__ ++#include ++#endif ++#include "address.h" ++#include "apb_cfg.h" ++#include "opcodes.h" ++#include "general_handler.h" ++#include "externs.h" ++#ifndef __UBOOT__ ++#include ++#endif ++ ++extern state_struct state; ++ ++void cdn_api_init(void) ++{ ++ memset(&state, 0, sizeof(state_struct)); ++} ++ ++CDN_API_STATUS cdn_api_loadfirmware(unsigned char *imem, int imemsize, ++ unsigned char *dmem, int dmemsize) ++{ ++ int i; ++ for (i = 0; i < imemsize; i += 4) ++ if (cdn_apb_write(ADDR_IMEM + i, ++ (unsigned int)imem[i] << 0 | ++ (unsigned int)imem[i + 1] << 8 | ++ (unsigned int)imem[i + 2] << 16 | ++ (unsigned int)imem[i + 3] << 24)) ++ return CDN_ERR; ++ for (i = 0; i < dmemsize; i += 4) ++ if (cdn_apb_write(ADDR_DMEM + i, ++ (unsigned int)dmem[i] << 0 | ++ (unsigned int)dmem[i + 1] << 8 | ++ (unsigned int)dmem[i + 2] << 16 | ++ (unsigned int)dmem[i + 3] << 24)) ++ return CDN_ERR; ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_general_test_echo(unsigned int val, ++ CDN_BUS_TYPE bus_type) ++{ ++ CDN_API_STATUS ret; ++ if (!state.running) { ++ if (!internal_apb_available()) ++ return CDN_BSY; ++ state.bus_type = bus_type; ++ state.rxenable = 1; ++ internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO, ++ 1, 4, val); ++ return CDN_STARTED; ++ } ++ if (state.txenable && !internal_mbox_tx_process().txend) ++ return CDN_BSY; ++ if (state.rxenable && !internal_mbox_rx_process().rxend) ++ return CDN_BSY; ++ ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO); ++ if (ret != CDN_OK) { ++ state.running = 0; ++ return ret; ++ } ++ state.running = 0; ++ if (val != internal_betoi(state.rxbuffer + INTERNAL_CMD_HEAD_SIZE, 4)) ++ return CDN_ERR; ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_general_test_echo_blocking(unsigned int val, ++ CDN_BUS_TYPE bus_type) ++{ ++ internal_block_function(cdn_api_general_test_echo(val, bus_type)); ++} ++ ++CDN_API_STATUS cdn_api_general_test_echo_ext(uint8_t const *msg, uint8_t *resp, ++ uint16_t num_bytes, ++ CDN_BUS_TYPE bus_type) ++{ ++ CDN_API_STATUS ret; ++ ++ if (!msg || !resp) ++ return CDN_ERR; ++ ++ if ((num_bytes > GENERAL_TEST_ECHO_MAX_PAYLOAD) || ++ (num_bytes < GENERAL_TEST_ECHO_MIN_PAYLOAD)) ++ return CDN_ERR; ++ ++ if (!state.running) { ++ if (!internal_apb_available()) ++ return CDN_BSY; ++ ++ state.bus_type = bus_type; ++ state.rxenable = 1; ++ ++ internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO, ++ 1, -num_bytes, msg); ++ ++ return CDN_STARTED; ++ } ++ ++ if (state.txenable && !internal_mbox_tx_process().txend) ++ return CDN_BSY; ++ ++ if (state.rxenable && !internal_mbox_rx_process().rxend) ++ return CDN_BSY; ++ ++ ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO); ++ ++ if (ret != CDN_OK) { ++ state.running = 0; ++ return ret; ++ } ++ ++ state.running = 0; ++ ++ memcpy(resp, state.rxbuffer + INTERNAL_CMD_HEAD_SIZE, num_bytes); ++ ++ if (memcmp(msg, resp, num_bytes) != 0) ++ return CDN_ERR; ++ ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_general_test_echo_ext_blocking(uint8_t const *msg, ++ uint8_t *resp, ++ uint16_t num_bytes, ++ CDN_BUS_TYPE bus_type) ++{ ++ internal_block_function(cdn_api_general_test_echo_ext ++ (msg, resp, num_bytes, bus_type) ++ ); ++} ++ ++CDN_API_STATUS cdn_api_general_getcurversion(unsigned short *ver, ++ unsigned short *verlib) ++{ ++ unsigned int vh, vl, vlh, vll; ++ if (cdn_apb_read(VER_L << 2, &vl)) ++ return CDN_ERR; ++ if (cdn_apb_read(VER_H << 2, &vh)) ++ return CDN_ERR; ++ if (cdn_apb_read(VER_LIB_L_ADDR << 2, &vll)) ++ return CDN_ERR; ++ if (cdn_apb_read(VER_LIB_H_ADDR << 2, &vlh)) ++ return CDN_ERR; ++ *ver = F_VER_MSB_RD(vh) << 8 | F_VER_LSB_RD(vl); ++ *verlib = F_SW_LIB_VER_H_RD(vlh) << 8 | F_SW_LIB_VER_L_RD(vll); ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_get_event(uint32_t *events) ++{ ++ uint32_t evt[4] = { 0 }; ++ ++ if (!events) { ++ printf("events pointer is NULL!\n"); ++ return CDN_ERR; ++ } ++ ++ if (cdn_apb_read(SW_EVENTS0 << 2, &evt[0]) || ++ cdn_apb_read(SW_EVENTS1 << 2, &evt[1]) || ++ cdn_apb_read(SW_EVENTS2 << 2, &evt[2]) || ++ cdn_apb_read(SW_EVENTS3 << 2, &evt[3])) { ++ printf("Failed to read events registers.\n"); ++ return CDN_ERR; ++ } ++ ++ *events = (evt[0] & 0xFF) ++ | ((evt[1] & 0xFF) << 8) ++ | ((evt[2] & 0xFF) << 16) ++ | ((evt[3] & 0xFF) << 24); ++ ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_get_debug_reg_val(uint16_t *val) ++{ ++ uint32_t dbg[2] = { 0 }; ++ ++ if (!val) { ++ printf("val pointer is NULL!\n"); ++ return CDN_ERR; ++ } ++ ++ if (cdn_apb_read(SW_DEBUG_L << 2, &dbg[0]) || ++ cdn_apb_read(SW_DEBUG_H << 2, &dbg[1])) { ++ printf("Failed to read debug registers.\n"); ++ return CDN_ERR; ++ } ++ ++ *val = (uint16_t) ((dbg[0] & 0xFF) | ((dbg[1] & 0xFF) << 8)); ++ ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_checkalive(void) ++{ ++ static unsigned int alive; ++ unsigned int newalive; ++ if (cdn_apb_read(KEEP_ALIVE << 2, &newalive)) ++ return CDN_ERR; ++ if (alive == newalive) ++ return CDN_BSY; ++ alive = newalive; ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_checkalive_blocking(void) ++{ ++ internal_block_function(cdn_api_checkalive()); ++} ++ ++CDN_API_STATUS cdn_api_maincontrol(unsigned char mode, unsigned char *resp) ++{ ++ if (!state.running) { ++ if (!internal_apb_available()) ++ return CDN_BSY; ++ state.bus_type = CDN_BUS_TYPE_APB; ++ state.rxenable = 1; ++ internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, ++ GENERAL_MAIN_CONTROL, 1, 1, mode); ++ return CDN_STARTED; ++ } ++ INTERNAL_PROCESS_MESSAGES; ++ internal_opcode_ok_or_return(MB_MODULE_ID_GENERAL, ++ GENERAL_MAIN_CONTROL_RESP); ++ internal_readmsg(1, 1, resp); ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_maincontrol_blocking(unsigned char mode, ++ unsigned char *resp) ++{ ++ internal_block_function(cdn_api_maincontrol(mode, resp)); ++} ++ ++CDN_API_STATUS cdn_api_apbconf(uint8_t dpcd_bus_sel, uint8_t dpcd_bus_lock, ++ uint8_t hdcp_bus_sel, uint8_t hdcp_bus_lock, ++ uint8_t capb_bus_sel, uint8_t capb_bus_lock, ++ uint8_t *dpcd_resp, uint8_t *hdcp_resp, ++ uint8_t *capb_resp) ++{ ++ uint8_t resp; ++ uint8_t set = 0; ++ ++ if (!state.running) { ++ if (!internal_apb_available()) ++ return CDN_BSY; ++ ++ state.bus_type = CDN_BUS_TYPE_APB; ++ state.rxenable = 1; ++ ++ set |= (dpcd_bus_sel) ++ ? (1 << GENERAL_BUS_SETTINGS_DPCD_BUS_BIT) ++ : 0; ++ set |= (dpcd_bus_lock) ++ ? (1 << GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT) ++ : 0; ++ set |= (hdcp_bus_sel) ++ ? (1 << GENERAL_BUS_SETTINGS_HDCP_BUS_BIT) ++ : 0; ++ set |= (hdcp_bus_lock) ++ ? (1 << GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT) ++ : 0; ++ set |= (capb_bus_sel) ++ ? (1 << GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT) ++ : 0; ++ set |= (capb_bus_lock) ++ ? (1 << GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT) ++ : 0; ++ ++ internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, ++ GENERAL_BUS_SETTINGS, 1, 1, set); ++ ++ return CDN_STARTED; ++ } ++ ++ INTERNAL_PROCESS_MESSAGES; ++ internal_opcode_ok_or_return(MB_MODULE_ID_GENERAL, ++ GENERAL_BUS_SETTINGS_RESP); ++ ++ /* Read one one-byte response */ ++ internal_readmsg(1, 1, &resp); ++ ++ *dpcd_resp = ++ (resp & (1 << GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT)) ? 1 : 0; ++ *hdcp_resp = ++ (resp & (1 << GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT)) ? 1 : 0; ++ *capb_resp = ++ (resp & (1 << GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT)) ? 1 : 0; ++ ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_apbconf_blocking(uint8_t dpcd_bus_sel, ++ uint8_t dpcd_bus_lock, ++ uint8_t hdcp_bus_sel, ++ uint8_t hdcp_bus_lock, ++ uint8_t capb_bus_sel, ++ uint8_t capb_bus_lock, ++ uint8_t *dpcd_resp, ++ uint8_t *hdcp_resp, ++ uint8_t *capb_resp) ++{ ++ internal_block_function(cdn_api_apbconf(dpcd_bus_sel, dpcd_bus_lock, ++ hdcp_bus_sel, hdcp_bus_lock, ++ capb_bus_sel, capb_bus_lock, ++ dpcd_resp, hdcp_resp, ++ capb_resp)); ++} ++ ++CDN_API_STATUS cdn_api_setclock(unsigned char mhz) ++{ ++ return cdn_apb_write(SW_CLK_H << 2, mhz); ++} ++ ++CDN_API_STATUS cdn_api_general_read_register(unsigned int addr, ++ GENERAL_READ_REGISTER_RESPONSE ++ *resp) ++{ ++ CDN_API_STATUS ret; ++ if (!state.running) { ++ if (!internal_apb_available()) ++ return CDN_BSY; ++ internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, ++ GENERAL_READ_REGISTER, 1, 4, addr); ++ state.bus_type = CDN_BUS_TYPE_APB; ++ state.rxenable = 1; ++ return CDN_STARTED; ++ } ++ INTERNAL_PROCESS_MESSAGES; ++ ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, ++ GENERAL_READ_REGISTER_RESP); ++ if (ret != CDN_OK) ++ return ret; ++ internal_readmsg(2, 4, &resp->addr, 4, &resp->val); ++ return CDN_OK; ++} ++ ++CDN_API_STATUS ++cdn_api_general_read_register_blocking(unsigned int addr, ++ GENERAL_READ_REGISTER_RESPONSE *resp) ++{ ++ internal_block_function(cdn_api_general_read_register(addr, resp)); ++} ++ ++CDN_API_STATUS cdn_api_general_write_register(unsigned int addr, ++ unsigned int val) ++{ ++ if (!state.running) { ++ if (!internal_apb_available()) ++ return CDN_BSY; ++ internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, ++ GENERAL_WRITE_REGISTER, 2, 4, addr, 4, ++ val); ++ state.bus_type = CDN_BUS_TYPE_APB; ++ return CDN_STARTED; ++ } ++ INTERNAL_PROCESS_MESSAGES; ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_general_write_register_blocking(unsigned int addr, ++ unsigned int val) ++{ ++ internal_block_function(cdn_api_general_write_register(addr, val)); ++} ++ ++CDN_API_STATUS cdn_api_general_write_field(unsigned int addr, ++ unsigned char startbit, ++ unsigned char bitsno, ++ unsigned int val) ++{ ++ if (!state.running) { ++ if (!internal_apb_available()) ++ return CDN_BSY; ++ internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_WRITE_FIELD, ++ 4, 4, addr, 1, startbit, 1, bitsno, 4, ++ val); ++ state.bus_type = CDN_BUS_TYPE_APB; ++ return CDN_STARTED; ++ } ++ INTERNAL_PROCESS_MESSAGES; ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_general_write_field_blocking(unsigned int addr, ++ unsigned char startbit, ++ unsigned char bitsno, ++ unsigned int val) ++{ ++ internal_block_function(cdn_api_general_write_field ++ (addr, startbit, bitsno, val)); ++} ++ ++CDN_API_STATUS cdn_api_general_phy_test_access(uint8_t *resp) ++{ ++ CDN_API_STATUS ret; ++ ++ *resp = 0; ++ ++ if (!state.running) { ++ if (!internal_apb_available()) ++ return CDN_BSY; ++ ++ internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ACCESS, ++ 0); ++ state.bus_type = CDN_BUS_TYPE_APB; ++ state.rxenable = 1; ++ ++ return CDN_STARTED; ++ } ++ ++ INTERNAL_PROCESS_MESSAGES; ++ ++ ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ACCESS); ++ ++ if (ret != CDN_OK) ++ return ret; ++ ++ internal_readmsg(1, 1, resp); ++ ++ return CDN_OK; ++} ++ ++CDN_API_STATUS cdn_api_general_phy_test_access_blocking(uint8_t *resp) ++{ ++ internal_block_function(cdn_api_general_phy_test_access(resp)); ++} +diff --git a/drivers/video/imx/hdp/API_General.h b/drivers/video/imx/hdp/API_General.h +new file mode 100644 +index 0000000000..44e16e8ad7 +--- /dev/null ++++ b/drivers/video/imx/hdp/API_General.h +@@ -0,0 +1,302 @@ ++/****************************************************************************** ++ * ++ * Copyright (C) 2016-2017 Cadence Design Systems, Inc. ++ * All rights reserved worldwide. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * ++ * 3. Neither the name of the copyright holder nor the names of its contributors ++ * may be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ++ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", ++ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED ++ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Copyright 2017 NXP ++ * ++ ****************************************************************************** ++ * ++ * API_General.h ++ * ++ ****************************************************************************** ++ */ ++ ++#ifndef API_GENERAL_H_ ++#define API_GENERAL_H_ ++ ++#ifndef __UBOOT__ ++#include ++#else ++#include ++#endif ++ ++#define GENERAL_TEST_ECHO_MAX_PAYLOAD 100 ++#define GENERAL_TEST_ECHO_MIN_PAYLOAD 1 ++ ++/** ++ * \addtogroup GENERAL_API ++ * \{ ++ */ ++/** status code returned by API calls */ ++typedef enum { ++ /** operation succedded */ ++ CDN_OK = 0, ++ /** CEC operation succedded */ ++ CDN_CEC_ERR_NONE = 0, ++ /** mailbox is currently sending or receiving data */ ++ CDN_BSY, ++ /** message set up and ready to be sent, no data sent yet */ ++ CDN_STARTED, ++ /** error encountered while reading/writing APB */ ++ CDN_ERR, ++ /** reply returned with bad opcode */ ++ CDN_BAD_OPCODE, ++ /** reply returned with bad module */ ++ CDN_BAD_MODULE, ++ /** reply not supported mode */ ++ CDN_ERROR_NOT_SUPPORTED, ++ /** Invalid argument passed to CEC API function */ ++ CDN_CEC_ERR_INVALID_ARG, ++ /** ++ * TX Buffer for CEC Messages is full. This is applicable only ++ * when TX Buffers for CEC Messages are implemented in the HW. ++ */ ++ CDN_CEC_ERR_TX_BUFF_FULL, ++ /** No Messages in the RX Buffers are present. */ ++ CDN_CEC_ERR_RX_BUFF_EMPTY, ++ /** Timeout during TX operation */ ++ CDN_CEC_ERR_TX_TIMEOUT, ++ /** Timeout during RX operation */ ++ CDN_CEC_ERR_RX_TIMEOUT, ++ /** Data transmision fail. */ ++ CDN_CEC_ERR_TX_FAILED, ++ /** Data reception fail. */ ++ CDN_CEC_ERR_RX_FAILED, ++ /** Operation aborted. */ ++ CDN_CEC_ERR_ABORT, ++ /** All Logical Addresses are in use. */ ++ CDN_CEC_ERR_ALL_LA_IN_USE, ++} CDN_API_STATUS; ++ ++typedef enum { ++ CDN_BUS_TYPE_APB = 0, ++ CDN_BUS_TYPE_SAPB = 1 ++} CDN_BUS_TYPE; ++ ++/** ++ * GENERAL_Read_Register response struct ++ */ ++typedef struct { ++ unsigned int addr; ++ unsigned int val; ++} GENERAL_READ_REGISTER_RESPONSE; ++ ++/** ++ * \brief set up API, must be called before any other API call ++ */ ++void cdn_api_init(void); ++ ++/** ++ * \brief Loads firmware ++ * ++ * \param iMem - pointer to instruction memory ++ * \param imemSize - size of instruction memory buffer ++ * \param dMem - pointer to data memory ++ * \param dmemSize - size of data memory buffer ++ * \return 0 if success, 1 if apb error encountered, 2 if CPU ++ * isn't alive after loading firmware ++ * ++ * This function does not require initialisation by #CDN_API_Init ++ */ ++ ++CDN_API_STATUS cdn_api_loadfirmware(unsigned char *imem, ++ int imemsize, ++ unsigned char *dmem, int dmemsize); ++/** ++ * \brief debug echo command for APB ++ * \param val - value to echo ++ * \return status ++ * ++ * will return #CDN_ERROR if reply message doesn't match request ++ */ ++CDN_API_STATUS cdn_api_general_test_echo(unsigned int val, ++ CDN_BUS_TYPE bus_type); ++ ++/** ++ * \brief blocking version of #CDN_API_General_Test_Echo ++ */ ++CDN_API_STATUS cdn_api_general_test_echo_blocking(unsigned int val, ++ CDN_BUS_TYPE bus_type); ++ ++/** ++ * \brief Extended Echo test for mailbox. ++ * ++ * This test will send msg buffer to firmware's mailbox and ++ * receive it back to the resp buffer. Received data will be ++ * check against data sent and status will be returned as well ++ * as received data. ++ * ++ * \param msg - Pointer to a buffer to send. ++ * \param resp - Pointer to buffer for receiving msg payload back. ++ * \param num_bytes - Number of bytes to send and receive. ++ * \param bus_type Bus type. ++ * \return status ++ * ++ * will return #CDN_ERROR if reply message doesn't match request or if ++ * arguments are invalid. ++ */ ++CDN_API_STATUS cdn_api_general_test_echo_ext(uint8_t const *msg, uint8_t *resp, ++ uint16_t num_bytes, ++ CDN_BUS_TYPE bus_type); ++ ++/** ++ * \brief blocking version of #CDN_API_General_Test_Echo_Ext ++ */ ++CDN_API_STATUS cdn_api_general_test_echo_ext_blocking(uint8_t const *msg, ++ uint8_t *resp, ++ uint16_t num_bytes, ++ CDN_BUS_TYPE bus_type); ++ ++/** ++ * \brief get current version ++ * \param [out] ver - fw version ++ * \param [out] libver - lib version ++ * \return status ++ * ++ * this fucntion does not require #CDN_API_Init ++ */ ++CDN_API_STATUS cdn_api_general_getcurversion(unsigned short *ver, ++ unsigned short *verlib); ++ ++/** ++ * \brief read event value ++ * \param [out] event - pointer to store 32-bit events value ++ * \return status ++ * ++ * this function does not require #CDN_API_Init ++ */ ++CDN_API_STATUS cdn_api_get_event(uint32_t *events); ++ ++/** ++ * \brief read debug register value ++ * \param [out] val - pointer to store 16-bit debug reg value ++ * \return status ++ * ++ * this function does not require #CDN_API_Init ++ */ ++CDN_API_STATUS cdn_api_get_debug_reg_val(uint16_t *val); ++ ++/** ++ * \brief check if KEEP_ALIVE register changed ++ * \return #CDN_BSY if KEEP_ALIVE not changed, #CDN_OK if changed and #CDN_ERR ++ * if error occured while reading ++ */ ++CDN_API_STATUS cdn_api_checkalive(void); ++ ++/** ++ * \breif blocking version of #CDN_API_CheckAlive ++ * blocks untill KEEP_ALIVE register changes or error occurs while reading ++ */ ++CDN_API_STATUS cdn_api_checkalive_blocking(void); ++ ++/** ++ * \brief set cpu to standby or active ++ * \param [in] state - 1 for active, 0 for standby ++ * \return status ++ */ ++CDN_API_STATUS cdn_api_maincontrol(unsigned char mode, unsigned char *resp); ++ ++/** ++ * \breif blocking version of #CDN_API_MainControl ++ */ ++CDN_API_STATUS cdn_api_maincontrol_blocking(unsigned char mode, ++ unsigned char *resp); ++ ++/** ++ * \brief settings for APB ++ * ++ * Sends GENERAL_APB_CONF Command via regular Mailbox. ++ * @param dpcd_bus_sel Set DPCD to use selected bus (0 for APB or 1 for SAPB) ++ * @param dpcd_bus_lock Lock bus type. Aftern that bus type cannot be changed ++ * by using this function. ++ * @param hdcp_bus_sel Same meaning as for DPCD but for HDCP. ++ * @param hdcp_bus_lock Same meaning as for DPCD but for HDCP. ++ * @param capb_bus_sel Same meaning as for DPCD but for Cipher APB. ++ * @param capb_bus_lock Same meaning as for DPCD but for Cipher APB. ++ * @param dpcd_resp [out] Status of the operation. ++ * If set to zero then DPCD bus type was successfuly changed. ++ * If not then error occurred, most likely due to locked DPCD bus. ++ * @param hdcp_resp [out] Same as for DPCD but for HDCP. ++ * @param capb_resp [out] Same as for DPCD but for Cipher APB. ++ * ++ * \return status ++ */ ++CDN_API_STATUS cdn_api_apbconf(uint8_t dpcd_bus_sel, uint8_t dpcd_bus_lock, ++ uint8_t hdcp_bus_sel, uint8_t hdcp_bus_lock, ++ uint8_t capb_bus_sel, uint8_t capb_bus_lock, ++ uint8_t *dpcd_resp, uint8_t *hdcp_resp, ++ uint8_t *capb_resp); ++ ++/** ++ * blocking version of #CDN_API_MainControl ++ */ ++CDN_API_STATUS cdn_api_apbconf_blocking(uint8_t dpcd_bus_sel, ++ uint8_t dpcd_bus_lock, ++ uint8_t hdcp_bus_sel, ++ uint8_t hdcp_bus_lock, ++ uint8_t capb_bus_sel, ++ uint8_t capb_bus_lock, ++ uint8_t *dpcd_resp, ++ uint8_t *hdcp_resp, ++ uint8_t *capb_resp); ++ ++/** ++ * \brief set the xtensa clk, write this api before turn on the cpu ++ */ ++CDN_API_STATUS cdn_api_setclock(unsigned char mhz); ++ ++CDN_API_STATUS cdn_api_general_read_register(unsigned int addr, ++ GENERAL_READ_REGISTER_RESPONSE ++ *resp); ++CDN_API_STATUS ++cdn_api_general_read_register_blocking(unsigned int addr, ++ GENERAL_READ_REGISTER_RESPONSE *resp); ++CDN_API_STATUS cdn_api_general_write_register(unsigned int addr, ++ unsigned int val); ++CDN_API_STATUS cdn_api_general_write_register_blocking(unsigned int addr, ++ unsigned int val); ++CDN_API_STATUS cdn_api_general_write_field(unsigned int addr, ++ unsigned char startbit, ++ unsigned char bitsno, ++ unsigned int val); ++CDN_API_STATUS cdn_api_general_write_field_blocking(unsigned int addr, ++ unsigned char startbit, ++ unsigned char bitsno, ++ unsigned int val); ++CDN_API_STATUS cdn_api_general_phy_test_access(uint8_t *resp); ++CDN_API_STATUS cdn_api_general_phy_test_access_blocking(uint8_t *resp); ++ ++#endif +diff --git a/drivers/video/imx/hdp/Makefile b/drivers/video/imx/hdp/Makefile +new file mode 100644 +index 0000000000..13dcefdee5 +--- /dev/null ++++ b/drivers/video/imx/hdp/Makefile +@@ -0,0 +1 @@ ++obj-y += API_General.o util.o test_base_sw.o +diff --git a/drivers/video/imx/hdp/address.h b/drivers/video/imx/hdp/address.h +new file mode 100644 +index 0000000000..327e7a90e4 +--- /dev/null ++++ b/drivers/video/imx/hdp/address.h +@@ -0,0 +1,109 @@ ++/****************************************************************************** ++ * ++ * Copyright (C) 2016-2017 Cadence Design Systems, Inc. ++ * All rights reserved worldwide. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * ++ * 3. Neither the name of the copyright holder nor the names of its contributors ++ * may be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ++ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", ++ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED ++ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Copyright 2017 NXP ++ * ++ ****************************************************************************** ++ * ++ * address.h ++ * ++ ****************************************************************************** ++ */ ++ ++#ifndef ADDRESS_H_ ++# define ADDRESS_H_ ++ ++# define ADDR_IMEM 0x10000 ++# define ADDR_DMEM 0x20000 ++# define ADDR_CIPHER 0x60000 ++# define BASE_CIPHER 0x600 ++# define ADDR_APB_CFG 0x00000 ++# define BASE_APB_CFG 0x000 ++# define ADDR_SOURCE_AIF_DECODER 0x30000 ++# define BASE_SOURCE_AIF_DECODER 0x300 ++# define ADDR_SOURCE_AIF_SMPL2PCKT 0x30080 ++# define BASE_SOURCE_AIF_SMPL2PCKT 0x300 ++# define ADDR_AIF_ENCODER 0x30000 ++# define BASE_AIF_ENCODER 0x300 ++# define ADDR_SOURCE_PIF 0x30800 ++# define BASE_SOURCE_PIF 0x308 ++# define ADDR_SINK_PIF 0x30800 ++# define BASE_SINK_PIF 0x308 ++# define ADDR_APB_CFG 0x00000 ++# define BASE_APB_CFG 0x000 ++# define ADDR_SOURCE_CSC 0x40000 ++# define BASE_SOURCE_CSC 0x400 ++# define ADDR_UCPU_CFG 0x00000 ++# define BASE_UCPU_CFG 0x000 ++# define ADDR_SOURCE_CAR 0x00900 ++# define BASE_SOURCE_CAR 0x009 ++# define ADDR_SINK_CAR 0x00900 ++# define BASE_SINK_CAR 0x009 ++# define ADDR_CLOCK_METERS 0x00A00 ++# define BASE_CLOCK_METERS 0x00A ++# define ADDR_SOURCE_VIF 0x00b00 ++# define BASE_SOURCE_VIF 0x00b ++# define ADDR_SINK_MHL_HD 0x01000 ++# define ADDR_SINK_VIDEO_HD 0x01800 ++# define BASE_SINK_MHL_HD 0x010 ++# define ADDR_SINK_CORE 0x07800 ++# define BASE_SINK_CORE 0x078 ++# define ADDR_DPTX_PHY 0x02000 ++# define BASE_DPTX_PHY 0x020 ++# define ADDR_DPTX_HPD 0x02100 ++# define BASE_DPTX_HPD 0x021 ++# define ADDR_DPTX_FRAMER 0x02200 ++# define BASE_DPTX_FRAMER 0x022 ++# define ADDR_DPTX_STREAM 0x02200 ++# define BASE_DPTX_STREAM 0x022 ++# define ADDR_DPTX_GLBL 0x02300 ++# define BASE_DPTX_GLBL 0x023 ++# define ADDR_DPTX_HDCP 0x02400 ++# define BASE_DPTX_HDCP 0x024 ++# define ADDR_DP_AUX 0x02800 ++# define BASE_DP_AUX 0x028 ++# define ADDR_CRYPTO 0x05800 ++# define BASE_CRYPTO 0x058 ++# define ADDR_CIPHER 0x60000 ++# define BASE_CIPHER 0x600 ++# define ADDR_SOURCE_MHL_HD 0x01000 ++ ++# define ADDR_AFE (0x20000 * 4) ++# define ADDR_SOURCD_PHY (0x800) ++ ++#endif ++ +diff --git a/drivers/video/imx/hdp/apb_cfg.h b/drivers/video/imx/hdp/apb_cfg.h +new file mode 100644 +index 0000000000..cdcbd76c01 +--- /dev/null ++++ b/drivers/video/imx/hdp/apb_cfg.h +@@ -0,0 +1,185 @@ ++/****************************************************************************** ++ * ++ * Copyright (C) 2016-2017 Cadence Design Systems, Inc. ++ * All rights reserved worldwide. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * ++ * 3. Neither the name of the copyright holder nor the names of its contributors ++ * may be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ++ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", ++ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED ++ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Copyright 2017 NXP ++ * ++ ****************************************************************************** ++ * ++ * This file was auto-generated. Do not edit it manually. ++ * ++ ****************************************************************************** ++ * ++ * apb_cfg.h ++ * ++ ****************************************************************************** ++ */ ++ ++#ifndef APB_CFG_H_ ++#define APB_CFG_H_ ++ ++/* register APB_CTRL */ ++#define APB_CTRL 0 ++#define F_APB_XT_RESET(x) (((x) & ((1 << 1) - 1)) << 0) ++#define F_APB_XT_RESET_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) ++#define F_APB_DRAM_PATH(x) (((x) & ((1 << 1) - 1)) << 1) ++#define F_APB_DRAM_PATH_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) ++#define F_APB_IRAM_PATH(x) (((x) & ((1 << 1) - 1)) << 2) ++#define F_APB_IRAM_PATH_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) ++ ++/* register XT_INT_CTRL */ ++#define XT_INT_CTRL 1 ++#define F_XT_INT_POLARITY(x) (((x) & ((1 << 2) - 1)) << 0) ++#define F_XT_INT_POLARITY_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) ++ ++/* register MAILBOX_FULL_ADDR */ ++#define MAILBOX_FULL_ADDR 2 ++#define F_MAILBOX_FULL(x) (((x) & ((1 << 1) - 1)) << 0) ++#define F_MAILBOX_FULL_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) ++ ++/* register MAILBOX_EMPTY_ADDR */ ++#define MAILBOX_EMPTY_ADDR 3 ++#define F_MAILBOX_EMPTY(x) (((x) & ((1 << 1) - 1)) << 0) ++#define F_MAILBOX_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) ++ ++/* register MAILBOX0_WR_DATA */ ++#define MAILBOX0_WR_DATA 4 ++#define F_MAILBOX0_WR_DATA(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_MAILBOX0_WR_DATA_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register MAILBOX0_RD_DATA */ ++#define MAILBOX0_RD_DATA 5 ++#define F_MAILBOX0_RD_DATA(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_MAILBOX0_RD_DATA_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register KEEP_ALIVE */ ++#define KEEP_ALIVE 6 ++#define F_KEEP_ALIVE_CNT(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_KEEP_ALIVE_CNT_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register VER_L */ ++#define VER_L 7 ++#define F_VER_LSB(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_VER_LSB_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register VER_H */ ++#define VER_H 8 ++#define F_VER_MSB(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_VER_MSB_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register VER_LIB_L_ADDR */ ++#define VER_LIB_L_ADDR 9 ++#define F_SW_LIB_VER_L(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_SW_LIB_VER_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register VER_LIB_H_ADDR */ ++#define VER_LIB_H_ADDR 10 ++#define F_SW_LIB_VER_H(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_SW_LIB_VER_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register SW_DEBUG_L */ ++#define SW_DEBUG_L 11 ++#define F_SW_DEBUG_7_0(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_SW_DEBUG_7_0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register SW_DEBUG_H */ ++#define SW_DEBUG_H 12 ++#define F_SW_DEBUG_15_8(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_SW_DEBUG_15_8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register MAILBOX_INT_MASK */ ++#define MAILBOX_INT_MASK 13 ++#define F_MAILBOX_INT_MASK(x) (((x) & ((1 << 2) - 1)) << 0) ++#define F_MAILBOX_INT_MASK_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) ++ ++/* register MAILBOX_INT_STATUS */ ++#define MAILBOX_INT_STATUS 14 ++#define F_MAILBOX_INT_STATUS(x) (((x) & ((1 << 2) - 1)) << 0) ++#define F_MAILBOX_INT_STATUS_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) ++ ++/* register SW_CLK_L */ ++#define SW_CLK_L 15 ++#define F_SW_CLOCK_VAL_L(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_SW_CLOCK_VAL_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register SW_CLK_H */ ++#define SW_CLK_H 16 ++#define F_SW_CLOCK_VAL_H(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_SW_CLOCK_VAL_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register SW_EVENTS0 */ ++#define SW_EVENTS0 17 ++#define F_SW_EVENTS7_0(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_SW_EVENTS7_0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register SW_EVENTS1 */ ++#define SW_EVENTS1 18 ++#define F_SW_EVENTS15_8(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_SW_EVENTS15_8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register SW_EVENTS2 */ ++#define SW_EVENTS2 19 ++#define F_SW_EVENTS23_16(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_SW_EVENTS23_16_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register SW_EVENTS3 */ ++#define SW_EVENTS3 20 ++#define F_SW_EVENTS31_24(x) (((x) & ((1 << 8) - 1)) << 0) ++#define F_SW_EVENTS31_24_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) ++ ++/* register XT_OCD_CTRL */ ++#define XT_OCD_CTRL 24 ++#define F_XT_DRESET(x) (((x) & ((1 << 1) - 1)) << 0) ++#define F_XT_DRESET_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) ++#define F_XT_OCDHALTONRESET(x) (((x) & ((1 << 1) - 1)) << 1) ++#define F_XT_OCDHALTONRESET_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) ++ ++/* register XT_OCD_CTRL_RO */ ++#define XT_OCD_CTRL_RO 25 ++#define F_XT_XOCDMODE(x) (((x) & ((1 << 1) - 1)) << 0) ++#define F_XT_XOCDMODE_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) ++ ++/* register APB_INT_MASK */ ++#define APB_INT_MASK 27 ++#define F_APB_INTR_MASK(x) (((x) & ((1 << 3) - 1)) << 0) ++#define F_APB_INTR_MASK_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) ++ ++/* register APB_STATUS_MASK */ ++#define APB_STATUS_MASK 28 ++#define F_APB_INTR_STATUS(x) (((x) & ((1 << 3) - 1)) << 0) ++#define F_APB_INTR_STATUS_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) ++ ++#endif /*APB_CFG*/ +diff --git a/drivers/video/imx/hdp/externs.h b/drivers/video/imx/hdp/externs.h +new file mode 100644 +index 0000000000..055f6ea2e8 +--- /dev/null ++++ b/drivers/video/imx/hdp/externs.h +@@ -0,0 +1,81 @@ ++/****************************************************************************** ++ * ++ * Copyright (C) 2016-2017 Cadence Design Systems, Inc. ++ * All rights reserved worldwide. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * ++ * 3. Neither the name of the copyright holder nor the names of its contributors ++ * may be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ++ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", ++ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED ++ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Copyright 2017 NXP ++ * ++ ****************************************************************************** ++ * ++ * externs.h ++ * ++ ****************************************************************************** ++ */ ++ ++#ifndef EXTERNS_H_ ++#define EXTERNS_H_ ++ ++#ifndef __UBOOT__ ++#include ++ ++#else ++#include ++#endif ++/** ++ * \addtogroup UTILS ++ * \{ ++ */ ++/** ++ * \brief read from apb ++ * \param addr - address to read ++ * \param value - pointer to store value ++ * \return non-zero value if error ++ */ ++/*extern int cdn_bus_read(unsigned int addr, unsigned int* value);*/ ++ ++/** ++ * \brief write to apb ++ * \param addr - address to write ++ * \param value - value to write ++ * \return non-zero if error ++ */ ++/*extern int cdn_bus_write(unsigned int addr, unsigned int value);*/ ++ ++uint32_t cdn_apb_read(uint32_t addr, uint32_t *value); ++uint32_t cdn_sapb_read(uint32_t addr, uint32_t *value); ++uint32_t cdn_apb_write(uint32_t addr, uint32_t value); ++uint32_t cdn_sapb_write(uint32_t addr, uint32_t value); ++#endif ++ +diff --git a/drivers/video/imx/hdp/general_handler.h b/drivers/video/imx/hdp/general_handler.h +new file mode 100644 +index 0000000000..3656ef8848 +--- /dev/null ++++ b/drivers/video/imx/hdp/general_handler.h +@@ -0,0 +1,162 @@ ++/****************************************************************************** ++ * ++ * Copyright (C) 2016-2017 Cadence Design Systems, Inc. ++ * All rights reserved worldwide. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * ++ * 3. Neither the name of the copyright holder nor the names of its contributors ++ * may be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ++ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", ++ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED ++ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Copyright 2017 NXP ++ * ++ ****************************************************************************** ++ * ++ * general_handler.h ++ * ++ ****************************************************************************** ++ */ ++ ++#ifndef GENERAL_HANDLER_H ++#define GENERAL_HANDLER_H ++ ++/** ++ * \file ++ * \brief general handler, checks available messages, receives ++ * it from mailbox, handles requests and sends response ++ * to the host ++ */ ++#define DP_TX_MAIL_HANDLER_REQUEST_BUFFER_LEN 256 ++ ++/** ++ * \brief opcode defines host->controller ++ */ ++#define GENERAL_MAIN_CONTROL 0x01 ++#define GENERAL_TEST_ECHO 0x02 ++#define GENERAL_BUS_SETTINGS 0x03 ++#define GENERAL_TEST_ACCESS 0x04 ++ ++#define GENERAL_WRITE_REGISTER 0x05 ++#define GENERAL_WRITE_FIELD 0x06 ++#define GENERAL_READ_REGISTER 0x07 ++ ++#define GENERAL_TEST_TRNG_SIMPLE 0xF0 ++ ++#define GENERAL_MAIN_CONTROL_SET_ACTIVE_BIT 0 ++#define GENERAL_MAIN_CONTROL_SET_ALT_CIPHER_ADDR 1 ++#define GENERAL_MAIN_CONTROL_SET_FAST_HDCP_DELAYS 2 ++ ++#define GENERAL_BUS_SETTINGS_DPCD_BUS_BIT 0 ++#define GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT 1 ++#define GENERAL_BUS_SETTINGS_HDCP_BUS_BIT 2 ++#define GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT 3 ++#define GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT 4 ++#define GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT 5 ++ ++/** ++ * \brief opcode defines controller->host ++ */ ++ ++#define GENERAL_MAIN_CONTROL_RESP 0x01 ++#define GENERAL_TEST_ECHO_RESP 0x02 ++#define GENERAL_BUS_SETTINGS_RESP 0x03 ++ ++#define GENERAL_READ_REGISTER_RESP 0x07 ++ ++#define GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT 0 ++#define GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT 1 ++#define GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT 2 ++ ++#define GENERAL_BUS_SETTINGS_RESP_SUCCESS 0 ++#define GENERAL_BUS_SETTINGS_RESP_LOCK_ERROR 1 ++ ++typedef struct { ++ unsigned char dpcd_locked; ++ unsigned char hdcp_locked; ++ unsigned char capb_locked; ++ unsigned char active_mode; ++} S_GENERAL_HANDLER_DATA; ++ ++/** ++ * \brief event id sent to the host ++ */ ++typedef enum { ++ EVENT_ID_DPTX_HPD = 0, ++ EVENT_ID_HDMI_TX_HPD = 0, ++ EVENT_ID_HDMI_RX_5V = 0, ++ ++ EVENT_ID_DPTX_TRAINING = 1, ++ EVENT_ID_HDMI_RX_SCDC_CHANGE = 1, ++ ++ EVENT_ID_RESERVE0 = 2, ++ EVENT_ID_RESERVE1 = 3, ++ ++ EVENT_ID_HDCPTX_STATUS = 4, ++ EVENT_ID_HDCPRX_STATUS = 4, ++ ++ EVENT_ID_HDCPTX_IS_KM_STORED = 5, ++ EVENT_ID_HDCPTX_STORE_KM = 6, ++ EVENT_ID_HDCPTX_IS_RECEIVER_ID_VALID = 7, ++ EVENT_ID_HDMITX_READ_REQUEST = 8, ++} EVENT_ID; ++ ++/** ++ * \brief convert bank id and register number to address and write to ptr ++ */ ++ ++#define select_reg_old(bank, reg_no, ptr) \ ++do { \ ++ ptr = 0; \ ++ if ((bank == 0x22) || (bank == 0x20) || (bank == 0x0b) || \ ++ (bank == 0x09) || (bank == 0x0A)) \ ++ ptr = (unsigned int *)(bank << 8 | reg_no); \ ++} while (0) ++ ++#define select_reg(bank, reg_no, ptr) \ ++ ptr = (unsigned int *)(bank << 8 | reg_no) ++ ++#define select_reg4(pmsb, p2, p3, plsb, ptr) \ ++ ptr = (unsigned int *)((pmsb << 24) | (p2 << 16) | \ ++ (p3 << 8) | (plsb << 0)) ++ ++ ++#define EVENTS_DPTX_CNT 2 ++#define EVENTS_HDCPTX_CNT 4 ++ ++void general_handler_set_active_mode(void); ++void general_handler_set_standby_mode(void); ++ ++/** ++ * \brief request sending en event to the host ++ * \param [in] eventId ++ * \param [in] eventCode ++ */ ++ ++#endif /* GENERAL_HANDLER_H */ +diff --git a/drivers/video/imx/hdp/opcodes.h b/drivers/video/imx/hdp/opcodes.h +new file mode 100644 +index 0000000000..e0e7d93412 +--- /dev/null ++++ b/drivers/video/imx/hdp/opcodes.h +@@ -0,0 +1,115 @@ ++/****************************************************************************** ++ * ++ * Copyright (C) 2016-2017 Cadence Design Systems, Inc. ++ * All rights reserved worldwide. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * ++ * 3. Neither the name of the copyright holder nor the names of its contributors ++ * may be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ++ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", ++ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED ++ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Copyright 2017 NXP ++ * ++ ****************************************************************************** ++ * ++ * This file was auto-generated. Do not edit it manually. ++ * ++ ****************************************************************************** ++ * ++ * opcodes.h ++ * ++ ****************************************************************************** ++ */ ++ ++#ifndef OPCODES_H_ ++# define OPCODES_H_ ++ ++# define DP_TX_MAIL_HANDLER_H ++# define DP_TX_MAIL_HANDLER_REQUEST_BUFFER_LEN 256 ++# define DPTX_SET_POWER_MNG 0x00 ++# define DPTX_SET_HOST_CAPABILITIES 0x01 ++# define DPTX_GET_EDID 0x02 ++# define DPTX_READ_DPCD 0x03 ++# define DPTX_WRITE_DPCD 0x04 ++# define DPTX_ENABLE_EVENT 0x05 ++# define DPTX_WRITE_REGISTER 0x06 ++# define DPTX_READ_REGISTER 0x07 ++# define DPTX_WRITE_FIELD 0x08 ++# define DPTX_TRAINING_CONTROL 0x09 ++# define DPTX_READ_EVENT 0x0A ++# define DPTX_READ_LINK_STAT 0x0B ++# define DPTX_SET_VIDEO 0x0C ++# define DPTX_SET_AUDIO 0x0D ++# define DPTX_GET_LAST_AUX_STAUS 0x0E ++# define DPTX_SET_LINK_BREAK_POINT 0x0F ++# define DPTX_FORCE_LANES 0x10 ++# define DPTX_HPD_STATE 0x11 ++# define DPTX_DBG_SET 0xF0 ++# define DP_TX_OPCODE_READ_I2C_REQUEST 0xA5 ++# define DP_TX_OPCODE_WRITE_I2C_REQUEST 0xA6 ++# define DP_TX_OPCODE_MESSAGE_FILTER 0xA7 ++# define DPTX_EDID_RESP 0x02 ++# define DPTX_DPCD_READ_RESP 0x03 ++# define DPTX_DPCD_WRITE_RESP 0x04 ++# define DPTX_READ_EVENT_RESP 0x0A ++# define DPTX_READ_REGISTER_RESP 0x07 ++# define DP_TX_OPCODE_MESSAGE 0x10 ++# define DP_TX_OPCODE_READ_I2C_RESPONSE 0x50 ++# define DP_TX_OPCODE_WRITE_I2C_RESPONSE 0x60 ++# define DP_TX_OPCODE_LOOPBACK_TEST 0xFE ++# define DP_TX_OPCODE_BIT_TEST 0xFF ++# define DP_TX_EVENT_ENABLE_HPD_BIT 0x00 ++# define DP_TX_EVENT_ENABLE_TRAINING_BIT 0x01 ++# define DP_TX_EVENT_CODE_HPD_HIGH 0x01 ++# define DP_TX_EVENT_CODE_HPD_LOW 0x02 ++# define DP_TX_EVENT_CODE_HPD_PULSE 0x04 ++# define DP_TX_EVENT_CODE_HPD_STATE_HIGH 0x08 ++# define DP_TX_EVENT_CODE_HPD_STATE_LOW 0x00 ++# define DP_TX_EVENT_CODE_TRAINING_FULL_STARTED 0x01 ++# define DP_TX_EVENT_CODE_TRAINING_FAST_STARTED 0x02 ++# define DP_TX_EVENT_CODE_TRAINING_FINISHED_CR 0x04 ++# define DP_TX_EVENT_CODE_TRAINING_FINISHED_EQ 0x08 ++# define DP_TX_EVENT_CODE_TRAINING_FINISHED_FAST 0x10 ++# define DP_TX_EVENT_CODE_TRAINING_FAILED_CR 0x20 ++# define DP_TX_EVENT_CODE_TRAINING_FAILED_EQ 0x40 ++# define DP_TX_EVENT_CODE_TRAINING_FAILED_FAST 0x80 ++# define MB_MODULE_ID_DP_TX 0x01 ++# define MB_MODULE_ID_DP_RX 0x02 ++# define MB_MODULE_ID_HDMI_TX 0x03 ++# define MB_MODULE_ID_HDMI_RX 0x04 ++# define MB_MODULE_ID_MHL_TX 0x05 ++# define MB_MODULE_ID_MHL_RX 0x06 ++# define MB_MODULE_ID_HDCP_TX 0x07 ++# define MB_MODULE_ID_HDCP_RX 0x08 ++# define MB_MODULE_ID_HDCP_GENERAL 0x09 ++# define MB_MODULE_ID_GENERAL 0x0A ++# define MB_MODULE_ID 1 ++ ++#endif +diff --git a/drivers/video/imx/hdp/test_base_sw.c b/drivers/video/imx/hdp/test_base_sw.c +new file mode 100644 +index 0000000000..7618323cd8 +--- /dev/null ++++ b/drivers/video/imx/hdp/test_base_sw.c +@@ -0,0 +1,181 @@ ++/****************************************************************************** ++ * ++ * Copyright (C) 2016-2017 Cadence Design Systems, Inc. ++ * All rights reserved worldwide. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * ++ * 3. Neither the name of the copyright holder nor the names of its contributors ++ * may be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ++ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", ++ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED ++ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Copyright 2017 NXP ++ * ++ ****************************************************************************** ++ * ++ * test_base_sw.c ++ * ++ ****************************************************************************** ++ */ ++ ++#ifndef __UBOOT__ ++#include ++#include ++#include ++#else ++#include ++#include ++ ++#ifdef CONFIG_ARCH_IMX8M ++/* mscale */ ++#define HDMI_BASE 0x32c00000 ++#define HDMI_PHY_BASE 0x32c80000 ++#define HDMI_SEC_BASE 0x32e40000 ++#endif ++#ifdef CONFIG_ARCH_IMX8 ++/* QM */ ++#define HDMI_BASE 0x56268000 ++#define HDMI_SEC_BASE 0x56269000 ++#define HDMI_OFFSET_ADDR 0x56261008 ++#define HDMI_SEC_OFFSET_ADDR 0x5626100c ++#endif ++ ++#endif ++ ++#ifdef CONFIG_ARCH_IMX8M ++int cdn_apb_read(unsigned int addr, unsigned int *value) ++{ ++ unsigned int temp; ++ uint64_t tmp_addr = addr + HDMI_BASE; ++ temp = __raw_readl(tmp_addr); ++ *value = temp; ++ return 0; ++} ++ ++int cdn_apb_write(unsigned int addr, unsigned int value) ++{ ++ uint64_t tmp_addr = addr + HDMI_BASE; ++ ++ __raw_writel(value, tmp_addr); ++ return 0; ++} ++ ++int cdn_sapb_read(unsigned int addr, unsigned int *value) ++{ ++ unsigned int temp; ++ uint64_t tmp_addr = addr + HDMI_SEC_BASE; ++ temp = __raw_readl(tmp_addr); ++ *value = temp; ++ return 0; ++} ++ ++int cdn_sapb_write(unsigned int addr, unsigned int value) ++{ ++ uint64_t tmp_addr = addr + HDMI_SEC_BASE; ++ __raw_writel(value, tmp_addr); ++ return 0; ++} ++ ++void cdn_sleep(uint32_t ms) ++{ ++ mdelay(ms); ++} ++ ++void cdn_usleep(uint32_t us) ++{ ++ udelay(us); ++} ++#endif ++#ifdef CONFIG_ARCH_IMX8 ++int cdn_apb_read(unsigned int addr, unsigned int *value) ++{ ++ unsigned int temp; ++ uint64_t tmp_addr = (addr & 0xfff) + HDMI_BASE; ++ ++ /* printf("%s():%d addr = 0x%08x, tmp_addr = 0x%08x, offset = 0x%08x\n", ++ __func__, __LINE__, addr, (unsigned int)tmp_addr, addr>>12); */ ++ ++ __raw_writel(addr >> 12, HDMI_OFFSET_ADDR); ++ ++ temp = __raw_readl(tmp_addr); ++ /* printf("%s():%d temp = 0x%08x\n", __func__, __LINE__, temp ); */ ++ ++ *value = temp; ++ return 0; ++} ++ ++int cdn_apb_write(unsigned int addr, unsigned int value) ++{ ++ uint64_t tmp_addr = (addr & 0xfff) + HDMI_BASE; ++ ++ /*printf("%s():%d addr=0x%08x, taddr=0x%08x, off=0x%08x, val=0x%08x\n", ++ __func__, __LINE__, addr, (unsigned int)tmp_addr, ++ addr>>12, value);*/ ++ ++ __raw_writel(addr >> 12, HDMI_OFFSET_ADDR); ++ ++ /* printf("%s():%d\n", __func__, __LINE__); */ ++ __raw_writel(value, tmp_addr); ++ ++ return 0; ++} ++ ++int cdn_sapb_read(unsigned int addr, unsigned int *value) ++{ ++ unsigned int temp; ++ uint64_t tmp_addr = (addr & 0xfff) + HDMI_SEC_BASE; ++ ++ __raw_writel(addr >> 12, HDMI_SEC_OFFSET_ADDR); ++ ++ temp = __raw_readl(tmp_addr); ++ *value = temp; ++ return 0; ++} ++ ++int cdn_sapb_write(unsigned int addr, unsigned int value) ++{ ++ uint64_t tmp_addr = (addr & 0xfff) + HDMI_SEC_BASE; ++ ++ __raw_writel(addr >> 12, HDMI_SEC_OFFSET_ADDR); ++ __raw_writel(value, tmp_addr); ++ ++ return 0; ++} ++ ++void cdn_sleep(uint32_t ms) ++{ ++ mdelay(ms); ++} ++ ++void cdn_usleep(uint32_t us) ++{ ++ udelay(us); ++} ++#endif ++ +diff --git a/drivers/video/imx/hdp/util.c b/drivers/video/imx/hdp/util.c +new file mode 100644 +index 0000000000..727946a796 +--- /dev/null ++++ b/drivers/video/imx/hdp/util.c +@@ -0,0 +1,329 @@ ++/****************************************************************************** ++ * ++ * Copyright (C) 2016-2017 Cadence Design Systems, Inc. ++ * All rights reserved worldwide. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * ++ * 3. Neither the name of the copyright holder nor the names of its contributors ++ * may be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ++ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", ++ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED ++ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Copyright 2017 NXP ++ * ++ ****************************************************************************** ++ * ++ * util.c ++ * ++ ****************************************************************************** ++ */ ++ ++#include "util.h" ++#include "API_General.h" ++#include "externs.h" ++#ifndef __UBOOT__ ++#include ++#endif ++#include "apb_cfg.h" ++#include "opcodes.h" ++#ifndef __UBOOT__ ++#include ++ ++#endif ++state_struct state; ++ ++int cdn_bus_read(unsigned int addr, unsigned int *value) ++{ ++ return state.bus_type ? ++ cdn_sapb_read(addr, value) : cdn_apb_read(addr, value); ++} ++ ++int cdn_bus_write(unsigned int addr, unsigned int value) ++{ ++ return state.bus_type ? ++ cdn_sapb_write(addr, value) : cdn_apb_write(addr, value); ++} ++ ++void internal_itobe(int val, volatile unsigned char *dest, int bytes) ++{ ++ int i; ++ for (i = bytes - 1; i >= 0; --i) { ++ dest[i] = (unsigned char)val; ++ val >>= 8; ++ } ++} ++ ++uint32_t internal_betoi(volatile uint8_t const *src, uint8_t bytes) ++{ ++ uint32_t ret = 0; ++ int i; ++ ++ if (bytes > sizeof(ret)) { ++ printf("Warning. Read request for payload larger then supported.\n"); ++ bytes = sizeof(ret); ++ } ++ ++ for (i = 0; i < bytes; ++i) { ++ ret <<= 8; ++ ret |= (unsigned int)src[i]; ++ } ++ ++ return ret; ++} ++ ++unsigned int internal_mkmsg(volatile unsigned char *dest, int valno, ...) ++{ ++ va_list vl; ++ unsigned int len = 0; ++ va_start(vl, valno); ++ len = internal_vmkmsg(dest, valno, vl); ++ va_end(vl); ++ return len; ++} ++ ++unsigned int internal_vmkmsg(volatile unsigned char *dest, int valno, ++ va_list vl) ++{ ++ unsigned int len = 0; ++ int i; ++ for (i = 0; i < valno; ++i) { ++ int size = va_arg(vl, int); ++ if (size > 0) { ++ internal_itobe(va_arg(vl, int), dest, size); ++ dest += size; ++ len += size; ++ } else { ++ memcpy((void *)dest, va_arg(vl, void *), -size); ++ dest -= size; ++ len -= size; ++ } ++ } ++ return len; ++} ++ ++void internal_tx_mkfullmsg(unsigned char module, unsigned char opcode, ++ int valno, ...) ++{ ++ va_list vl; ++ va_start(vl, valno); ++ internal_vtx_mkfullmsg(module, opcode, valno, vl); ++ va_end(vl); ++} ++ ++void internal_vtx_mkfullmsg(unsigned char module, unsigned char opcode, ++ int valno, va_list vl) ++{ ++ unsigned int len = ++ internal_vmkmsg(state.txbuffer + INTERNAL_CMD_HEAD_SIZE, valno, vl); ++ internal_mbox_tx_enable(module, opcode, len); ++ state.txenable = 1; ++ state.running = 1; ++} ++ ++void internal_readmsg(int valno, ...) ++{ ++ va_list vl; ++ va_start(vl, valno); ++ internal_vreadmsg(valno, vl); ++ va_end(vl); ++} ++ ++void internal_vreadmsg(int valno, va_list vl) ++{ ++ uint8_t *src = state.rxbuffer + INTERNAL_CMD_HEAD_SIZE; ++ size_t i; ++ ++ for (i = 0; i < (size_t) valno; ++i) { ++ int size = va_arg(vl, int); ++ void *ptr = va_arg(vl, void *); ++ ++ if (!ptr) { ++ src += size; ++ } else if (!size) { ++ *((unsigned char **)ptr) = src; ++ } else if (size > 0) { ++ switch ((size_t) size) { ++ case sizeof(uint8_t): ++ *((uint8_t *)ptr) = internal_betoi(src, size); ++ break; ++ case sizeof(uint16_t): ++ *((uint16_t *)ptr) = internal_betoi(src, size); ++ break; ++ case 3: /* 3-byte value (e.g. DPCD address) ++ can be safely converted from BE.*/ ++ case sizeof(uint32_t): ++ *((uint32_t *)ptr) = internal_betoi(src, size); ++ break; ++ default: ++ printf("Warning. Unsupported variable size.\n"); ++ memcpy(ptr, src, size); ++ }; ++ ++ src += size; ++ } else { ++ memcpy(ptr, src, -size); ++ src -= size; ++ } ++ } ++} ++ ++INTERNAL_MBOX_STATUS mailbox_write(unsigned char val) ++{ ++ INTERNAL_MBOX_STATUS ret; ++ unsigned int full; ++ if (cdn_bus_read(MAILBOX_FULL_ADDR << 2, &full)) { ++ ret.tx_status = CDN_TX_APB_ERROR; ++ return ret; ++ } ++ if (full) { ++ ret.tx_status = CDN_TX_FULL; ++ return ret; ++ } ++ if (cdn_bus_write(MAILBOX0_WR_DATA << 2, val)) { ++ ret.tx_status = CDN_TX_APB_ERROR; ++ return ret; ++ } ++ ret.tx_status = CDN_TX_WRITE; ++ return ret; ++} ++ ++INTERNAL_MBOX_STATUS mailbox_read(volatile unsigned char *val) ++{ ++ INTERNAL_MBOX_STATUS ret; ++ unsigned int empty; ++ unsigned int rd; ++ if (cdn_bus_read(MAILBOX_EMPTY_ADDR << 2, &empty)) { ++ ret.rx_status = CDN_RX_APB_ERROR; ++ return ret; ++ } ++ if (empty) { ++ ret.rx_status = CDN_RX_EMPTY; ++ return ret; ++ } ++ if (cdn_bus_read(MAILBOX0_RD_DATA << 2, &rd)) { ++ ret.rx_status = CDN_RX_APB_ERROR; ++ return ret; ++ } ++ *val = (unsigned char)rd; ++ ret.rx_status = CDN_RX_READ; ++ return ret; ++} ++ ++INTERNAL_MBOX_STATUS internal_mbox_tx_process(void) ++{ ++ unsigned int txcount = 0; ++ unsigned int length = ++ (unsigned int)state.txbuffer[2] << 8 | (unsigned int)state. ++ txbuffer[3]; ++ INTERNAL_MBOX_STATUS ret = {.txend = 0 }; ++ ret.tx_status = CDN_TX_NOTHING; ++ INTERNAL_MBOX_STATUS tx_ret; ++ if (!state.txenable) ++ return ret; ++ while ((tx_ret.tx_status = ++ mailbox_write(state.txbuffer[state.txi]).tx_status) == ++ CDN_TX_WRITE) { ++ txcount++; ++ if (++state.txi >= length + 4) { ++ state.txenable = 0; ++ state.txi = 0; ++ ret.txend = 1; ++ break; ++ } ++ } ++ if (txcount && tx_ret.tx_status == CDN_TX_FULL) ++ ret.tx_status = CDN_TX_WRITE; ++ else ++ ret.tx_status = tx_ret.tx_status; ++ return ret; ++} ++ ++INTERNAL_MBOX_STATUS internal_mbox_rx_process(void) ++{ ++ unsigned int rxcount = 0; ++ INTERNAL_MBOX_STATUS ret = { 0, 0, 0, 0 }; ++ INTERNAL_MBOX_STATUS rx_ret; ++ while ((rx_ret.rx_status = ++ mailbox_read(state.rxbuffer + state.rxi).rx_status) == ++ CDN_RX_READ) { ++ rxcount++; ++ if (++state.rxi >= 4 + ++ ((unsigned int)state.rxbuffer[2] << 8 | ++ (unsigned int)state.rxbuffer[3])) { /* end of message */ ++ state.rxi = 0; ++ ret.rxend = 1; ++ state.rxenable = 0; ++ break; ++ } ++ } ++ ret.rx_status = rxcount ? CDN_RX_READ : CDN_RX_EMPTY; ++ return ret; ++} ++ ++unsigned int internal_apb_available(void) ++{ ++ return !(state.rxenable || state.txenable); ++} ++ ++void internal_mbox_tx_enable(unsigned char module, unsigned char opcode, ++ unsigned short length) ++{ ++ state.txbuffer[0] = opcode; ++ state.txbuffer[1] = module; ++ state.txbuffer[2] = (unsigned char)(length >> 8); ++ state.txbuffer[3] = (unsigned char)length; ++ state.txenable = 1; ++} ++ ++CDN_API_STATUS internal_test_rx_head(unsigned char module, unsigned char opcode) ++{ ++ if (opcode != state.rxbuffer[0]) ++ return CDN_BAD_OPCODE; ++ if (module != state.rxbuffer[1]) ++ return CDN_BAD_MODULE; ++ return CDN_OK; ++} ++ ++CDN_API_STATUS internal_test_rx_head_match(void) ++{ ++ return internal_test_rx_head(state.txbuffer[1], state.txbuffer[0]); ++} ++ ++void print_fw_ver(void) ++{ ++ unsigned short ver, verlib; ++ cdn_api_general_getcurversion(&ver, &verlib); ++ printf("FIRMWARE VERSION: %d, LIB VERSION: %d\n", ver, verlib); ++} ++ ++unsigned short internal_get_msg_len(void) ++{ ++ return ((unsigned short)state.rxbuffer[2] << 8) | (unsigned short)state. ++ rxbuffer[3]; ++} +diff --git a/drivers/video/imx/hdp/util.h b/drivers/video/imx/hdp/util.h +new file mode 100644 +index 0000000000..605f0f933b +--- /dev/null ++++ b/drivers/video/imx/hdp/util.h +@@ -0,0 +1,278 @@ ++/****************************************************************************** ++ * ++ * Copyright (C) 2016-2017 Cadence Design Systems, Inc. ++ * All rights reserved worldwide. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * ++ * 3. Neither the name of the copyright holder nor the names of its contributors ++ * may be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ++ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ++ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", ++ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED ++ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, ++ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE ++ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Copyright 2017 NXP ++ * ++ ****************************************************************************** ++ * ++ * util.h ++ * ++ ****************************************************************************** ++ */ ++ ++#ifndef UTIL_H_ ++#define UTIL_H_ ++ ++#include "API_General.h" ++#ifndef __UBOOT__ ++#include ++#include ++#else ++#include ++#endif ++/** ++ * \addtogroup UTILS ++ * \{ ++ */ ++#define INTERNAL_CMD_HEAD_SIZE 4 ++ ++/** ++ * \brief expands to blocking function body ++ * \param x - function call ++ */ ++#define internal_block_function(x) \ ++do { \ ++ CDN_API_STATUS ret; \ ++ do { \ ++ ret = x; \ ++ } while (ret == CDN_BSY || ret == CDN_STARTED); \ ++ return ret; \ ++} while (0) ++ ++/** ++ * \brief write message and write response (if any), non-blocking way. Also sets state.running = 0 ++ */ ++#define INTERNAL_PROCESS_MESSAGES \ ++do { \ ++ if (state.txenable && !internal_mbox_tx_process().txend) \ ++ return CDN_BSY; \ ++ if (state.rxenable && !internal_mbox_rx_process().rxend) \ ++ return CDN_BSY; \ ++ state.running = 0; \ ++} while (0) ++ ++#define internal_opcode_ok_or_return(module, opcode) \ ++do { \ ++ CDN_API_STATUS ret = internal_test_rx_head(module, opcode); \ ++ if (ret != CDN_OK) \ ++ return ret; \ ++} while (0) ++ ++#define internal_opcode_match_or_return() \ ++do { \ ++ CDN_API_STATUS ret = internal_test_rx_head_match(); \ ++ if (ret != CDN_OK) \ ++ return ret; \ ++} while (0) ++ ++/* macro for simple tx only command, command format as in mkfullmsg ++ (with count) */ ++#define internal_macro_command_tx(module, opcode, bustype, command...) \ ++do { \ ++ if (!state.running) { \ ++ internal_tx_mkfullmsg(module, opcode, command); \ ++ state.bus_type = bustype; \ ++ return CDN_STARTED; \ ++ } \ ++ INTERNAL_PROCESS_MESSAGES; \ ++} while (0) ++ ++/* macro for command with response with matching opcode, command format as in ++ mkfullmsg (with count) */ ++#define internal_macro_command_txrx(module, opcode, bustype, command...) \ ++do { \ ++ if (!state.running) { \ ++ internal_tx_mkfullmsg(module, opcode, command); \ ++ state.bus_type = bustype; \ ++ state.rxenable = 1; \ ++ return CDN_STARTED; \ ++ } \ ++ INTERNAL_PROCESS_MESSAGES; \ ++ internal_opcode_match_or_return(); \ ++} while (0) ++ ++typedef struct { ++ /** apb write status */ ++ enum tx_status_enum { ++ /** one or more bytes written */ ++ CDN_TX_WRITE = 0, ++ /** nothing to write */ ++ CDN_TX_NOTHING = 1, ++ /** mailbox full, 0 bytes written */ ++ CDN_TX_FULL = 2, ++ /** APB error while writing */ ++ CDN_TX_APB_ERROR = 3 ++ } tx_status:3; ++ /** apb read status */ ++ enum rx_status_enum { ++ /** 1 or more bytes read */ ++ CDN_RX_READ = 0, ++ /** mailbox empty, 0 bytes read */ ++ CDN_RX_EMPTY = 1, ++ /** apb error while reading */ ++ CDN_RX_APB_ERROR = 2 ++ } rx_status:2; ++ /** indicates end of currenly recived message */ ++ unsigned char rxend:1; ++ /** end of tx message reached */ ++ unsigned char txend:1; ++} INTERNAL_MBOX_STATUS; ++ ++/** ++ * \brief put val into dest in big endian format ++ * \param val - value to put ++ * \param dest - place to put value ++ * \param bytes - true size of val in bytes. for example if ++ * bytes = 2 val is treated as short int ++ */ ++void internal_itobe(int val, volatile unsigned char *dest, int bytes); ++ ++/** ++ * \brief read big endian value from src and return it ++ * \param src - source to read from ++ * \param bytes - size of read value ++ * \return result ++ */ ++uint32_t internal_betoi(volatile uint8_t const *src, uint8_t bytes); ++ ++/** ++ * \brief create message from size and value pairs; also sets ++ * state.running and state.txEnable ++ * \param dest - pointer to write message to ++ * \param valNo - number of values to write ++ * \param ... - pairs of size and value, each value is written ++ * after another. if size is positive value, value is ++ * written with #internal_itobe, if size is negative, ++ * value is treated as src pointer for memcpy ++ * ++ * example: ++ * ++ * unsigned short x = 0xAABB; ++ * ++ * internal_mkmsg(dest, 3, 1, 1, 2, 3, -2, &x); ++ * ++ * will write 01 00 03 AA BB to dest ++ */ ++unsigned int internal_mkmsg(volatile unsigned char *dest, int valno, ...); ++unsigned int internal_vmkmsg(volatile unsigned char *dest, int valno, ++ va_list vl); ++ ++/** ++ * \brief setup message header in txBuffer, set txEnable = 1 ++ */ ++void internal_mbox_tx_enable(unsigned char module, unsigned char opcode, ++ unsigned short length); ++ ++/** ++ * \brief write from txBuffer to mailbox untill full or end of message. ++ * ++ * when txEnable == 0 writes nothing ++ * when write reaches end of message set txEnable = 0 ++ */ ++ ++/** ++ * \brief combination of #internal_mkmsg and #internal_mbox_tx_enable ++ * ++ * #internal_mkmsg dest and #internal_mbox_tx_enable length are determined ++ * automaticly this function also sets state.txEnable = 1 and ++ * state.running ++ */ ++void internal_tx_mkfullmsg(unsigned char module, unsigned char opcode, ++ int valno, ...); ++void internal_vtx_mkfullmsg(unsigned char module, unsigned char opcode, ++ int valno, va_list vl); ++ ++/** ++ * \brief read from state.txBuffer and store results in specified pointers ++ * \param valNo - numbero of values to read ++ * \param ... - pairs of size and ptr ++ * ++ * this function is similar to #internal_mkmsg - ++ * ++ * when size is positive read value using #internal_betoi ++ * when size is negative mempcy from txBuffer to ptr -size bytes ++ * when size is 0 write to ptr addres of current position in rxbuffer ++ * when ptr is NULL ignore size bytes (if size is negative this ++ * will rewind buffer) ++ */ ++void internal_readmsg(int valno, ...); ++void internal_vreadmsg(int valno, va_list vl); ++ ++INTERNAL_MBOX_STATUS internal_mbox_tx_process(void); ++/** ++ * \brief read to rxBuffer from mailbox untill empty or end of message ++ * ++ * when rxEnable == 0 reads nothing ++ * when end of message reached sets rxEnable = 0 ++ */ ++INTERNAL_MBOX_STATUS internal_mbox_rx_process(void); ++ ++/** ++ * \brief check if apb is available ++ * \return !(rxEnable && txEable) ++ */ ++unsigned int internal_apb_available(void); ++ ++/** ++ * \brief test if parameters match module and opcode in rxBuffer ++ * \return CDN_OK or CDN_BAD_OPCODE or CDN_BAD_MODULE ++ */ ++CDN_API_STATUS internal_test_rx_head(unsigned char module, ++ unsigned char opcode); ++ ++CDN_API_STATUS internal_test_rx_head_match(void); ++ ++/** ++ * \brief print current fw and lib version ++ */ ++void print_fw_ver(void); ++ ++typedef struct { ++ unsigned char txbuffer[1024]; ++ unsigned char rxbuffer[1024]; ++ unsigned int txi; /* iterators */ ++ unsigned int rxi; ++ unsigned char txenable; /*data readt to send*/ ++ unsigned char rxenable; ++ unsigned char running; ++ CDN_BUS_TYPE bus_type; ++ unsigned int tmp; ++} state_struct; ++ ++unsigned short internal_get_msg_len(void); ++ ++#endif +diff --git a/drivers/video/imx/hdp_load.c b/drivers/video/imx/hdp_load.c +new file mode 100644 +index 0000000000..d5eea2cf72 +--- /dev/null ++++ b/drivers/video/imx/hdp_load.c +@@ -0,0 +1,107 @@ ++/* ++ * Copyright 2017-2018 NXP ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++ ++#include "API_General.h" ++#include "scfw_utils.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define ON 1 ++#define OFF 0 ++ ++static void display_set_power(int onoff) ++{ ++ sc_ipc_t ipcHndl = -1; ++ ++ SC_PM_SET_RESOURCE_POWER_MODE(ipcHndl, SC_R_DC_0, onoff); ++ SC_PM_SET_RESOURCE_POWER_MODE(ipcHndl, SC_R_HDMI, onoff); ++} ++ ++static void display_set_clocks(void) ++{ ++ sc_ipc_t ipcHndl = -1; ++ const sc_pm_clock_rate_t pll = 1188000000; ++ const sc_pm_clock_rate_t hdmi_core_clock = pll / 10; ++ const sc_pm_clock_rate_t hdmi_bus_clock = pll / 14; ++ ++ SC_PM_SET_RESOURCE_POWER_MODE(ipcHndl, ++ SC_R_HDMI_PLL_0, SC_PM_PW_MODE_OFF); ++ SC_PM_SET_CLOCK_RATE(ipcHndl, ++ SC_R_HDMI_PLL_0, SC_PM_CLK_PLL, pll); ++ SC_PM_SET_RESOURCE_POWER_MODE(ipcHndl, ++ SC_R_HDMI_PLL_0, SC_PM_PW_MODE_ON); ++ ++ /* HDMI DI Bus Clock */ ++ SC_PM_SET_CLOCK_RATE(ipcHndl, ++ SC_R_HDMI, SC_PM_CLK_MISC4, hdmi_bus_clock); ++ /* HDMI DI Core Clock */ ++ SC_PM_SET_CLOCK_RATE(ipcHndl, ++ SC_R_HDMI, SC_PM_CLK_MISC2, hdmi_core_clock); ++} ++ ++static void display_enable_clocks(int enable) ++{ ++ sc_ipc_t ipcHndl = -1; ++ ++ SC_PM_CLOCK_ENABLE(ipcHndl, SC_R_HDMI_PLL_0, SC_PM_CLK_PLL, enable); ++ SC_PM_CLOCK_ENABLE(ipcHndl, SC_R_HDMI, SC_PM_CLK_MISC2, enable); ++ SC_PM_CLOCK_ENABLE(ipcHndl, SC_R_HDMI, SC_PM_CLK_MISC4, enable); ++} ++ ++int do_hdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ if (argc < 2) ++ return 0; ++ ++ if (strncmp(argv[1], "tracescfw", 9) == 0) { ++ g_debug_scfw = 1; ++ printf("Enabled SCFW API tracing\n"); ++ } else if (strncmp(argv[1], "load", 4) == 0) { ++ unsigned long address = 0; ++ unsigned long offset = 0x2000; ++ const int iram_size = 0x10000; ++ const int dram_size = 0x8000; ++ ++ if (argc > 2) { ++ address = simple_strtoul(argv[2], NULL, 0); ++ if (argc > 3) ++ offset = simple_strtoul(argv[3], NULL, 0); ++ } else ++ printf("Missing address\n"); ++ ++ printf("Loading hdp firmware from 0x%016lx offset 0x%016lx\n", ++ address, offset); ++ display_set_power(SC_PM_PW_MODE_ON); ++ display_set_clocks(); ++ display_enable_clocks(ON); ++ cdn_api_loadfirmware((unsigned char *)(address + offset), ++ iram_size, ++ (unsigned char *)(address + offset + ++ iram_size), ++ dram_size); ++ display_enable_clocks(OFF); ++ printf("Loading hdp firmware Complete\n"); ++ /* do not turn off hdmi power or firmware load will be lost */ ++ } else { ++ printf("test error argc %d\n", argc); ++ } ++ ++ return 0; ++} ++/***************************************************/ ++ ++U_BOOT_CMD( ++ hdp, CONFIG_SYS_MAXARGS, 1, do_hdp, ++ "load hdmi firmware ", ++ "[] ...\n" ++ "hdpload [address] []\n" ++ " address - address where the binary image starts\n" ++ " - IRAM offset in the binary image (8192 default)\n" ++ "tracescfw - Trace SCFW API calls for video commands\n" ++ ); +diff --git a/drivers/video/imx/scfw_utils.h b/drivers/video/imx/scfw_utils.h +new file mode 100644 +index 0000000000..a583d26a78 +--- /dev/null ++++ b/drivers/video/imx/scfw_utils.h +@@ -0,0 +1,90 @@ ++/* ++ * Copyright 2017 NXP ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++#ifndef _SCFW_UTILS_H_ ++#define _SCFW_UTILS_H_ ++ ++#include ++#include ++ ++static int g_debug_scfw; /* set to one to turn on SCFW API tracing */ ++ ++#define SC_PM_SET_CLOCK_PARENT(__ipcHndl__, __res__, __clk__, __parent__) \ ++do { \ ++ char _res_str[] = #__res__;\ ++ char _clk_str[] = #__clk__;\ ++ sc_err_t _ret;\ ++ if (g_debug_scfw) \ ++ printf("(%4d) sc_pm_set_clock_parent %s:%s -> %d\n",\ ++ __LINE__, _res_str, _clk_str, __parent__);\ ++ _ret = sc_pm_set_clock_parent(__ipcHndl__,\ ++ __res__, __clk__, __parent__);\ ++ if (_ret != SC_ERR_NONE) \ ++ printf("(%d)>> sc_pm_set_clock_parent failed! %s:%s -> %d (error = %d)\n",\ ++ __LINE__, _res_str, _clk_str, __parent__, _ret);\ ++} while (0) ++ ++#define SC_PM_SET_CLOCK_RATE(__ipcHndl__, __res__, __clk__, __rate__) \ ++do { \ ++ char _res_str[] = #__res__;\ ++ char _clk_str[] = #__clk__;\ ++ sc_err_t _ret;\ ++ sc_pm_clock_rate_t _actual = __rate__;\ ++ if (g_debug_scfw) \ ++ printf("(%4d) sc_pm_set_clock_rate %s:%s -> %d\n",\ ++ __LINE__, _res_str, _clk_str, __rate__);\ ++ _ret = sc_pm_set_clock_rate(__ipcHndl__, __res__, __clk__, &_actual);\ ++ if (_ret != SC_ERR_NONE)\ ++ printf("(%4d)>> sc_pm_set_clock_rate failed! %s:%s -> %d (error = %d)\n",\ ++ __LINE__, _res_str, _clk_str, __rate__, _ret);\ ++ if (_actual != __rate__)\ ++ printf("(%4d)>> Actual rate for %s:%s is %d instead of %d\n", \ ++ __LINE__, _res_str, _clk_str, _actual, __rate__); \ ++} while (0) ++ ++#define SC_PM_CLOCK_ENABLE(__ipcHndl__, __res__, __clk__, __enable__) \ ++do { \ ++ char _res_str[] = #__res__;\ ++ char _clk_str[] = #__clk__;\ ++ sc_err_t _ret;\ ++ if (g_debug_scfw) \ ++ printf("(%4d) sc_pm_clock_enable %s:%s -> %d\n",\ ++ __LINE__, _res_str, _clk_str, __enable__);\ ++ _ret = sc_pm_clock_enable(ipcHndl,\ ++ __res__, __clk__, __enable__, false);\ ++ if (_ret != SC_ERR_NONE)\ ++ printf("(%4d)>> sc_pm_clock_enable failed! %s:%s -> %d (error = %d)\n",\ ++ __LINE__, _res_str, _clk_str, __enable__, _ret);\ ++} while (0) \ ++ ++#define SC_MISC_SET_CONTROL(__ipcHndl__, __res__, __clk__, __value__) \ ++do { \ ++ char _res_str[] = #__res__; \ ++ char _clk_str[] = #__clk__; \ ++ sc_err_t _ret; \ ++ if (g_debug_scfw) \ ++ printf("(%4d) sc_misc_set_control %s:%s -> %d\n",\ ++ __LINE__, _res_str, _clk_str, __value__);\ ++ _ret = sc_misc_set_control(ipcHndl, \ ++ __res__, __clk__, __value__); \ ++ if (_ret != SC_ERR_NONE) \ ++ printf("(%4d)>> sc_misc_set_control failed! %s:%s -> %d (error = %d)\n", \ ++ __LINE__, _res_str, _clk_str, __value__, _ret); \ ++} while (0) ++ ++#define SC_PM_SET_RESOURCE_POWER_MODE(__ipcHndl__, __res__, __enable__) \ ++do { \ ++ char _res_str[] = #__res__; \ ++ sc_err_t _ret; \ ++ if (g_debug_scfw) \ ++ printf("(%4d) sc_pm_set_resource_power_mode %s -> %d\n",\ ++ __LINE__, _res_str, __enable__);\ ++ _ret = sc_pm_set_resource_power_mode(ipcHndl, __res__, __enable__);\ ++ if (_ret != SC_ERR_NONE) \ ++ printf("(%4d)>> sc_pm_set_resource_power_mode failed! %s -> %d (error = %d)\n", \ ++ __LINE__, _res_str, __enable__, _ret);\ ++} while (0) ++ ++#endif /*_SCFW_UTILS_H_ */ +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0011-thermal-add-i.MX8-thermal-driver.patch b/recipes-bsp/u-boot-mainline/files/0011-thermal-add-i.MX8-thermal-driver.patch deleted file mode 100644 index a87970c..0000000 --- a/recipes-bsp/u-boot-mainline/files/0011-thermal-add-i.MX8-thermal-driver.patch +++ /dev/null @@ -1,257 +0,0 @@ -From 978f589e7c40976f78f177d312d50d9fb3e18303 Mon Sep 17 00:00:00 2001 -From: Peng Fan -Date: Fri, 12 Apr 2019 07:55:03 +0000 -Subject: [PATCH 11/19] thermal: add i.MX8 thermal driver - -Add i.MX8 thermal driver to support get temperature from SCU. - -Signed-off-by: Peng Fan ---- - drivers/thermal/Kconfig | 9 ++ - drivers/thermal/Makefile | 1 + - drivers/thermal/imx_scu_thermal.c | 203 ++++++++++++++++++++++++++++++++++++++ - 3 files changed, 213 insertions(+) - create mode 100644 drivers/thermal/imx_scu_thermal.c - -diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig -index a71b9be5fb..bdf8dc6fef 100644 ---- a/drivers/thermal/Kconfig -+++ b/drivers/thermal/Kconfig -@@ -17,6 +17,15 @@ config IMX_THERMAL - cpufreq is used as the cooling device to throttle CPUs when the - passive trip is crossed. - -+config IMX_SCU_THERMAL -+ bool "Temperature sensor driver for NXP i.MX8" -+ depends on ARCH_IMX8 -+ help -+ Support for Temperature sensors on NXP i.MX8. -+ It supports one critical trip point and one passive trip point. The -+ boot is hold to the cool device to throttle CPUs when the passive -+ trip is crossed -+ - config TI_DRA7_THERMAL - bool "Temperature sensor driver for TI dra7xx SOCs" - help -diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile -index cc75e387e4..ef2929d180 100644 ---- a/drivers/thermal/Makefile -+++ b/drivers/thermal/Makefile -@@ -5,4 +5,5 @@ - - obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o - obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o -+obj-$(CONFIG_IMX_SCU_THERMAL) += imx_scu_thermal.o - obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o -diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c -new file mode 100644 -index 0000000000..7e17377b69 ---- /dev/null -+++ b/drivers/thermal/imx_scu_thermal.c -@@ -0,0 +1,203 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+struct imx_sc_thermal_plat { -+ int critical; -+ int alert; -+ int polling_delay; -+ int id; -+ bool zone_node; -+}; -+ -+static int read_temperature(struct udevice *dev, int *temp) -+{ -+ s16 celsius; -+ s8 tenths; -+ int ret; -+ -+ sc_rsrc_t *sensor_rsrc = (sc_rsrc_t *)dev_get_driver_data(dev); -+ -+ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); -+ -+ if (!temp) -+ return -EINVAL; -+ -+ ret = sc_misc_get_temp(-1, sensor_rsrc[pdata->id], SC_C_TEMP, -+ &celsius, &tenths); -+ if (ret) { -+ printf("Error: get temperature failed! (error = %d)\n", ret); -+ return ret; -+ } -+ -+ *temp = celsius * 1000 + tenths * 100; -+ -+ return 0; -+} -+ -+int imx_sc_thermal_get_temp(struct udevice *dev, int *temp) -+{ -+ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); -+ int cpu_temp = 0; -+ int ret; -+ -+ ret = read_temperature(dev, &cpu_temp); -+ if (ret) -+ return ret; -+ -+ while (cpu_temp >= pdata->alert) { -+ printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)", -+ cpu_temp, pdata->alert, pdata->critical); -+ puts(" waiting...\n"); -+ mdelay(pdata->polling_delay); -+ ret = read_temperature(dev, &cpu_temp); -+ if (ret) -+ return ret; -+ } -+ -+ *temp = cpu_temp / 1000; -+ -+ return 0; -+} -+ -+static const struct dm_thermal_ops imx_sc_thermal_ops = { -+ .get_temp = imx_sc_thermal_get_temp, -+}; -+ -+static int imx_sc_thermal_probe(struct udevice *dev) -+{ -+ debug("%s dev name %s\n", __func__, dev->name); -+ return 0; -+} -+ -+static int imx_sc_thermal_bind(struct udevice *dev) -+{ -+ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); -+ int reg, ret; -+ int offset; -+ const char *name; -+ const void *prop; -+ -+ debug("%s dev name %s\n", __func__, dev->name); -+ -+ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "compatible", -+ NULL); -+ if (!prop) -+ return 0; -+ -+ pdata->zone_node = 1; -+ -+ reg = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "tsens-num", 0); -+ if (reg == 0) { -+ printf("%s: no temp sensor number provided!\n", __func__); -+ return -EINVAL; -+ } -+ -+ offset = fdt_subnode_offset(gd->fdt_blob, 0, "thermal-zones"); -+ fdt_for_each_subnode(offset, gd->fdt_blob, offset) { -+ /* Bind the subnode to this driver */ -+ name = fdt_get_name(gd->fdt_blob, offset, NULL); -+ -+ ret = device_bind_with_driver_data(dev, dev->driver, name, -+ dev->driver_data, -+ offset_to_ofnode(offset), -+ NULL); -+ if (ret) -+ printf("Error binding driver '%s': %d\n", -+ dev->driver->name, ret); -+ } -+ return 0; -+} -+ -+static int imx_sc_thermal_ofdata_to_platdata(struct udevice *dev) -+{ -+ struct imx_sc_thermal_plat *pdata = dev_get_platdata(dev); -+ struct fdtdec_phandle_args args; -+ const char *type; -+ int ret; -+ int trips_np; -+ -+ debug("%s dev name %s\n", __func__, dev->name); -+ -+ if (pdata->zone_node) -+ return 0; -+ -+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev), -+ "thermal-sensors", -+ "#thermal-sensor-cells", -+ 0, 0, &args); -+ if (ret) -+ return ret; -+ -+ if (args.node != dev_of_offset(dev->parent)) -+ return -EFAULT; -+ -+ if (args.args_count >= 1) -+ pdata->id = args.args[0]; -+ else -+ pdata->id = 0; -+ -+ debug("args.args_count %d, id %d\n", args.args_count, pdata->id); -+ -+ pdata->polling_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), -+ "polling-delay", 1000); -+ -+ trips_np = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev), -+ "trips"); -+ fdt_for_each_subnode(trips_np, gd->fdt_blob, trips_np) { -+ type = fdt_getprop(gd->fdt_blob, trips_np, "type", NULL); -+ if (type) { -+ if (strcmp(type, "critical") == 0) { -+ pdata->critical = fdtdec_get_int(gd->fdt_blob, -+ trips_np, -+ "temperature", -+ 85); -+ } else if (strcmp(type, "passive") == 0) { -+ pdata->alert = fdtdec_get_int(gd->fdt_blob, -+ trips_np, -+ "temperature", -+ 80); -+ } -+ } -+ } -+ -+ debug("id %d polling_delay %d, critical %d, alert %d\n", pdata->id, -+ pdata->polling_delay, pdata->critical, pdata->alert); -+ -+ return 0; -+} -+ -+static const sc_rsrc_t imx8qxp_sensor_rsrc[] = { -+ SC_R_SYSTEM, SC_R_DRC_0, SC_R_PMIC_0, -+ SC_R_PMIC_1, SC_R_PMIC_2, -+}; -+ -+static const struct udevice_id imx_sc_thermal_ids[] = { -+ { .compatible = "nxp,imx8qxp-sc-tsens", .data = -+ (ulong)&imx8qxp_sensor_rsrc, }, -+ { } -+}; -+ -+U_BOOT_DRIVER(imx_sc_thermal) = { -+ .name = "imx_sc_thermal", -+ .id = UCLASS_THERMAL, -+ .ops = &imx_sc_thermal_ops, -+ .of_match = imx_sc_thermal_ids, -+ .bind = imx_sc_thermal_bind, -+ .probe = imx_sc_thermal_probe, -+ .ofdata_to_platdata = imx_sc_thermal_ofdata_to_platdata, -+ .platdata_auto_alloc_size = sizeof(struct imx_sc_thermal_plat), -+ .flags = DM_FLAG_PRE_RELOC, -+}; --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0012-MLK-17205-2-video-imx-hdp-Adding-HDP-firmware-loadin.patch b/recipes-bsp/u-boot-mainline/files/0012-MLK-17205-2-video-imx-hdp-Adding-HDP-firmware-loadin.patch new file mode 100644 index 0000000..022b8e4 --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0012-MLK-17205-2-video-imx-hdp-Adding-HDP-firmware-loadin.patch @@ -0,0 +1,37 @@ +From 60ebfc3c6aa4e04c2c0418a14b83c549a2828610 Mon Sep 17 00:00:00 2001 +From: Oliver Brown +Date: Wed, 13 Dec 2017 17:12:45 -0600 +Subject: [PATCH 12/15] MLK-17205-2 video: imx: hdp: Adding HDP firmware + loading to the build + +Adding the HDP firmware loading to the build. + +Signed-off-by: Oliver Brown +(cherry picked from downstream commit d4702582552aa1921fce58329ae40c24481fba3a) +--- + drivers/video/Kconfig | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig +index c3781b160d..a40df01500 100644 +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -549,6 +549,15 @@ config VIDEO + model. Video drivers typically provide a colour text console and + cursor. + ++config VIDEO_IMX_HDP_LOAD ++ bool "i.MX8 HDMI/DP firmware loading" ++ default n ++ depends on IMX8 ++ help ++ Support for HDMI/DP firmware loading for i.MX8QM processors. The ++ firmware is copied from system memory to the HDMI/DP IRAM and ++ DRAM memory. ++ + config CFB_CONSOLE + bool "Enable colour frame buffer console" + depends on VIDEO +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0012-imx8-cpu-get-temperature-when-print-cpu-desc.patch b/recipes-bsp/u-boot-mainline/files/0012-imx8-cpu-get-temperature-when-print-cpu-desc.patch deleted file mode 100644 index f700305..0000000 --- a/recipes-bsp/u-boot-mainline/files/0012-imx8-cpu-get-temperature-when-print-cpu-desc.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 82467cb2172d0470413876ad398d032a649a7e11 Mon Sep 17 00:00:00 2001 -From: Peng Fan -Date: Fri, 12 Apr 2019 07:55:06 +0000 -Subject: [PATCH 12/19] imx8: cpu: get temperature when print cpu desc - -Read the temperature when print cpu inforation. - -Signed-off-by: Peng Fan ---- - arch/arm/mach-imx/imx8/cpu.c | 35 +++++++++++++++++++++++++++++++++-- - 1 file changed, 33 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c -index 2c425357b5..12716e7e9e 100644 ---- a/arch/arm/mach-imx/imx8/cpu.c -+++ b/arch/arm/mach-imx/imx8/cpu.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -573,15 +574,45 @@ const char *get_core_name(void) - return "?"; - } - -+#if defined(CONFIG_IMX_SCU_THERMAL) -+static int cpu_imx_get_temp(void) -+{ -+ struct udevice *thermal_dev; -+ int cpu_tmp, ret; -+ -+ ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0", -+ &thermal_dev); -+ -+ if (!ret) { -+ ret = thermal_get_temp(thermal_dev, &cpu_tmp); -+ if (ret) -+ return 0xdeadbeef; -+ } else { -+ return 0xdeadbeef; -+ } -+ -+ return cpu_tmp; -+} -+#endif -+ - int cpu_imx_get_desc(struct udevice *dev, char *buf, int size) - { - struct cpu_imx_platdata *plat = dev_get_platdata(dev); -+ int ret; - - if (size < 100) - return -ENOSPC; - -- snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n", -- plat->type, plat->rev, plat->name, plat->freq_mhz); -+ ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz", -+ plat->type, plat->rev, plat->name, plat->freq_mhz); -+ -+ if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) { -+ buf = buf + ret; -+ size = size - ret; -+ ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp()); -+ } -+ -+ snprintf(buf + ret, size - ret, "\n"); - - return 0; - } --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0013-MLK-17205-3-video-imx-hdp-Adding-configs-for-HDP-fir.patch b/recipes-bsp/u-boot-mainline/files/0013-MLK-17205-3-video-imx-hdp-Adding-configs-for-HDP-fir.patch new file mode 100644 index 0000000..8c31bcb --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0013-MLK-17205-3-video-imx-hdp-Adding-configs-for-HDP-fir.patch @@ -0,0 +1,54 @@ +From a646aace8bfd6fc83e360c2fd0c406812922ba5f Mon Sep 17 00:00:00 2001 +From: Oliver Brown +Date: Wed, 13 Dec 2017 17:14:58 -0600 +Subject: [PATCH 13/15] MLK-17205-3 video: imx: hdp: Adding configs for HDP + firmware loading + +Added default environment for hdp loading. +Added hdp loading as default for iMX8QM MEK board. + +Signed-off-by: Oliver Brown +(cherry picked from downstream commit 432e5b4347841095c3b5a8a0d106f35deadd006e) +(cherry picked from downstream commit cb78a32fa8eb8c37932be003ebe4fa1f8c46c1d5) +--- + configs/imx8qm_mek_defconfig | 1 + + include/configs/imx8qm_mek.h | 5 +++++ + 2 files changed, 6 insertions(+) + +diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig +index 1c67b98c5d..5aae2fd0d9 100644 +--- a/configs/imx8qm_mek_defconfig ++++ b/configs/imx8qm_mek_defconfig +@@ -74,4 +74,5 @@ CONFIG_SPL_DM_REGULATOR_GPIO=y + CONFIG_DM_SERIAL=y + CONFIG_FSL_LPUART=y + CONFIG_SPL_TINY_MEMSET=y ++CONFIG_VIDEO_IMX_HDP_LOAD=y + # CONFIG_EFI_LOADER is not set +diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h +index d06ed61c80..32fcf7eb8f 100644 +--- a/include/configs/imx8qm_mek.h ++++ b/include/configs/imx8qm_mek.h +@@ -80,7 +80,11 @@ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ ++ "hdp_addr=0x84000000\0" \ ++ "hdp_file=hdmitxfw.bin\0" \ ++ "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ ++ "if run loadhdp; then; hdp load ${hdp_addr}; fi;" \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ +@@ -101,6 +105,7 @@ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ ++ "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0013-imx-imx8dx-qxp-enable-thermal.patch b/recipes-bsp/u-boot-mainline/files/0013-imx-imx8dx-qxp-enable-thermal.patch deleted file mode 100644 index 3caa779..0000000 --- a/recipes-bsp/u-boot-mainline/files/0013-imx-imx8dx-qxp-enable-thermal.patch +++ /dev/null @@ -1,103 +0,0 @@ -From ca9e4fef07365d39566288a45670c75d320e2f32 Mon Sep 17 00:00:00 2001 -From: Peng Fan -Date: Fri, 12 Apr 2019 07:55:09 +0000 -Subject: [PATCH 13/19] imx: imx8dx/qxp: enable thermal - -Add thermal dts node -Enable thermal in defconfig - -Signed-off-by: Peng Fan ---- - arch/arm/dts/fsl-imx8dx.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++++ - configs/imx8qxp_mek_defconfig | 2 ++ - 2 files changed, 58 insertions(+) - -diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi -index 715abb413d..4fc87a9fc8 100644 ---- a/arch/arm/dts/fsl-imx8dx.dtsi -+++ b/arch/arm/dts/fsl-imx8dx.dtsi -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - - / { - model = "Freescale i.MX8DX"; -@@ -543,6 +544,61 @@ - power-domains = <&pd_conn_enet1>; - status = "disabled"; - }; -+ -+ tsens: thermal-sensor { -+ compatible = "nxp,imx8qxp-sc-tsens"; -+ /* number of the temp sensor on the chip */ -+ tsens-num = <2>; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ thermal_zones: thermal-zones { -+ /* cpu thermal */ -+ cpu-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ /*the slope and offset of the temp sensor */ -+ thermal-sensors = <&tsens 0>; -+ trips { -+ cpu_alert0: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit0: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert0>; -+ cooling-device = -+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ drc-thermal0 { -+ polling-delay-passive = <250>; -+ polling-delay = <2000>; -+ thermal-sensors = <&tsens 1>; -+ status = "disabled"; -+ trips { -+ drc_alert0: trip0 { -+ temperature = <107000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ drc_crit0: trip1 { -+ temperature = <127000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; - }; - - &A35_0 { -diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig -index 2fb2fdf7ff..6101f62087 100644 ---- a/configs/imx8qxp_mek_defconfig -+++ b/configs/imx8qxp_mek_defconfig -@@ -74,5 +74,7 @@ CONFIG_DM_REGULATOR_GPIO=y - CONFIG_SPL_DM_REGULATOR_GPIO=y - CONFIG_DM_SERIAL=y - CONFIG_FSL_LPUART=y -+CONFIG_DM_THERMAL=y -+CONFIG_IMX_SCU_THERMAL=y - CONFIG_SPL_TINY_MEMSET=y - # CONFIG_EFI_LOADER is not set --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0014-apalis-imx8-enable-hdp-firmware-loading.patch b/recipes-bsp/u-boot-mainline/files/0014-apalis-imx8-enable-hdp-firmware-loading.patch new file mode 100644 index 0000000..64c6ccc --- /dev/null +++ b/recipes-bsp/u-boot-mainline/files/0014-apalis-imx8-enable-hdp-firmware-loading.patch @@ -0,0 +1,65 @@ +From fbbde5249ec74fdb0873438e13d1e55f5214ed72 Mon Sep 17 00:00:00 2001 +From: Marcel Ziswiler +Date: Fri, 31 May 2019 10:32:32 +0300 +Subject: [PATCH 14/15] apalis-imx8: enable hdp firmware loading + +Signed-off-by: Marcel Ziswiler +--- + configs/apalis-imx8qm_defconfig | 1 + + include/configs/apalis-imx8.h | 13 +++++++++++-- + 2 files changed, 12 insertions(+), 2 deletions(-) + +diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig +index d7dfc4a27b..f1c5511fd0 100644 +--- a/configs/apalis-imx8qm_defconfig ++++ b/configs/apalis-imx8qm_defconfig +@@ -55,4 +55,5 @@ CONFIG_DM_SERIAL=y + CONFIG_FSL_LPUART=y + CONFIG_DM_THERMAL=y + CONFIG_IMX_SCU_THERMAL=y ++CONFIG_VIDEO_IMX_HDP_LOAD=y + # CONFIG_EFI_LOADER is not set +diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h +index be2c5a2293..e5f0d1396a 100644 +--- a/include/configs/apalis-imx8.h ++++ b/include/configs/apalis-imx8.h +@@ -61,9 +61,12 @@ + "fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \ + "fdtfile=fsl-imx8qm-apalis-eval.dtb\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ ++ "hdp_addr=0x84000000\0" \ ++ "hdp_file=hdmitxfw.bin\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ ++ "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=PARTUUID=${uuid} rootwait " \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ +@@ -71,8 +74,10 @@ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ + "\0" \ +- "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ +- "apalis-imx8/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \ ++ "nfsboot=run netargs; dhcp ${loadaddr} ${image}; if tftp ${hdp_addr} " \ ++ "${hdp_file}; then; hdp load ${hdp_addr}; fi; tftp " \ ++ "${fdt_addr} apalis-imx8/${fdt_file}; booti ${loadaddr} - " \ ++ "${fdt_addr}\0" \ + "panel=NULL\0" \ + "script=boot.scr\0" \ + "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ +@@ -81,6 +86,10 @@ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ + "${blkcnt}; fi\0" + ++#undef CONFIG_BOOTCOMMAND ++#define CONFIG_BOOTCOMMAND \ ++ "if run loadhdp; then; hdp load ${hdp_addr}; fi; run distro_bootcmd" ++ + /* Link Definitions */ + #define CONFIG_LOADADDR 0x80280000 + +-- +2.13.6 + diff --git a/recipes-bsp/u-boot-mainline/files/0014-arm-dts-imx8qm-add-lpuart1-lpuart2-lpuart3-lpuart4.patch b/recipes-bsp/u-boot-mainline/files/0014-arm-dts-imx8qm-add-lpuart1-lpuart2-lpuart3-lpuart4.patch deleted file mode 100644 index c5ff58b..0000000 --- a/recipes-bsp/u-boot-mainline/files/0014-arm-dts-imx8qm-add-lpuart1-lpuart2-lpuart3-lpuart4.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 32ff3f8ecf03f60627d4e92de9a34b2fc2cdaf4d Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Mon, 29 Apr 2019 01:22:42 +0200 -Subject: [PATCH 14/19] arm: dts: imx8qm: add lpuart1, lpuart2, lpuart3, - lpuart4 - -Add support for lpuart1, lpuart2, lpuart3 and lpuart4. - -Signed-off-by: Marcel Ziswiler -Reviewed-by: Max Krummenacher ---- - arch/arm/dts/fsl-imx8qm.dtsi | 80 ++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 80 insertions(+) - -diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi -index b39c40bd98..db01959990 100644 ---- a/arch/arm/dts/fsl-imx8qm.dtsi -+++ b/arch/arm/dts/fsl-imx8qm.dtsi -@@ -22,6 +22,10 @@ - ethernet0 = &fec1; - ethernet1 = &fec2; - serial0 = &lpuart0; -+ serial1 = &lpuart1; -+ serial2 = &lpuart2; -+ serial3 = &lpuart3; -+ serial4 = &lpuart4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; -@@ -193,6 +197,30 @@ - power-domains = <&pd_dma>; - wakeup-irq = <345>; - }; -+ pd_dma_lpuart1: PD_DMA_UART1 { -+ reg = ; -+ #power-domain-cells = <0>; -+ power-domains = <&pd_dma>; -+ wakeup-irq = <346>; -+ }; -+ pd_dma_lpuart2: PD_DMA_UART2 { -+ reg = ; -+ #power-domain-cells = <0>; -+ power-domains = <&pd_dma>; -+ wakeup-irq = <347>; -+ }; -+ pd_dma_lpuart3: PD_DMA_UART3 { -+ reg = ; -+ #power-domain-cells = <0>; -+ power-domains = <&pd_dma>; -+ wakeup-irq = <348>; -+ }; -+ pd_dma_lpuart4: PD_DMA_UART4 { -+ reg = ; -+ #power-domain-cells = <0>; -+ power-domains = <&pd_dma>; -+ wakeup-irq = <349>; -+ }; - }; - }; - -@@ -297,6 +325,58 @@ - status = "disabled"; - }; - -+ lpuart1: serial@5a070000 { -+ compatible = "fsl,imx8qm-lpuart"; -+ reg = <0x0 0x5a070000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8QM_UART1_CLK>, -+ <&clk IMX8QM_UART1_IPG_CLK>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX8QM_UART1_CLK>; -+ assigned-clock-rates = <80000000>; -+ power-domains = <&pd_dma_lpuart1>; -+ status = "disabled"; -+ }; -+ -+ lpuart2: serial@5a080000 { -+ compatible = "fsl,imx8qm-lpuart"; -+ reg = <0x0 0x5a080000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8QM_UART2_CLK>, -+ <&clk IMX8QM_UART2_IPG_CLK>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX8QM_UART2_CLK>; -+ assigned-clock-rates = <80000000>; -+ power-domains = <&pd_dma_lpuart2>; -+ status = "disabled"; -+ }; -+ -+ lpuart3: serial@5a090000 { -+ compatible = "fsl,imx8qm-lpuart"; -+ reg = <0x0 0x5a090000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8QM_UART3_CLK>, -+ <&clk IMX8QM_UART3_IPG_CLK>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX8QM_UART3_CLK>; -+ assigned-clock-rates = <80000000>; -+ power-domains = <&pd_dma_lpuart3>; -+ status = "disabled"; -+ }; -+ -+ lpuart4: serial@5a0a0000 { -+ compatible = "fsl,imx8qm-lpuart"; -+ reg = <0x0 0x5a0a0000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&clk IMX8QM_UART4_CLK>, -+ <&clk IMX8QM_UART4_IPG_CLK>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX8QM_UART4_CLK>; -+ assigned-clock-rates = <80000000>; -+ power-domains = <&pd_dma_lpuart4>; -+ status = "disabled"; -+ }; -+ - usdhc1: usdhc@5b010000 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; - interrupt-parent = <&gic>; --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0015-arm-dts-imx8qm-add-support-for-i2c0-i2c1-i2c2-i2c3-a.patch b/recipes-bsp/u-boot-mainline/files/0015-arm-dts-imx8qm-add-support-for-i2c0-i2c1-i2c2-i2c3-a.patch deleted file mode 100644 index 2e92485..0000000 --- a/recipes-bsp/u-boot-mainline/files/0015-arm-dts-imx8qm-add-support-for-i2c0-i2c1-i2c2-i2c3-a.patch +++ /dev/null @@ -1,110 +0,0 @@ -From c3717078539984c45329200a1b8fed171d651f33 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Mon, 29 Apr 2019 18:03:46 +0200 -Subject: [PATCH 15/19] arm: dts: imx8qm: add support for i2c0, i2c1, i2c2, - i2c3 and i2c4 - -Add support for i2c0, i2c1, i2c2, i2c3 and i2c4. - -Signed-off-by: Marcel Ziswiler -Reviewed-by: Max Krummenacher ---- - arch/arm/dts/fsl-imx8qm.dtsi | 75 ++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 75 insertions(+) - -diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi -index db01959990..af060db3a1 100644 ---- a/arch/arm/dts/fsl-imx8qm.dtsi -+++ b/arch/arm/dts/fsl-imx8qm.dtsi -@@ -29,6 +29,11 @@ - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c2 = &i2c2; -+ i2c3 = &i2c3; -+ i2c4 = &i2c4; - }; - - memory@80000000 { -@@ -224,6 +229,76 @@ - }; - }; - -+ i2c0: i2c@5a800000 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x0 0x5a800000 0x0 0x4000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&clk IMX8QM_I2C0_CLK>, -+ <&clk IMX8QM_I2C0_IPG_CLK>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX8QM_I2C0_CLK>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd_dma_lpi2c0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@5a810000 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x0 0x5a810000 0x0 0x4000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&clk IMX8QM_I2C1_CLK>, -+ <&clk IMX8QM_I2C1_IPG_CLK>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX8QM_I2C1_CLK>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd_dma_lpi2c1>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@5a820000 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x0 0x5a820000 0x0 0x4000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&clk IMX8QM_I2C2_CLK>, -+ <&clk IMX8QM_I2C2_IPG_CLK>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX8QM_I2C2_CLK>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd_dma_lpi2c2>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@5a830000 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x0 0x5a830000 0x0 0x4000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&clk IMX8QM_I2C3_CLK>, -+ <&clk IMX8QM_I2C3_IPG_CLK>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX8QM_I2C3_CLK>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd_dma_lpi2c3>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@5a840000 { -+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; -+ reg = <0x0 0x5a840000 0x0 0x4000>; -+ interrupts = ; -+ interrupt-parent = <&gic>; -+ clocks = <&clk IMX8QM_I2C4_CLK>, -+ <&clk IMX8QM_I2C4_IPG_CLK>; -+ clock-names = "per", "ipg"; -+ assigned-clocks = <&clk IMX8QM_I2C4_CLK>; -+ assigned-clock-rates = <24000000>; -+ power-domains = <&pd_dma_lpi2c4>; -+ status = "disabled"; -+ }; -+ - gpio0: gpio@5d080000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d080000 0x0 0x10000>; --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch b/recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch deleted file mode 100644 index 5ef6305..0000000 --- a/recipes-bsp/u-boot-mainline/files/0016-clk-imx8qm-fix-usdhc2-clocks.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 025a98d87d9e2274a438d3878428c04abf4fc717 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Mon, 29 Apr 2019 17:57:24 +0200 -Subject: [PATCH 16/19] clk: imx8qm: fix usdhc2 clocks - -Trying to bring up uSDHC2 the following error message was observed: - -MMC: imx8_clk_set_rate(Invalid clk ID #60) -imx8_clk_set_rate(Invalid clk ID #60) -usdhc@5b030000 - probe failed: -22 - -This commit fixes this by properly setting resp. clocks. - -Signed-off-by: Marcel Ziswiler -Reviewed-by: Max Krummenacher ---- - drivers/clk/imx/clk-imx8qm.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c -index 6b5561e178..a6b09d2109 100644 ---- a/drivers/clk/imx/clk-imx8qm.c -+++ b/drivers/clk/imx/clk-imx8qm.c -@@ -80,6 +80,12 @@ ulong imx8_clk_get_rate(struct clk *clk) - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; -+ case IMX8QM_SDHC2_IPG_CLK: -+ case IMX8QM_SDHC2_CLK: -+ case IMX8QM_SDHC2_DIV: -+ resource = SC_R_SDHC_2; -+ pm_clk = SC_PM_CLK_PER; -+ break; - case IMX8QM_UART0_IPG_CLK: - case IMX8QM_UART0_CLK: - resource = SC_R_UART_0; -@@ -185,6 +191,12 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; -+ case IMX8QM_SDHC2_IPG_CLK: -+ case IMX8QM_SDHC2_CLK: -+ case IMX8QM_SDHC2_DIV: -+ resource = SC_R_SDHC_2; -+ pm_clk = SC_PM_CLK_PER; -+ break; - case IMX8QM_ENET0_IPG_CLK: - case IMX8QM_ENET0_AHB_CLK: - case IMX8QM_ENET0_REF_DIV: -@@ -273,6 +285,12 @@ int __imx8_clk_enable(struct clk *clk, bool enable) - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; -+ case IMX8QM_SDHC2_IPG_CLK: -+ case IMX8QM_SDHC2_CLK: -+ case IMX8QM_SDHC2_DIV: -+ resource = SC_R_SDHC_2; -+ pm_clk = SC_PM_CLK_PER; -+ break; - case IMX8QM_ENET0_IPG_CLK: - case IMX8QM_ENET0_AHB_CLK: - case IMX8QM_ENET0_REF_DIV: --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0017-imx8qm-fix-cpu-frequency-reporting.patch b/recipes-bsp/u-boot-mainline/files/0017-imx8qm-fix-cpu-frequency-reporting.patch deleted file mode 100644 index 088c2d2..0000000 --- a/recipes-bsp/u-boot-mainline/files/0017-imx8qm-fix-cpu-frequency-reporting.patch +++ /dev/null @@ -1,40 +0,0 @@ -From c54d289c92c963d449ad91fd683e13180b88c3b1 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Tue, 30 Apr 2019 09:50:50 +0200 -Subject: [PATCH 17/19] imx8qm: fix cpu frequency reporting - -CPU frequency reporting failed with the following error message being -printed: - -sc_pm_get_clock_rate: resource:507 clk:2: res:3 -Could not read CPU frequency: -22 -CPU: NXP i.MX8QM RevB A53 at 0 MHz - -Fix this by differentiating between the A35 as found on the i.MX 8QXP -and the A53 as found on the i.MX 8QM SoCs. - -Signed-off-by: Marcel Ziswiler -Reviewed-by: Max Krummenacher ---- - arch/arm/mach-imx/imx8/cpu.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c -index 12716e7e9e..12596c6387 100644 ---- a/arch/arm/mach-imx/imx8/cpu.c -+++ b/arch/arm/mach-imx/imx8/cpu.c -@@ -654,8 +654,10 @@ static ulong imx8_get_cpu_rate(void) - { - ulong rate; - int ret; -+ int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ? -+ SC_R_A53 : SC_R_A72; - -- ret = sc_pm_get_clock_rate(-1, SC_R_A35, SC_PM_CLK_CPU, -+ ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU, - (sc_pm_clock_rate_t *)&rate); - if (ret) { - printf("Could not read CPU frequency: %d\n", ret); --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0018-imx8-fuse-fix-fuse-driver.patch b/recipes-bsp/u-boot-mainline/files/0018-imx8-fuse-fix-fuse-driver.patch deleted file mode 100644 index 9177373..0000000 --- a/recipes-bsp/u-boot-mainline/files/0018-imx8-fuse-fix-fuse-driver.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 07345149dd07e6b9adec1fa8358663ec8202242b Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Tue, 30 Apr 2019 10:08:55 +0200 -Subject: [PATCH 18/19] imx8: fuse: fix fuse driver - -This fixes the i.MX 8 fuse driver to actually build for i.MX 8QM as -well. - -Signed-off-by: Marcel Ziswiler -Reviewed-by: Max Krummenacher ---- - drivers/misc/imx8/fuse.c | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c -index 29d2256a22..2f2fad2c17 100644 ---- a/drivers/misc/imx8/fuse.c -+++ b/drivers/misc/imx8/fuse.c -@@ -15,13 +15,11 @@ DECLARE_GLOBAL_DATA_PTR; - #define FSL_ECC_WORD_START_1 0x10 - #define FSL_ECC_WORD_END_1 0x10F - --#ifdef CONFIG_IMX8QXP - #define FSL_ECC_WORD_START_2 0x220 - #define FSL_ECC_WORD_END_2 0x31F - - #define FSL_QXP_FUSE_GAP_START 0x110 - #define FSL_QXP_FUSE_GAP_END 0x21F --#endif - - #define FSL_SIP_OTP_READ 0xc200000A - #define FSL_SIP_OTP_WRITE 0xc200000B --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/0019-board-toradex-add-apalis-imx8qm-4gb-wb-it-v1.0b-modu.patch b/recipes-bsp/u-boot-mainline/files/0019-board-toradex-add-apalis-imx8qm-4gb-wb-it-v1.0b-modu.patch deleted file mode 100644 index 4102993..0000000 --- a/recipes-bsp/u-boot-mainline/files/0019-board-toradex-add-apalis-imx8qm-4gb-wb-it-v1.0b-modu.patch +++ /dev/null @@ -1,1434 +0,0 @@ -From 6c5418e7567c367c76c7657726cdea85e497a470 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler -Date: Mon, 29 Apr 2019 01:24:25 +0200 -Subject: [PATCH 19/19] board: toradex: add apalis imx8qm 4gb wb it v1.0b - module support - -This commit adds initial support for the Toradex Apalis iMX8QM 4GB WB IT -V1.0B module. Unlike the V1.0A early access samples exclusively booting -from SD card, they are now strapped to boot from eFuses which are -factory fused to properly boot from their on-module eMMC. U-Boot -supports either booting from the on-module eMMC or may be used for -recovery purpose using the universal update utility (uuu) aka mfgtools -3.0. - -Functionality wise the following is known to be working: -- eMMC, 8-bit and 4-bit MMC/SD card slots -- Gigabit Ethernet -- GPIOs -- I2C - -Unfortunately, there is no USB functionality for the i.MX 8QM as of yet. - -Signed-off-by: Marcel Ziswiler -Reviewed-by: Max Krummenacher - -Series-to: u-boot@lists.denx.de - -Series-version: 2 - -Series-changes: 2 -- Use firmware-imx-8.0 matching NXP's sumo-4.14.78-1.0.0_ga BSP as - suggested by Max. -- Drop Qualcomm (formwerly Atheros) AR8031 specific board_phy_config() - stuff not applicable to the Micrel PHY we are using as suggested by Max. -- Drop CONFIG_FEC_XCV_TYPE in favour of device tree configuration therof - as suggested by Max. - -Cover-letter: -apalis imx8qm 4gb wb it v1.0b module support - -This series adds support for more lpuart instances, support for i2c0, -i2c1, i2c2, i2c3, i2c4, fixes support for uSDHC2, fixes CPU frequency -reporting, fixes fuse driver and last but not least introduces support -for the Toradex Apalis iMX8QM 4GB WB IT V1.0B module. - -This series is available together with the last few clean-up patches -and the Colibri iMX8QXP patch series on our git server [1] as well. - -[1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next -END ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 128 ++++++ - arch/arm/dts/fsl-imx8qm-apalis.dts | 615 ++++++++++++++++++++++++++++ - arch/arm/mach-imx/imx8/Kconfig | 6 + - board/toradex/apalis-imx8qm/Kconfig | 30 ++ - board/toradex/apalis-imx8qm/MAINTAINERS | 9 + - board/toradex/apalis-imx8qm/Makefile | 6 + - board/toradex/apalis-imx8qm/README | 66 +++ - board/toradex/apalis-imx8qm/apalis-imx8qm.c | 149 +++++++ - board/toradex/apalis-imx8qm/imximage.cfg | 24 ++ - configs/apalis-imx8qm_defconfig | 56 +++ - include/configs/apalis-imx8qm.h | 177 ++++++++ - 12 files changed, 1267 insertions(+) - create mode 100644 arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi - create mode 100644 arch/arm/dts/fsl-imx8qm-apalis.dts - create mode 100644 board/toradex/apalis-imx8qm/Kconfig - create mode 100644 board/toradex/apalis-imx8qm/MAINTAINERS - create mode 100644 board/toradex/apalis-imx8qm/Makefile - create mode 100644 board/toradex/apalis-imx8qm/README - create mode 100644 board/toradex/apalis-imx8qm/apalis-imx8qm.c - create mode 100644 board/toradex/apalis-imx8qm/imximage.cfg - create mode 100644 configs/apalis-imx8qm_defconfig - create mode 100644 include/configs/apalis-imx8qm.h - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 598dc213e3..2c1cf3122a 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -576,6 +576,7 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ - dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb - - dtb-$(CONFIG_ARCH_IMX8) += \ -+ fsl-imx8qm-apalis.dtb \ - fsl-imx8qm-mek.dtb \ - fsl-imx8qxp-colibri.dtb \ - fsl-imx8qxp-mek.dtb -diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi -new file mode 100644 -index 0000000000..7b1a9550e4 ---- /dev/null -+++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi -@@ -0,0 +1,128 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR X11 -+/* -+ * Copyright 2019 Toradex AG -+ */ -+ -+&mu { -+ u-boot,dm-spl; -+}; -+ -+&clk { -+ u-boot,dm-spl; -+}; -+ -+&iomuxc { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio0 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio1 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio2 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio3 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio4 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio5 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio6 { -+ u-boot,dm-spl; -+}; -+ -+&pd_lsio_gpio7 { -+ u-boot,dm-spl; -+}; -+ -+&pd_conn { -+ u-boot,dm-spl; -+}; -+ -+&pd_conn_sdch0 { -+ u-boot,dm-spl; -+}; -+ -+&pd_conn_sdch1 { -+ u-boot,dm-spl; -+}; -+ -+&pd_conn_sdch2 { -+ u-boot,dm-spl; -+}; -+ -+&gpio0 { -+ u-boot,dm-spl; -+}; -+ -+&gpio1 { -+ u-boot,dm-spl; -+}; -+ -+&gpio2 { -+ u-boot,dm-spl; -+}; -+ -+&gpio3 { -+ u-boot,dm-spl; -+}; -+ -+&gpio4 { -+ u-boot,dm-spl; -+}; -+ -+&gpio5 { -+ u-boot,dm-spl; -+}; -+ -+&gpio6 { -+ u-boot,dm-spl; -+}; -+ -+&gpio7 { -+ u-boot,dm-spl; -+}; -+ -+&lpuart0 { -+ u-boot,dm-spl; -+}; -+ -+&lpuart1 { -+ u-boot,dm-spl; -+}; -+ -+&lpuart2 { -+ u-boot,dm-spl; -+}; -+ -+&lpuart3 { -+ u-boot,dm-spl; -+}; -+ -+&usdhc1 { -+ u-boot,dm-spl; -+}; -+ -+&usdhc2 { -+ u-boot,dm-spl; -+}; -+ -+&usdhc3 { -+ u-boot,dm-spl; -+}; -diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts -new file mode 100644 -index 0000000000..9b1f8aa32d ---- /dev/null -+++ b/arch/arm/dts/fsl-imx8qm-apalis.dts -@@ -0,0 +1,615 @@ -+// SPDX-License-Identifier: GPL-2.0+ OR X11 -+/* -+ * Copyright 2017-2019 Toradex -+ */ -+ -+/dts-v1/; -+ -+/* First 128KB is for PSCI ATF. */ -+/memreserve/ 0x80000000 0x00020000; -+ -+#include "fsl-imx8qm.dtsi" -+#include "fsl-imx8qm-apalis-u-boot.dtsi" -+ -+/ { -+ model = "Toradex Apalis iMX8QM"; -+ compatible = "toradex,apalis-imx8qm", "fsl,imx8qm"; -+ -+ chosen { -+ bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200"; -+ stdout-path = &lpuart1; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, -+ <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, -+ <&pinctrl_gpio12>, <&pinctrl_gpio34>, <&pinctrl_gpio56>, -+ <&pinctrl_gpio7>, <&pinctrl_gpio8>, <&pinctrl_gpio_bkl_on>, -+ <&pinctrl_gpio_keys>, <&pinctrl_gpio_pwm0>, -+ <&pinctrl_gpio_pwm1>, <&pinctrl_gpio_pwm2>, -+ <&pinctrl_gpio_pwm3>, <&pinctrl_gpio_pwm_bkl>, -+ <&pinctrl_gpio_usbh_en>, <&pinctrl_gpio_usbh_oc_n>, -+ <&pinctrl_gpio_usbo1_en>, <&pinctrl_gpio_usbo1_oc_n>, -+ <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, -+ <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, -+ <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, -+ <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>, -+ <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>; -+ -+ apalis-imx8qm { -+ pinctrl_gpio12: gpio12grp { -+ fsl,pins = < -+ /* Apalis GPIO1 */ -+ SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021 -+ /* Apalis GPIO2 */ -+ SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021 -+ >; -+ }; -+ -+ pinctrl_gpio34: gpio34grp { -+ fsl,pins = < -+ /* Apalis GPIO3 */ -+ SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021 -+ /* Apalis GPIO4 */ -+ SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021 -+ >; -+ }; -+ -+ pinctrl_gpio56: gpio56grp { -+ fsl,pins = < -+ /* Apalis GPIO5 */ -+ SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021 -+ /* Apalis GPIO6 */ -+ SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x06000021 -+ >; -+ }; -+ -+ pinctrl_gpio7: gpio7 { -+ fsl,pins = < -+ /* Apalis GPIO7 */ -+ SC_P_MLB_SIG_LSIO_GPIO3_IO26 0x00000021 -+ >; -+ }; -+ -+ pinctrl_gpio8: gpio8 { -+ fsl,pins = < -+ /* Apalis GPIO8 */ -+ SC_P_MLB_DATA_LSIO_GPIO3_IO28 0x00000021 -+ >; -+ }; -+ -+ pinctrl_gpio_keys: gpio-keys { -+ fsl,pins = < -+ /* Apalis WAKE1_MICO */ -+ SC_P_SPI3_CS0_LSIO_GPIO2_IO20 0x06000021 -+ >; -+ }; -+ -+ pinctrl_fec1: fec1grp { -+ fsl,pins = < -+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 3.3V mode */ -+ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 -+ SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 -+ SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 -+ SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 -+ SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 -+ SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 -+ SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 -+ SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 -+ SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 -+ SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 -+ SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 -+ SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 -+ SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 -+ SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 -+ SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020 -+ /* ETH_RESET# */ -+ SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020 -+ >; -+ }; -+ -+ pinctrl_gpio_bkl_on: gpio-bkl-on { -+ fsl,pins = < -+ /* Apalis BKL_ON */ -+ SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021 -+ >; -+ }; -+ -+ /* Apalis I2C2 (DDC) */ -+ pinctrl_lpi2c0: lpi2c0grp { -+ fsl,pins = < -+ SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022 -+ SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022 -+ >; -+ }; -+ -+ pinctrl_cam1_gpios: cam1gpiosgrp { -+ fsl,pins = < -+ /* Apalis CAM1_D7 */ -+ SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021 -+ /* Apalis CAM1_D6 */ -+ SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021 -+ /* Apalis CAM1_D5 */ -+ SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021 -+ /* Apalis CAM1_D4 */ -+ SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021 -+ /* Apalis CAM1_D3 */ -+ SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021 -+ /* Apalis CAM1_D2 */ -+ SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021 -+ /* Apalis CAM1_D1 */ -+ SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021 -+ /* Apalis CAM1_D0 */ -+ SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021 -+ /* Apalis CAM1_PCLK */ -+ SC_P_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021 -+ /* Apalis CAM1_MCLK */ -+ SC_P_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021 -+ /* Apalis CAM1_VSYNC */ -+ SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021 -+ /* Apalis CAM1_HSYNC */ -+ SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021 -+ >; -+ }; -+ -+ pinctrl_dap1_gpios: dap1gpiosgrp { -+ fsl,pins = < -+ /* Apalis DAP1_MCLK */ -+ SC_P_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021 -+ /* Apalis DAP1_D_OUT */ -+ SC_P_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021 -+ /* Apalis DAP1_RESET */ -+ SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021 -+ /* Apalis DAP1_BIT_CLK */ -+ SC_P_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021 -+ /* Apalis DAP1_D_IN */ -+ SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021 -+ /* Apalis DAP1_SYNC */ -+ SC_P_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021 -+ /* Wi-Fi_I2S_EN# */ -+ SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021 -+ >; -+ }; -+ -+ pinctrl_esai0_gpios: esai0gpiosgrp { -+ fsl,pins = < -+ /* Apalis LCD1_G1 */ -+ SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021 -+ /* Apalis LCD1_G2 */ -+ SC_P_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021 -+ >; -+ }; -+ -+ pinctrl_fec2_gpios: fec2gpiosgrp { -+ fsl,pins = < -+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 -+ /* Apalis LCD1_R1 */ -+ SC_P_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021 -+ /* Apalis LCD1_R0 */ -+ SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021 -+ /* Apalis LCD1_G0 */ -+ SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021 -+ /* Apalis LCD1_R7 */ -+ SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021 -+ /* Apalis LCD1_DE */ -+ SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021 -+ /* Apalis LCD1_HSYNC */ -+ SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021 -+ /* Apalis LCD1_VSYNC */ -+ SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021 -+ /* Apalis LCD1_PCLK */ -+ SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021 -+ /* Apalis LCD1_R6 */ -+ SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021 -+ /* Apalis LCD1_R5 */ -+ SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021 -+ /* Apalis LCD1_R4 */ -+ SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021 -+ /* Apalis LCD1_R3 */ -+ SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021 -+ /* Apalis LCD1_R2 */ -+ SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021 -+ >; -+ }; -+ -+ pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpio { -+ fsl,pins = < -+ /* Apalis TS_2 */ -+ SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021 -+ >; -+ }; -+ -+ pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp { -+ fsl,pins = < -+ /* Apalis LCD1_G6 */ -+ SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021 -+ /* Apalis LCD1_G7 */ -+ SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021 -+ >; -+ }; -+ -+ pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp { -+ fsl,pins = < -+ /* Apalis TS_4 */ -+ SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021 -+ >; -+ }; -+ -+ pinctrl_mlb_gpios: mlbgpiosgrp { -+ fsl,pins = < -+ /* Apalis TS_1 */ -+ SC_P_MLB_CLK_LSIO_GPIO3_IO27 0x00000021 -+ >; -+ }; -+ -+ pinctrl_qspi1a_gpios: qspi1agpiosgrp { -+ fsl,pins = < -+ /* Apalis LCD1_B0 */ -+ SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 -+ /* Apalis LCD1_B1 */ -+ SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021 -+ /* Apalis LCD1_B2 */ -+ SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021 -+ /* Apalis LCD1_B3 */ -+ SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021 -+ /* Apalis LCD1_B5 */ -+ SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 -+ /* Apalis LCD1_B7 */ -+ SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021 -+ /* Apalis LCD1_B4 */ -+ SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021 -+ /* Apalis LCD1_B6 */ -+ SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021 -+ >; -+ }; -+ -+ pinctrl_sim0_gpios: sim0gpiosgrp { -+ fsl,pins = < -+ /* Apalis LCD1_G5 */ -+ SC_P_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021 -+ /* Apalis LCD1_G3 */ -+ SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021 -+ /* Apalis TS_5 */ -+ SC_P_SIM0_IO_LSIO_GPIO0_IO02 0x00000021 -+ /* Apalis LCD1_G4 */ -+ SC_P_SIM0_RST_LSIO_GPIO0_IO01 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc1_gpios: usdhc1gpiosgrp { -+ fsl,pins = < -+ /* Apalis TS_6 */ -+ SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021 -+ >; -+ }; -+ -+ pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { -+ fsl,pins = < -+ /* Apalis TS_3 */ -+ SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 -+ >; -+ }; -+ -+ /* On-module I2C */ -+ pinctrl_lpi2c1: lpi2c1grp { -+ fsl,pins = < -+ SC_P_GPT0_CLK_DMA_I2C1_SCL 0x04000020 -+ SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020 -+ >; -+ }; -+ -+ /* Apalis I2C1 */ -+ pinctrl_lpi2c2: lpi2c2grp { -+ fsl,pins = < -+ SC_P_GPT1_CLK_DMA_I2C2_SCL 0x04000020 -+ SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020 -+ >; -+ }; -+ -+ /* Apalis I2C3 (CAM) */ -+ pinctrl_lpi2c3: lpi2c3grp { -+ fsl,pins = < -+ SC_P_SIM0_PD_DMA_I2C3_SCL 0x04000020 -+ SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020 -+ >; -+ }; -+ -+ /* Apalis UART3 */ -+ pinctrl_lpuart0: lpuart0grp { -+ fsl,pins = < -+ SC_P_UART0_RX_DMA_UART0_RX 0x06000020 -+ SC_P_UART0_TX_DMA_UART0_TX 0x06000020 -+ >; -+ }; -+ -+ /* Apalis UART1 */ -+ pinctrl_lpuart1: lpuart1grp { -+ fsl,pins = < -+ SC_P_UART1_RX_DMA_UART1_RX 0x06000020 -+ SC_P_UART1_TX_DMA_UART1_TX 0x06000020 -+ SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 -+ SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 -+ >; -+ }; -+ -+ pinctrl_lpuart1ctrl: lpuart1ctrlgrp { -+ fsl,pins = < -+ /* Apalis UART1_DTR */ -+ SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021 -+ /* Apalis UART1_DSR */ -+ SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021 -+ /* Apalis UART1_DCD */ -+ SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021 -+ /* Apalis UART1_RI */ -+ SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021 -+ >; -+ }; -+ -+ /* Apalis UART4 */ -+ pinctrl_lpuart2: lpuart2grp { -+ fsl,pins = < -+ SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020 -+ SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 -+ >; -+ }; -+ -+ /* Apalis UART2 */ -+ pinctrl_lpuart3: lpuart3grp { -+ fsl,pins = < -+ SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020 -+ SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020 -+ SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020 -+ SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020 -+ >; -+ }; -+ -+ /* Apalis PWM3 */ -+ pinctrl_gpio_pwm0: gpiopwm0grp { -+ fsl,pins = < -+ SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 0x00000021 -+ >; -+ }; -+ -+ /* Apalis PWM4 */ -+ pinctrl_gpio_pwm1: gpiopwm1grp { -+ fsl,pins = < -+ SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 0x00000021 -+ >; -+ }; -+ -+ /* Apalis PWM1 */ -+ pinctrl_gpio_pwm2: gpiopwm2grp { -+ fsl,pins = < -+ SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 0x00000021 -+ >; -+ }; -+ -+ /* Apalis PWM2 */ -+ pinctrl_gpio_pwm3: gpiopwm3grp { -+ fsl,pins = < -+ SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 0x00000021 -+ >; -+ }; -+ -+ /* Apalis BKL1_PWM */ -+ pinctrl_gpio_pwm_bkl: gpiopwmbklgrp { -+ fsl,pins = < -+ SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 0x00000021 -+ >; -+ }; -+ -+ /* Apalis USBH_EN */ -+ pinctrl_gpio_usbh_en: gpiousbhen { -+ fsl,pins = < -+ SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x06000060 -+ >; -+ }; -+ -+ /* Apalis USBH_OC# */ -+ pinctrl_gpio_usbh_oc_n: gpiousbhocn { -+ fsl,pins = < -+ SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x06000060 -+ >; -+ }; -+ -+ /* Apalis USBO1_EN */ -+ pinctrl_gpio_usbo1_en: gpiousbo1en { -+ fsl,pins = < -+ SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000060 -+ >; -+ }; -+ -+ /* Apalis USBO1_OC# */ -+ pinctrl_gpio_usbo1_oc_n: gpiousbo1ocn { -+ fsl,pins = < -+ SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x06000060 -+ >; -+ }; -+ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 -+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 -+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 -+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 -+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 -+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 -+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 -+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 -+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 -+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 -+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 -+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 -+ >; -+ }; -+ -+ pinctrl_sata1_act: sata1actgrp { -+ fsl,pins = < -+ /* Apalis SATA1_ACT# */ -+ SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021 -+ >; -+ }; -+ -+ pinctrl_mmc1_cd: mmc1cdgrp { -+ fsl,pins = < -+ /* Apalis MMC1_CD# */ -+ SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc2: usdhc2grp { -+ fsl,pins = < -+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 -+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 -+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 -+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 -+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 -+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 -+ SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021 -+ SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021 -+ SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021 -+ SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021 -+ /* On-module PMIC use */ -+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 -+ >; -+ }; -+ -+ pinctrl_sd1_cd: sd1cdgrp { -+ fsl,pins = < -+ /* Apalis SD1_CD# */ -+ SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 -+ SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 -+ SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 -+ SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 -+ SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 -+ SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 -+ /* On-module PMIC use */ -+ SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 -+ >; -+ }; -+ }; -+}; -+ -+&fec1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_fec1>; -+ fsl,magic-packet; -+ phy-handle = <ðphy0>; -+ phy-mode = "rgmii"; -+ phy-reset-duration = <10>; -+ phy-reset-gpios = <&gpio1 11 1>; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@7 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+ }; -+}; -+ -+/* Apalis I2C2 (DDC) */ -+&i2c0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c0>; -+ clock-frequency = <100000>; -+ status = "okay"; -+}; -+ -+/* On-module I2C */ -+&i2c1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c1>; -+ status = "okay"; -+}; -+ -+/* Apalis I2C1 */ -+&i2c2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c2>; -+ status = "okay"; -+}; -+ -+/* Apalis I2C3 (CAM) */ -+&i2c3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpi2c3>; -+ status = "okay"; -+}; -+ -+/* Apalis UART3 */ -+&lpuart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart0>; -+ status = "okay"; -+}; -+ -+/* Apalis UART1 */ -+&lpuart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart1>; -+ status = "okay"; -+}; -+ -+/* Apalis UART4 */ -+&lpuart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart2>; -+ status = "okay"; -+}; -+ -+/* Apalis UART2 */ -+&lpuart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_lpuart3>; -+ status = "okay"; -+}; -+ -+/* eMMC */ -+&usdhc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc1>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+/* Apalis MMC1 */ -+&usdhc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; -+ bus-width = <8>; -+ cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ -+ status = "okay"; -+}; -+ -+/* Apalis SD1 */ -+&usdhc3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>; -+ bus-width = <4>; -+ cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */ -+ status = "okay"; -+}; -diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig -index 90223aaefc..c87f77fee6 100644 ---- a/arch/arm/mach-imx/imx8/Kconfig -+++ b/arch/arm/mach-imx/imx8/Kconfig -@@ -27,6 +27,11 @@ choice - prompt "i.MX8 board select" - optional - -+config TARGET_APALIS_IMX8QM -+ bool "Support Apalis iMX8QM module" -+ select BOARD_LATE_INIT -+ select IMX8QM -+ - config TARGET_COLIBRI_IMX8QXP - bool "Support Colibri iMX8QXP module" - select BOARD_LATE_INIT -@@ -46,6 +51,7 @@ endchoice - - source "board/freescale/imx8qm_mek/Kconfig" - source "board/freescale/imx8qxp_mek/Kconfig" -+source "board/toradex/apalis-imx8qm/Kconfig" - source "board/toradex/colibri-imx8qxp/Kconfig" - - endif -diff --git a/board/toradex/apalis-imx8qm/Kconfig b/board/toradex/apalis-imx8qm/Kconfig -new file mode 100644 -index 0000000000..38b64cd6e6 ---- /dev/null -+++ b/board/toradex/apalis-imx8qm/Kconfig -@@ -0,0 +1,30 @@ -+if TARGET_APALIS_IMX8QM -+ -+config SYS_BOARD -+ default "apalis-imx8qm" -+ -+config SYS_VENDOR -+ default "toradex" -+ -+config SYS_CONFIG_NAME -+ default "apalis-imx8qm" -+ -+config TDX_CFG_BLOCK -+ default y -+ -+config TDX_HAVE_MMC -+ default y -+ -+config TDX_CFG_BLOCK_DEV -+ default "0" -+ -+config TDX_CFG_BLOCK_PART -+ default "1" -+ -+# Toradex config block in eMMC, at the end of 1st "boot sector" -+config TDX_CFG_BLOCK_OFFSET -+ default "-512" -+ -+source "board/toradex/common/Kconfig" -+ -+endif -diff --git a/board/toradex/apalis-imx8qm/MAINTAINERS b/board/toradex/apalis-imx8qm/MAINTAINERS -new file mode 100644 -index 0000000000..f2a61236b8 ---- /dev/null -+++ b/board/toradex/apalis-imx8qm/MAINTAINERS -@@ -0,0 +1,9 @@ -+Apalis iMX8QM -+M: Marcel Ziswiler -+W: http://developer.toradex.com/software/linux/linux-software -+S: Maintained -+F: arch/arm/dts/fsl-imx8qm-apalis.dts -+F: arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi -+F: board/toradex/apalis-imx8qm/ -+F: configs/apalis-imx8qm_defconfig -+F: include/configs/apalis-imx8qm.h -diff --git a/board/toradex/apalis-imx8qm/Makefile b/board/toradex/apalis-imx8qm/Makefile -new file mode 100644 -index 0000000000..d606a866b4 ---- /dev/null -+++ b/board/toradex/apalis-imx8qm/Makefile -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+# Copyright 2019 Toradex -+# -+ -+obj-y += apalis-imx8qm.o -diff --git a/board/toradex/apalis-imx8qm/README b/board/toradex/apalis-imx8qm/README -new file mode 100644 -index 0000000000..e6e3dcb367 ---- /dev/null -+++ b/board/toradex/apalis-imx8qm/README -@@ -0,0 +1,66 @@ -+U-Boot for the Toradex Apalis iMX8QM V1.0B Module -+ -+Quick Start -+=========== -+ -+- Build the ARM trusted firmware binary -+- Get scfw_tcm.bin and ahab-container.img -+- Build U-Boot -+- Load U-Boot binary using uuu -+- Flash U-Boot binary into the eMMC -+- Boot -+ -+Get and Build the ARM Trusted Firmware -+====================================== -+ -+$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf -+$ cd imx-atf/ -+$ make PLAT=imx8qm bl31 -+ -+Get scfw_tcm.bin and ahab-container.img -+======================================= -+ -+$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true -+$ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin -+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin -+$ chmod +x firmware-imx-8.0.bin -+$ ./firmware-imx-8.0.bin -+ -+Copy the following binaries to the U-Boot folder: -+ -+$ cp imx-atf/build/imx8qm/release/bl31.bin . -+$ cp u-boot/u-boot.bin . -+ -+Copy the following firmware to the U-Boot folder: -+ -+$ cp firmware-imx-8.0/firmware/seco/ahab-container.img . -+ -+Build U-Boot -+============ -+ -+$ make apalis-imx8qm_defconfig -+$ make u-boot-dtb.imx -+ -+Load the U-Boot Binary Using UUU -+================================ -+ -+Get the latest version of the universal update utility (uuu) aka mfgtools 3.0: -+ -+https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases -+ -+Put the module into USB recovery aka serial downloader mode, connect USB device -+to your host and execute uuu: -+ -+sudo ./uuu u-boot/u-boot-dtb.imx -+ -+Flash the U-Boot Binary into the eMMC -+===================================== -+ -+Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition: -+ -+load mmc 1:1 $loadaddr u-boot-dtb.imx -+setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 -+mmc dev 0 1 -+mmc write ${loadaddr} 0x0 ${blkcnt} -+ -+Boot -diff --git a/board/toradex/apalis-imx8qm/apalis-imx8qm.c b/board/toradex/apalis-imx8qm/apalis-imx8qm.c -new file mode 100644 -index 0000000000..f516e546a8 ---- /dev/null -+++ b/board/toradex/apalis-imx8qm/apalis-imx8qm.c -@@ -0,0 +1,149 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2019 Toradex -+ */ -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../common/tdx-cfg-block.h" -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ -+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ -+ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ -+ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) -+ -+static iomux_cfg_t uart1_pads[] = { -+ SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -+ SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -+}; -+ -+static void setup_iomux_uart(void) -+{ -+ imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -+} -+ -+int board_early_init_f(void) -+{ -+ sc_pm_clock_rate_t rate; -+ sc_err_t err = 0; -+ -+ /* Power up UART1 */ -+ err = sc_pm_set_resource_power_mode(-1, SC_R_UART_1, SC_PM_PW_MODE_ON); -+ if (err != SC_ERR_NONE) -+ return 0; -+ -+ /* Set UART3 clock root to 80 MHz */ -+ rate = 80000000; -+ err = sc_pm_set_clock_rate(-1, SC_R_UART_1, SC_PM_CLK_PER, &rate); -+ if (err != SC_ERR_NONE) -+ return 0; -+ -+ /* Enable UART1 clock root */ -+ err = sc_pm_clock_enable(-1, SC_R_UART_1, SC_PM_CLK_PER, true, false); -+ if (err != SC_ERR_NONE) -+ return 0; -+ -+ setup_iomux_uart(); -+ -+ return 0; -+} -+ -+#if IS_ENABLED(CONFIG_DM_GPIO) -+static void board_gpio_init(void) -+{ -+ /* TODO */ -+} -+#else -+static inline void board_gpio_init(void) {} -+#endif -+ -+#if IS_ENABLED(CONFIG_FEC_MXC) -+#include -+ -+int board_phy_config(struct phy_device *phydev) -+{ -+ if (phydev->drv->config) -+ phydev->drv->config(phydev); -+ -+ return 0; -+} -+#endif -+ -+void build_info(void) -+{ -+ u32 sc_build = 0, sc_commit = 0; -+ -+ /* Get SCFW build and commit id */ -+ sc_misc_build_info(-1, &sc_build, &sc_commit); -+ if (!sc_build) { -+ printf("SCFW does not support build info\n"); -+ sc_commit = 0; /* Display 0 if build info not supported */ -+ } -+ printf("Build: SCFW %x\n", sc_commit); -+} -+ -+int checkboard(void) -+{ -+ puts("Model: Toradex Apalis iMX8\n"); -+ -+ build_info(); -+ print_bootinfo(); -+ -+ return 0; -+} -+ -+int board_init(void) -+{ -+ board_gpio_init(); -+ -+ return 0; -+} -+ -+void detail_board_ddr_info(void) -+{ -+ puts("\nDDR "); -+} -+ -+/* -+ * Board specific reset that is system reset. -+ */ -+void reset_cpu(ulong addr) -+{ -+ /* TODO */ -+} -+ -+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -+int ft_board_setup(void *blob, bd_t *bd) -+{ -+ return ft_common_board_setup(blob, bd); -+} -+#endif -+ -+int board_mmc_get_env_dev(int devno) -+{ -+ return devno; -+} -+ -+int board_late_init(void) -+{ -+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -+/* TODO move to common */ -+ env_set("board_name", "Apalis iMX8QM"); -+ env_set("board_rev", "v1.0"); -+#endif -+ -+ return 0; -+} -diff --git a/board/toradex/apalis-imx8qm/imximage.cfg b/board/toradex/apalis-imx8qm/imximage.cfg -new file mode 100644 -index 0000000000..71981f8c55 ---- /dev/null -+++ b/board/toradex/apalis-imx8qm/imximage.cfg -@@ -0,0 +1,24 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2019 Toradex -+ * -+ * Refer doc/README.imx8image for more details about how-to configure -+ * and create imx8image boot image -+ */ -+ -+#define __ASSEMBLY__ -+ -+/* Boot from SD, sector size 0x400 */ -+BOOT_FROM EMMC_FASTBOOT 0x400 -+/* SoC type IMX8QM */ -+SOC_TYPE IMX8QM -+/* Append seco container image */ -+APPEND mx8qm-ahab-container.img -+/* Create the 2nd container */ -+CONTAINER -+/* Add scfw image with exec attribute */ -+IMAGE SCU mx8qm-apalis-scfw-tcm.bin -+/* Add ATF image with exec attribute */ -+IMAGE A35 bl31.bin 0x80000000 -+/* Add U-Boot image with load attribute */ -+DATA A35 u-boot-dtb.bin 0x80020000 -diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig -new file mode 100644 -index 0000000000..ae62b2d923 ---- /dev/null -+++ b/configs/apalis-imx8qm_defconfig -@@ -0,0 +1,56 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_IMX8=y -+CONFIG_SYS_TEXT_BASE=0x80020000 -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_TARGET_APALIS_IMX8QM=y -+CONFIG_NR_DRAM_BANKS=3 -+CONFIG_DISTRO_DEFAULTS=y -+CONFIG_FIT=y -+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8qm/imximage.cfg" -+CONFIG_LOG=y -+CONFIG_VERSION_VARIABLE=y -+# CONFIG_DISPLAY_BOARDINFO is not set -+CONFIG_BOARD_EARLY_INIT_F=y -+CONFIG_CMD_CPU=y -+# CONFIG_CMD_IMPORTENV is not set -+CONFIG_CMD_MEMTEST=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_FUSE=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_UUID=y -+CONFIG_CMD_EXT4_WRITE=y -+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_CLK_IMX8=y -+CONFIG_CPU=y -+CONFIG_DM_GPIO=y -+CONFIG_MXC_GPIO=y -+CONFIG_DM_I2C=y -+CONFIG_SYS_I2C_IMX_LPI2C=y -+CONFIG_MISC=y -+CONFIG_DM_MMC=y -+CONFIG_PHYLIB=y -+CONFIG_PHY_ADDR_ENABLE=y -+CONFIG_PHY_MICREL=y -+CONFIG_PHY_MICREL_KSZ90X1=y -+CONFIG_DM_ETH=y -+CONFIG_FEC_MXC_SHARE_MDIO=y -+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 -+CONFIG_FEC_MXC=y -+CONFIG_MII=y -+CONFIG_PINCTRL=y -+CONFIG_PINCTRL_IMX8=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_IMX8_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_DM_SERIAL=y -+CONFIG_FSL_LPUART=y -+CONFIG_DM_THERMAL=y -+CONFIG_IMX_SCU_THERMAL=y -+# CONFIG_EFI_LOADER is not set -diff --git a/include/configs/apalis-imx8qm.h b/include/configs/apalis-imx8qm.h -new file mode 100644 -index 0000000000..f5cba2b1c1 ---- /dev/null -+++ b/include/configs/apalis-imx8qm.h -@@ -0,0 +1,177 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2019 Toradex -+ */ -+ -+#ifndef __APALIS_IMX8QM_H -+#define __APALIS_IMX8QM_H -+ -+#include -+#include -+ -+#define CONFIG_REMAKE_ELF -+ -+#define CONFIG_DISPLAY_BOARDINFO_LATE -+ -+#undef CONFIG_CMD_EXPORTENV -+#undef CONFIG_CMD_IMPORTENV -+#undef CONFIG_CMD_IMLS -+ -+#undef CONFIG_CMD_CRC32 -+#undef CONFIG_BOOTM_NETBSD -+ -+#define CONFIG_FSL_ESDHC -+#define CONFIG_FSL_USDHC -+#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -+#define USDHC1_BASE_ADDR 0x5B010000 -+#define USDHC2_BASE_ADDR 0x5B020000 -+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -+ -+#define CONFIG_ENV_OVERWRITE -+ -+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -+ -+/* Networking */ -+#define FEC_QUIRK_ENET_MAC -+ -+#define CONFIG_IP_DEFRAG -+#define CONFIG_TFTP_BLOCKSIZE SZ_4K -+#define CONFIG_TFTP_TSIZE -+ -+#define CONFIG_IPADDR 192.168.10.2 -+#define CONFIG_NETMASK 255.255.255.0 -+#define CONFIG_SERVERIP 192.168.10.1 -+ -+#define MEM_LAYOUT_ENV_SETTINGS \ -+ "fdt_addr_r=0x84000000\0" \ -+ "kernel_addr_r=0x82000000\0" \ -+ "ramdisk_addr_r=0x84100000\0" -+ -+#define BOOT_TARGET_DEVICES(func) \ -+ func(MMC, mmc, 0) \ -+ func(MMC, mmc, 1) \ -+ func(MMC, mmc, 2) \ -+ func(DHCP, dhcp, na) -+#include -+#undef BOOTENV_RUN_NET_USB_START -+#define BOOTENV_RUN_NET_USB_START "" -+ -+/* Initial environment variables */ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ BOOTENV \ -+ MEM_LAYOUT_ENV_SETTINGS \ -+ "boot_fdt=try\0" \ -+ "bootscript=echo Running bootscript from mmc ...; source\0" \ -+ "console=ttyLP1 earlycon\0" \ -+ "fdt_addr=0x83000000\0" \ -+ "fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \ -+ "fdt_high=0xffffffffffffffff\0" \ -+ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ -+ "image=Image\0" \ -+ "initrd_addr=0x83800000\0" \ -+ "initrd_high=0xffffffffffffffff\0" \ -+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ -+ "${script};\0" \ -+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ -+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ -+ "mmcargs=setenv bootargs console=${console},${baudrate} " \ -+ "root=PARTUUID=${uuid} rootwait " \ -+ "mmcautodetect=yes\0" \ -+ "mmcboot=echo Booting from mmc ...; " \ -+ "run finduuid; run mmcargs; " \ -+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ -+ "if run loadfdt; then " \ -+ "booti ${loadaddr} - ${fdt_addr}; " \ -+ "else " \ -+ "echo WARN: Cannot load the DT; " \ -+ "fi; " \ -+ "else " \ -+ "echo wait for boot; " \ -+ "fi;\0" \ -+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ -+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ -+ "netargs=setenv bootargs console=${console},${baudrate} " \ -+ "root=/dev/nfs " \ -+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ -+ "netboot=echo Booting from net ...; " \ -+ "run netargs; " \ -+ "if test ${ip_dyn} = yes; then " \ -+ "setenv get_cmd dhcp; " \ -+ "else " \ -+ "setenv get_cmd tftp; " \ -+ "fi; " \ -+ "${get_cmd} ${loadaddr} ${image}; " \ -+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ -+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ -+ "booti ${loadaddr} - ${fdt_addr}; " \ -+ "else " \ -+ "echo WARN: Cannot load the DT; " \ -+ "fi; " \ -+ "else " \ -+ "booti; " \ -+ "fi;\0" \ -+ "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ -+ "apalis-imx8qm/${fdt_file}; booti ${loadaddr} - " \ -+ "${fdt_addr}\0" \ -+ "panel=NULL\0" \ -+ "script=boot.scr\0" -+ -+#undef CONFIG_BOOTCOMMAND -+#define CONFIG_BOOTCOMMAND \ -+ "mmc dev ${mmcdev}; if mmc rescan; then " \ -+ "if run loadbootscript; then " \ -+ "run bootscript; " \ -+ "else " \ -+ "if run loadimage; then " \ -+ "run mmcboot; " \ -+ "else run netboot; " \ -+ "fi; " \ -+ "fi; " \ -+ "else booti ${loadaddr} - ${fdt_addr}; fi" -+ -+/* Link Definitions */ -+#define CONFIG_LOADADDR 0x80280000 -+ -+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -+ -+#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 -+ -+#define CONFIG_SYS_MEMTEST_START 0x88000000 -+#define CONFIG_SYS_MEMTEST_END 0x89000000 -+ -+/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -+#define CONFIG_ENV_SIZE SZ_8K -+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ -+ CONFIG_TDX_CFG_BLOCK_OFFSET) -+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ -+#define CONFIG_SYS_MMC_ENV_PART 1 -+ -+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -+ -+/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ -+#define CONFIG_SYS_FSL_USDHC_NUM 3 -+ -+/* Size of malloc() pool */ -+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) -+ -+#define CONFIG_SYS_SDRAM_BASE 0x80000000 -+#define PHYS_SDRAM_1 0x80000000 -+#define PHYS_SDRAM_2 0x880000000 -+#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ -+#define PHYS_SDRAM_2_SIZE SZ_2G /* 2 GB */ -+ -+/* Serial */ -+#define CONFIG_BAUDRATE 115200 -+ -+/* Monitor Command Prompt */ -+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -+#define CONFIG_SYS_CBSIZE SZ_2K -+#define CONFIG_SYS_MAXARGS 64 -+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ -+ sizeof(CONFIG_SYS_PROMPT) + 16) -+ -+/* Generic Timer Definitions */ -+#define COUNTER_FREQUENCY 8000000 /* 8MHz */ -+ -+#endif /* __APALIS_IMX8QM_H */ --- -2.14.5 - diff --git a/recipes-bsp/u-boot-mainline/files/video_mxsfb_fix_mxsfb_fbdev_binding_issues.mbox b/recipes-bsp/u-boot-mainline/files/video_mxsfb_fix_mxsfb_fbdev_binding_issues.mbox new file mode 100644 index 0000000..f32653c --- /dev/null +++ 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albert.u.boot@aribaud.net, + sbabic@denx.de, + festevam@gmail.com, + uboot-imx@nxp.com, + peng.fan@nxp.com, + jagan@amarulasolutions.com, + marcel.ziswiler@toradex.com, + stefan@agner.ch, + max.krummenacher@toradex.com +Subject: [PATCH 1/6] video: mxsfb: fix mxsfb fbdev binding issues +Message-Id: <20190619084710.19074-2-igor.opaniuk@gmail.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20190619084710.19074-1-igor.opaniuk@gmail.com> +References: <20190619084710.19074-1-igor.opaniuk@gmail.com> +X-MDID: 1560934034-1SIYzjPIaBSY +Return-Path: igor.opaniuk@gmail.com +X-MS-Exchange-Organization-ExpirationStartTime: 19 Jun 2019 08:47:14.3918 + (UTC) +X-MS-Exchange-Organization-ExpirationStartTimeReason: OriginalSubmit +X-MS-Exchange-Organization-ExpirationInterval: 1:00:00:00.0000000 +X-MS-Exchange-Organization-ExpirationIntervalReason: OriginalSubmit +X-MS-Exchange-Organization-Network-Message-Id: + 2a4bed9d-c604-4a64-1f8c-08d6f492ba16 +X-EOPAttributedMessage: 0 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2019 11:47:05 +0300 +X-Evolution-Source: 1468251588.7413.5@roman-pc.toradex.int +Content-Transfer-Encoding: 8bit + +From: Igor Opaniuk + +Add support for display and bits-per-pixel properties. + +Signed-off-by: Igor Opaniuk +--- + drivers/video/mxsfb.c | 74 ++++++++++++++++++++++++++++++++++++------- + 1 file changed, 62 insertions(+), 12 deletions(-) + +diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c +index f02ba20138..6c9a7c05e8 100644 +--- a/drivers/video/mxsfb.c ++++ b/drivers/video/mxsfb.c +@@ -271,6 +271,42 @@ dealloc_fb: + } + #else /* ifndef CONFIG_DM_VIDEO */ + ++static int mxs_of_get_timings(struct udevice *dev, ++ struct display_timing *timings, ++ u32 *bpp) ++{ ++ int ret = 0; ++ u32 display_phandle; ++ ofnode display_node; ++ ++ ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle); ++ if (ret) { ++ dev_err(dev, "required display property isn't provided\n"); ++ return -EINVAL; ++ } ++ ++ display_node = ofnode_get_by_phandle(display_phandle); ++ if (!ofnode_valid(display_node)) { ++ dev_err(dev, "failed to find display subnode\n"); ++ return -EINVAL; ++ } ++ ++ ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp); ++ if (ret) { ++ dev_err(dev, ++ "required bits-per-pixel property isn't provided\n"); ++ return -EINVAL; ++ } ++ ++ ret = ofnode_decode_display_timing(display_node, 0, timings); ++ if (ret) { ++ dev_err(dev, "failed to get any display timings\n"); ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ + static int mxs_video_probe(struct udevice *dev) + { + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); +@@ -278,18 +314,16 @@ static int mxs_video_probe(struct udevice *dev) + + struct ctfb_res_modes mode; + struct display_timing timings; +- int bpp = -1; ++ u32 bpp = 0; + u32 fb_start, fb_end; + int ret; + + debug("%s() plat: base 0x%lx, size 0x%x\n", + __func__, plat->base, plat->size); + +- ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings); +- if (ret) { +- dev_err(dev, "failed to get any display timings\n"); +- return -EINVAL; +- } ++ ret = mxs_of_get_timings(dev, &timings, &bpp); ++ if (ret) ++ return ret; + + mode.xres = timings.hactive.typ; + mode.yres = timings.vactive.typ; +@@ -301,13 +335,12 @@ static int mxs_video_probe(struct udevice *dev) + mode.vsync_len = timings.vsync_len.typ; + mode.pixclock = HZ2PS(timings.pixelclock.typ); + +- bpp = BITS_PP; +- + ret = mxs_probe_common(&mode, bpp, plat->base); + if (ret) + return ret; + + switch (bpp) { ++ case 32: + case 24: + case 18: + uc_priv->bpix = VIDEO_BPP32; +@@ -341,15 +374,32 @@ static int mxs_video_bind(struct udevice *dev) + { + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct display_timing timings; ++ u32 bpp = 0; ++ u32 bytes_pp = 0; + int ret; + +- ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings); +- if (ret) { +- dev_err(dev, "failed to get any display timings\n"); ++ ret = mxs_of_get_timings(dev, &timings, &bpp); ++ if (ret) ++ return ret; ++ ++ switch (bpp) { ++ case 32: ++ case 24: ++ case 18: ++ bytes_pp = 4; ++ break; ++ case 16: ++ bytes_pp = 2; ++ break; ++ case 8: ++ bytes_pp = 1; ++ break; ++ default: ++ dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp); + return -EINVAL; + } + +- plat->size = timings.hactive.typ * timings.vactive.typ * BYTES_PP; ++ plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp; + + return 0; + } +-- +2.17.1 + + +From igor.opaniuk@gmail.com Wed Jun 19 08:47:17 2019 +Received: from AM0PR05MB6466.eurprd05.prod.outlook.com + (2603:10a6:20b:3a::32) by AM6PR0502MB3688.eurprd05.prod.outlook.com with + HTTPS via AM6PR0202CA0055.EURPRD02.PROD.OUTLOOK.COM; Wed, 19 Jun 2019 + 08:47:17 +0000 +Received: from HE1PR0501CA0006.eurprd05.prod.outlook.com + (2603:10a6:3:1a::16) by AM0PR05MB6466.eurprd05.prod.outlook.com + (2603:10a6:208:13e::11) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1987.11; Wed, 19 Jun + 2019 08:47:16 +0000 +Received: from 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Currently there is support only for +old style lcdif node definitions. + +[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/display/mxsfb.txt + +Signed-off-by: Igor Opaniuk +--- + arch/arm/dts/imx7-colibri.dtsi | 47 +++++++++++++++++++--------------- + 1 file changed, 26 insertions(+), 21 deletions(-) + +diff --git a/arch/arm/dts/imx7-colibri.dtsi b/arch/arm/dts/imx7-colibri.dtsi +index 81717c233d..308e0b2a63 100644 +--- a/arch/arm/dts/imx7-colibri.dtsi ++++ b/arch/arm/dts/imx7-colibri.dtsi +@@ -113,29 +113,34 @@ + }; + + &lcdif { +- u-boot,dm-pre-reloc; + status = "okay"; ++ display = <&display0>; ++ u-boot,dm-pre-reloc; + +- display-timings { +- native-mode = <&timing_vga>; +- +- /* Standard VGA timing */ +- timing_vga: 640x480 { +- u-boot,dm-pre-reloc; +- clock-frequency = <25175000>; +- hactive = <640>; +- vactive = <480>; +- hback-porch = <48>; +- hfront-porch = <16>; +- vback-porch = <33>; +- vfront-porch = <10>; +- hsync-len = <96>; +- vsync-len = <2>; +- +- de-active = <1>; +- hsync-active = <0>; +- vsync-active = <0>; +- pixelclk-active = <0>; ++ display0: display0 { ++ bits-per-pixel = <18>; ++ bus-width = <24>; ++ status = "okay"; ++ ++ display-timings { ++ native-mode = <&timing_vga>; ++ timing_vga: 640x480 { ++ u-boot,dm-pre-reloc; ++ clock-frequency = <25175000>; ++ hactive = <640>; ++ vactive = <480>; ++ hback-porch = <48>; ++ hfront-porch = <16>; ++ vback-porch = <33>; ++ vfront-porch = <10>; ++ hsync-len = <96>; ++ vsync-len = <2>; ++ ++ de-active = <1>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ pixelclk-active = <0>; ++ }; + }; + }; + }; +-- +2.17.1 + + +From igor.opaniuk@gmail.com Wed Jun 19 08:47:17 2019 +Received: from DBBPR05MB6476.eurprd05.prod.outlook.com + (2603:10a6:203:69::11) by AM6PR0502MB3688.eurprd05.prod.outlook.com with + HTTPS via AM5PR0202CA0001.EURPRD02.PROD.OUTLOOK.COM; Wed, 19 Jun 2019 + 08:47:17 +0000 +Received: from AM3PR05CA0128.eurprd05.prod.outlook.com + (2603:10a6:207:2::30) by DBBPR05MB6476.eurprd05.prod.outlook.com + (2603:10a6:10:cc::12) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1987.11; 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Wed, 19 Jun 2019 01:47:14 + -0700 (PDT) +From: Igor Opaniuk +To: u-boot@lists.denx.de +Cc: agust@denx.de, + albert.u.boot@aribaud.net, + sbabic@denx.de, + festevam@gmail.com, + uboot-imx@nxp.com, + peng.fan@nxp.com, + jagan@amarulasolutions.com, + marcel.ziswiler@toradex.com, + stefan@agner.ch, + max.krummenacher@toradex.com +Subject: [PATCH 3/6] configs: colibri_imx7: enable DM_VIDEO +Message-Id: <20190619084710.19074-4-igor.opaniuk@gmail.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20190619084710.19074-1-igor.opaniuk@gmail.com> +References: <20190619084710.19074-1-igor.opaniuk@gmail.com> +X-MDID: 1560934036-48RNLTRy7JUa +Return-Path: igor.opaniuk@gmail.com +X-MS-Exchange-Organization-ExpirationStartTime: 19 Jun 2019 08:47:16.7174 + (UTC) +X-MS-Exchange-Organization-ExpirationStartTimeReason: OriginalSubmit +X-MS-Exchange-Organization-ExpirationInterval: 1:00:00:00.0000000 +X-MS-Exchange-Organization-ExpirationIntervalReason: OriginalSubmit +X-MS-Exchange-Organization-Network-Message-Id: + 9c5ecfd9-cb9f-43d0-f9e7-08d6f492bb78 +X-EOPAttributedMessage: 0 +X-EOPTenantAttributedMessage: d9995866-0d9b-4251-8315-093f062abab4:0 +X-MS-Exchange-Organization-MessageDirectionality: Incoming +X-Forefront-Antispam-Report: + CIP:185.132.181.6;IPV:CAL;SCL:-1;CTRY:NL;EFV:NLI;SFV:SKN;SFS:;DIR:INB;SFP:;SCL:-1;SRVR:DBBPR05MB6476;H:dispatch1-eu1.ppe-hosted.com;FPR:;SPF:None;LANG:en; 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Wed, 19 Jun 2019 01:47:16 + -0700 (PDT) +From: Igor Opaniuk +To: u-boot@lists.denx.de +Cc: agust@denx.de, + albert.u.boot@aribaud.net, + sbabic@denx.de, + festevam@gmail.com, + uboot-imx@nxp.com, + peng.fan@nxp.com, + jagan@amarulasolutions.com, + marcel.ziswiler@toradex.com, + stefan@agner.ch, + max.krummenacher@toradex.com +Subject: [PATCH 4/6] colibri-imx6ull: support building with DM_VIDEO=y +Message-Id: <20190619084710.19074-5-igor.opaniuk@gmail.com> +X-Mailer: git-send-email 2.17.1 +In-Reply-To: <20190619084710.19074-1-igor.opaniuk@gmail.com> +References: <20190619084710.19074-1-igor.opaniuk@gmail.com> +X-MDID: 1560934038-IPsMFvB-gl6M +Return-Path: igor.opaniuk@gmail.com +X-MS-Exchange-Organization-ExpirationStartTime: 19 Jun 2019 08:47:18.8261 + (UTC) +X-MS-Exchange-Organization-ExpirationStartTimeReason: OriginalSubmit +X-MS-Exchange-Organization-ExpirationInterval: 1:00:00:00.0000000 +X-MS-Exchange-Organization-ExpirationIntervalReason: OriginalSubmit +X-MS-Exchange-Organization-Network-Message-Id: + cad5879a-4679-4588-bdd5-08d6f492bcba +X-EOPAttributedMessage: 0 +X-EOPTenantAttributedMessage: d9995866-0d9b-4251-8315-093f062abab4:0 +X-MS-Exchange-Organization-MessageDirectionality: Incoming +X-Forefront-Antispam-Report: + CIP:91.209.104.157;IPV:NLI;CTRY:GB;EFV:NLI;SFV:NSPM;SFS:(2980300002)(199004)(189003)(34206002)(61266001)(336012)(57986006)(4326008)(450100002)(426003)(6666004)(55446002)(47776003)(1076003)(356004)(83322999)(16003)(82202003)(95326003)(59536001)(5660300002)(76482006)(2160300002)(7596002)(7636002)(305945005)(86362001)(126002)(51416003)(16586007)(60626007)(956004)(2616005)(26005)(476003)(486006)(48376002)(2351001)(44832011)(36756003)(1096003)(11346002)(246002)(76506005)(73972006)(50226002)(446003)(73392003)(8676002)(50466002)(2361001)(76176011)(60616004);DIR:INB;SFP:;SCL:1;SRVR:HE1PR0502MB3692;H:dispatch1-eu1.ppe-hosted.com;FPR:;SPF:SoftFail;LANG:en;PTR:dispatch1-eu1.ppe-hosted.com;A:1;MX:1; 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This fixes linking issues when building with DM_VIDEO enabled mxsfb +driver. +2. Provide proper defines for both VIDEO=y and DM_VIDEO=y. + +Signed-off-by: Igor Opaniuk +--- + arch/arm/mach-imx/mx6/soc.c | 2 +- + include/configs/colibri-imx6ull.h | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c +index e80f1d484b..86a9eeba0c 100644 +--- a/arch/arm/mach-imx/mx6/soc.c ++++ b/arch/arm/mach-imx/mx6/soc.c +@@ -549,7 +549,7 @@ const struct boot_mode soc_boot_modes[] = { + void reset_misc(void) + { + #ifndef CONFIG_SPL_BUILD +-#ifdef CONFIG_VIDEO_MXS ++#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO) + lcdif_power_down(); + #endif + #endif +diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h +index 21d9a3da01..1c6acf0081 100644 +--- a/include/configs/colibri-imx6ull.h ++++ b/include/configs/colibri-imx6ull.h +@@ -170,7 +170,7 @@ + #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M + #define DFU_DEFAULT_POLL_TIMEOUT 300 + +-#ifdef CONFIG_VIDEO ++#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) + #define CONFIG_VIDEO_MXS + #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR + #define CONFIG_VIDEO_LOGO +-- +2.17.1 + + +From igor.opaniuk@gmail.com Wed Jun 19 08:47:20 2019 +Received: from DBBPR05MB6476.eurprd05.prod.outlook.com + (2603:10a6:209:85::48) by AM6PR0502MB3688.eurprd05.prod.outlook.com with + HTTPS via AM6P193CA0143.EURP193.PROD.OUTLOOK.COM; Wed, 19 Jun 2019 08:47:20 + +0000 +Received: from HE1PR05CA0355.eurprd05.prod.outlook.com (2603:10a6:7:94::14) + by DBBPR05MB6476.eurprd05.prod.outlook.com (2603:10a6:10:cc::12) with + Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1987.11; Wed, 19 Jun + 2019 08:47:19 +0000 +Received: from DB5EUR01FT010.eop-EUR01.prod.protection.outlook.com + (2a01:111:f400:7e02::201) by HE1PR05CA0355.outlook.office365.com + (2603:10a6:7:94::14) with Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1965.12 via 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2019 11:47:09 +0300 +X-Evolution-Source: 1468251588.7413.5@roman-pc.toradex.int +Content-Transfer-Encoding: 8bit + +From: Igor Opaniuk + +Provide proper display timings for lcdif node, used by mxsfb DM_VIDEO +enabled framebuffer driver. + +Signed-off-by: Igor Opaniuk +--- + arch/arm/dts/imx6ull-colibri.dts | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts +index 6c847ab792..262205ac5e 100644 +--- a/arch/arm/dts/imx6ull-colibri.dts ++++ b/arch/arm/dts/imx6ull-colibri.dts +@@ -12,8 +12,10 @@ + compatible = "toradex,colibri-imx6ull", "fsl,imx6ull"; + + aliases { ++ u-boot,dm-pre-reloc; + mmc0 = &usdhc1; + usb0 = &usbotg1; /* required for ums */ ++ display0 = &lcdif; + }; + + chosen { +@@ -156,6 +158,36 @@ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; ++ status = "okay"; ++ display = <&display0>; ++ u-boot,dm-pre-reloc; ++ ++ display0: display0 { ++ bits-per-pixel = <18>; ++ bus-width = <24>; ++ status = "okay"; ++ ++ display-timings { ++ native-mode = <&timing_vga>; ++ timing_vga: 640x480 { ++ u-boot,dm-pre-reloc; ++ clock-frequency = <25175000>; ++ hactive = <640>; ++ vactive = <480>; ++ hback-porch = <48>; ++ hfront-porch = <16>; ++ vback-porch = <33>; ++ vfront-porch = <10>; ++ hsync-len = <96>; ++ vsync-len = <2>; ++ ++ de-active = <1>; ++ hsync-active = <0>; ++ vsync-active = <0>; ++ pixelclk-active = <0>; ++ }; ++ }; ++ }; + }; + + /* PWM */ +-- +2.17.1 + + +From igor.opaniuk@gmail.com Wed Jun 19 08:47:24 2019 +Received: from VI1PR0502MB3694.eurprd05.prod.outlook.com + (2603:10a6:209:3e::36) by AM6PR0502MB3688.eurprd05.prod.outlook.com with + HTTPS via AM6P193CA0023.EURP193.PROD.OUTLOOK.COM; Wed, 19 Jun 2019 08:47:24 + +0000 +Received: from DB6PR05CA0021.eurprd05.prod.outlook.com (2603:10a6:6:14::34) + by VI1PR0502MB3694.eurprd05.prod.outlook.com (2603:10a6:803:10::22) with + Microsoft SMTP Server (version=TLS1_2, + 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1.0 +Date: Wed, 19 Jun 2019 11:47:10 +0300 +X-Evolution-Source: 1468251588.7413.5@roman-pc.toradex.int +Content-Transfer-Encoding: 8bit + +From: Igor Opaniuk + +Use CONFIG_DM_VIDEO=y by default for Colibri iMX6ULL. + +Signed-off-by: Igor Opaniuk +--- + configs/colibri-imx6ull_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig +index 5c89439f7b..ac5c519346 100644 +--- a/configs/colibri-imx6ull_defconfig ++++ b/configs/colibri-imx6ull_defconfig +@@ -80,6 +80,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 + CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 + CONFIG_CI_UDC=y + CONFIG_USB_GADGET_DOWNLOAD=y +-CONFIG_VIDEO=y ++CONFIG_DM_VIDEO=y + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_FDT_FIXUP_PARTITIONS=y +-- +2.17.1 + + diff --git a/recipes-bsp/u-boot-mainline/u-boot-common.inc b/recipes-bsp/u-boot-mainline/u-boot-common.inc index f6c4dad..0d56392 100644 --- a/recipes-bsp/u-boot-mainline/u-boot-common.inc +++ b/recipes-bsp/u-boot-mainline/u-boot-common.inc @@ -8,28 +8,41 @@ PE = "1" # We use the revision in order to avoid having to fetch it from the # repo during parse -SRCREV = "b4ee6daad7a2604ca9466b2ba48de86cc27d381f" +SRCREV = "77f6e2dd0551d8a825bab391a1bd6b838874bcd4" SRC_URI = "git://git.denx.de/u-boot.git" +# patches in flight SRC_URI += " \ - file://0001-imx-Use-a-convenient-default-value-for-SYS_MALLOC_F_.patch \ - file://0003-usb-limit-USB_MAX_XFER_BLK-to-256.patch \ - file://0004-apalis_imx6-add-device-tree-to-makefile.patch \ - file://0005-colibri-imx6ull-fix-usb-host-mode.patch \ - file://0006-net-fec_mxc-not-access-reserved-register-on-i.MX8.patch \ - file://0007-imx-fix-building-for-i.mx8-without-spl.patch \ - file://0008-board-toradex-add-colibri-imx8qxp-2gb-wb-it-v1.0b-mo.patch \ - file://0009-board-toradex-drop-support.arm-maintainer-email.patch \ - file://0010-misc-imx8-add-sc_misc_get_temp.patch \ - file://0011-thermal-add-i.MX8-thermal-driver.patch \ - file://0012-imx8-cpu-get-temperature-when-print-cpu-desc.patch \ - file://0013-imx-imx8dx-qxp-enable-thermal.patch \ - file://0014-arm-dts-imx8qm-add-lpuart1-lpuart2-lpuart3-lpuart4.patch \ - file://0015-arm-dts-imx8qm-add-support-for-i2c0-i2c1-i2c2-i2c3-a.patch \ - file://0016-clk-imx8qm-fix-usdhc2-clocks.patch \ - file://0017-imx8qm-fix-cpu-frequency-reporting.patch \ - file://0018-imx8-fuse-fix-fuse-driver.patch \ - file://0019-board-toradex-add-apalis-imx8qm-4gb-wb-it-v1.0b-modu.patch \ + file://0001-usb-limit-USB_MAX_XFER_BLK-to-256.patch \ + file://0002-misc-imx8-add-sc_misc_get_temp.patch \ + file://0003-thermal-add-i.MX8-thermal-driver.patch \ + file://0004-imx-imx8dx-qxp-enable-thermal.patch \ + file://0005-misc-imx8-add-sc_rm_set_master_sid.patch \ + file://0006-MLK-14938-8-imx8-Add-SMMU-setup-to-Soc-codes.patch \ + file://0007-apalis-imx8-enable-smmu-setup.patch \ + file://0008-MLK-16087-imx8qm-qxp-Disable-kernel-FDT-nodes-for-th.patch \ + file://0009-MLK-16560-1-imx8-Configure-sids-based-on-iommu-prope.patch \ + file://0010-apalis-imx8-enable-of_system_setup.patch \ + file://0011-MLK-17205-1-video-imx-hdp-Adding-support-for-HDP-fir.patch \ + file://0012-MLK-17205-2-video-imx-hdp-Adding-HDP-firmware-loadin.patch \ + file://0013-MLK-17205-3-video-imx-hdp-Adding-configs-for-HDP-fir.patch \ + file://0014-apalis-imx8-enable-hdp-firmware-loading.patch \ + \ + file://0001-imx8-cpu-fix-warning-for-cpu_imx_get_temp.patch \ + file://0002-video-fsl_dcu_fb-refactor-init-functions.patch \ + file://0003-video-fsl_dcu_fb-add-DM_VIDEO-support.patch \ + file://0004-ARM-dts-colibri_vf-Add-dcu0-node.patch \ + file://0005-colibri_vf-enable-DM_VIDEO.patch \ + file://0006-colibri-apalis-tegra-drop-DFU-support.patch \ + file://0007-colibri-apalis-imx-drop-DFU-support.patch \ + \ + file://0001-video-mxsfb-fix-mxsfb-fbdev-binding-issues.patch \ + file://0002-ARM-dts-colibri_imx7-Fix-lcdif-node-definition.patch \ + file://0003-configs-colibri_imx7-enable-DM_VIDEO.patch \ + file://0004-colibri-imx6ull-support-building-with-DM_VIDEO-y.patch \ + file://0005-ARM-dts-colibri-imx6ull-extend-lcdif-node.patch \ + file://0006-configs-colibri-imx6ull-switch-to-DM_VIDEO.patch \ " + S = "${WORKDIR}/git" -- cgit v1.2.3