path: root/recipes-bsp/imx-mkimage/files/0002-add-memory-timings-for-Apalis-iMX8.patch

From 5fbcedaf8ade13bddd9aca7baf7a7132a63096e7 Mon Sep 17 00:00:00 2001
From: Stefan Agner <stefan.agner@toradex.com>
Date: Thu, 18 Jan 2018 10:10:11 +0100
Subject: [PATCH 2/2] add memory timings for Apalis iMX8

This adds 800MHz and 1.6GHz memory timings for Apalis iMX8, copied
from the imx-scfw-porting-kit git tree.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---
 iMX8QM/imx8qm_apalis-imx8_dcd_1.6GHz.cfg | 469 +++++++++++++++++++++++++++
 iMX8QM/imx8qm_apalis-imx8_dcd_800MHz.cfg | 523 +++++++++++++++++++++++++++++++
 2 files changed, 992 insertions(+)
 create mode 100755 iMX8QM/imx8qm_apalis-imx8_dcd_1.6GHz.cfg
 create mode 100755 iMX8QM/imx8qm_apalis-imx8_dcd_800MHz.cfg

diff --git a/iMX8QM/imx8qm_apalis-imx8_dcd_1.6GHz.cfg b/iMX8QM/imx8qm_apalis-imx8_dcd_1.6GHz.cfg
new file mode 100755
index 0000000..6deb9e0
--- /dev/null
+++ b/iMX8QM/imx8qm_apalis-imx8_dcd_1.6GHz.cfg
@@ -0,0 +1,469 @@
+#define __ASSEMBLY__
+
+#include <ddrc_mem_map.h>
+#include <ddr_phy_mem_map.h>
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address   absolute address of the register
+ * value   value to be stored in the register
+ */
+
+#ifndef SCFW_DCD
+/* For 1600MHz DDR, DRC 800MHz operation */
+DATA 4	0xff148000	0x00000885	/* DRC0 bringup */
+DATA 4	0xff1a0000	0x00000885	/* DRC1 bringup */
+#else
+/* Set the DRC rate to 800MHz, the PHY PLL will double this for the DRAM rate. */
+uint32_t rate2 = SC_800MHZ;
+pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
+pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &rate2);
+#endif
+
+DATA 4	0x41a40208	0x1
+DATA 4	0x41d00208	0x1
+DATA 4	0x41a40040	0xb
+DATA 4	0x41d00040	0xb
+DATA 4	0x41a40204	0x1
+DATA 4	0x41d00204	0x1
+/* DRAM 0 controller configuration begin */
+DATA 4 	DDRC_MSTR_0   	0xC3080020	// Set LPDDR4, BL = 16 and active ranks
+DATA 4 	DDRC_DERATEEN_0   	0x00000213	// derate enable, derate values, byte to read MRR data
+DATA 4 	DDRC_DERATEINT_0   	0x0186A000	// derate MR4 interval read
+DATA 4 	DDRC_RFSHTMG_0	0x006100E0	// tREFI, tRFC
+DATA 4 	DDRC_INIT0_0  	0x4003061C	// pre_cke = 2ms, post_cke = 2us
+DATA 4 	DDRC_INIT1_0  	0x009E0000	// dram_rstn = 200us
+DATA 4 	DDRC_INIT3_0  	0x0054002D	// MR1, MR2
+DATA 4 	DDRC_INIT4_0  	0x00F10000	// MR3, MR13
+DATA 4	DDRC_RANKCTL_0  	0x0000066F	// diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
+DATA 4	DDRC_DRAMTMG0_0 	0x1A201B22	// wr2pr, tFAW, tRASmax, tRASmin
+DATA 4	DDRC_DRAMTMG1_0 	0x00060633	// tXP, rd2pre, tRC
+DATA 4	DDRC_DRAMTMG2_0 	0x07101817	// WL, RL, rd2wr, wr2rd
+DATA 4	DDRC_DRAMTMG3_0 	0x00C0C000	// tmrw, tmrd, tmod
+DATA 4	DDRC_DRAMTMG4_0 	0x0F04080F	// trcd, tccd, trrd, trp
+DATA 4	DDRC_DRAMTMG5_0 	0x02040C0C	// tCKCKEH, tCKCKEL, tckesr, tcke
+DATA 4	DDRC_DRAMTMG6_0 	0x02020007	// tckdpde, tckdpdx, tckcsx
+DATA 4	DDRC_DRAMTMG7_0 	0x00000401	// tckpde, tckpdx
+DATA 4	DDRC_DRAMTMG12_0	0x00020610	// tCMDCKE, tCKEHCMD
+DATA 4	DDRC_DRAMTMG13_0	0x0C100002	// tODTLoff, tCCDMW, tPPD
+DATA 4	DDRC_DRAMTMG14_0	0x000000E6	// txsr
+DATA 4	DDRC_ZQCTL0_0   	0x03200018	// tZQCAL, tZQLAT
+DATA 4	DDRC_ZQCTL1_0   	0x028061A8	// tZQReset, tzq_short_interval
+DATA 4	DDRC_DFITMG0_0  	0x049E820C	// dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
+DATA 4	DDRC_DFITMG1_0  	0x00070303	// dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
+DATA 4	DDRC_DFITMG2_0  	0x00001C0A	// dfi_tphy_rdcslat, dfi_tphy_wrcslat
+DATA 4	DDRC_DFIMISC_0  	0x00000005	// dfi_data_cs_polarity
+DATA 4	DDRC_DFIUPD0_0  	0x00400003	// Disable the automatic dfi_ctrlupd_req generation
+DATA 4	DDRC_DFIUPD1_0  	0x008000A0	// dfi_ctrlupd_req generation interval generation (min and max)
+DATA 4	DDRC_DFIUPD2_0  	0x80000000	// dfi_phyupd_en
+DATA 4	DDRC_ADDRMAP0_0 	0x00000016	// addrmap_cs_bit0
+DATA 4	DDRC_ADDRMAP3_0 	0x00000000	// addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
+DATA 4	DDRC_ADDRMAP4_0 	0x00001F1F	// addrmap_col_b10 and addrmap_col_b11 set to de-activated
+DATA 4	DDRC_ADDRMAP1_0 	0x00080808	// addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
+DATA 4	DDRC_ADDRMAP5_0 	0x07070707	// addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
+DATA 4	DDRC_ADDRMAP6_0 	0x0F070707	// addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
+DATA 4	DDRC_DBICTL_0   	0x00000007	// rd_dbi_en=wr_dbi_en=dm_en=1
+DATA 4	DDRC_ODTMAP_0   	0x00002211	// rank[3:0]_wr_odt, rank[3:0]_wr_odt
+DATA 4	DDRC_PCTRL_0_0  	0x00000001	// Enable port 0
+DATA 4	DDRC_DFITMG0_SHADOW_0	0x00808000
+
+/* DRAM 1 controller initialization */
+DATA 4	DDRC_MSTR_1     	0xC3080020	// Set LPDDR4, BL = 16 and active ranks
+DATA 4 	DDRC_DERATEEN_1 	0x00000203	// derate enable, derate values, byte to read MRR data
+DATA 4 	DDRC_DERATEINT_1	0x0186A000	// derate MR4 interval read
+DATA 4	DDRC_RFSHTMG_1  	0x006100E0	// tREFI, tRFC
+DATA 4	DDRC_INIT0_1    	0x4003061C	// pre_cke = 2ms, post_cke = 2us
+DATA 4	DDRC_INIT1_1    	0x009E0000	// dram_rstn = 200us
+DATA 4	DDRC_INIT3_1    	0x0054002D	// MR1, MR2
+DATA 4	DDRC_INIT4_1    	0x00F10000	// MR3, MR13
+DATA 4	DDRC_RANKCTL_1  	0x0000066F	// diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
+DATA 4	DDRC_DRAMTMG0_1 	0x1A201B22	// wr2pr, tFAW, tRASmax, tRASmin
+DATA 4	DDRC_DRAMTMG1_1 	0x00060633	// tXP, rd2pre, tRC
+DATA 4	DDRC_DRAMTMG2_1 	0x07101817	// WL, RL, rd2wr, wr2rd
+DATA 4	DDRC_DRAMTMG3_1 	0x00C0C000	// tmrw, tmrd, tmod
+DATA 4	DDRC_DRAMTMG4_1 	0x0F04080F	// trcd, tccd, trrd, trp
+DATA 4	DDRC_DRAMTMG5_1 	0x02040C0C	// tCKCKEH, tCKCKEL, tckesr, tcke
+DATA 4	DDRC_DRAMTMG6_1 	0x02020007	// tckdpde, tckdpdx, tckcsx
+DATA 4	DDRC_DRAMTMG7_1 	0x00000401	// tckpde, tckpdx
+DATA 4	DDRC_DRAMTMG12_1	0x00020610	// tCMDCKE, tCKEHCMD
+DATA 4	DDRC_DRAMTMG13_1	0x0C100002	// tODTLoff, tCCDMW, tPPD
+DATA 4	DDRC_DRAMTMG14_1	0x000000E6	// txsr
+DATA 4	DDRC_ZQCTL0_1   	0x03200018	// tZQCAL, tZQLAT
+DATA 4	DDRC_ZQCTL1_1   	0x028061A8	// tZQReset, tzq_short_interval
+DATA 4	DDRC_DFITMG0_1  	0x049E820C	// dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
+DATA 4	DDRC_DFITMG1_1  	0x00070303	// dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
+DATA 4	DDRC_DFITMG2_1  	0x00001C0A	// dfi_tphy_rdcslat, dfi_tphy_wrcslat
+DATA 4	DDRC_DFIMISC_1  	0x00000005	// dfi_data_cs_polarity
+DATA 4	DDRC_DFIUPD0_1  	0x00400003	// Disable the automatic dfi_ctrlupd_req generation
+DATA 4	DDRC_DFIUPD1_1  	0x008000A0	// dfi_ctrlupd_req generation interval generation (min and max)
+DATA 4	DDRC_DFIUPD2_1  	0x80000000	// dfi_phyupd_en
+DATA 4	DDRC_ADDRMAP0_1 	0x00000016	// addrmap_cs_bit0
+DATA 4	DDRC_ADDRMAP3_1 	0x00000000	// addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
+DATA 4	DDRC_ADDRMAP4_1 	0x00001F1F	// addrmap_col_b10 and addrmap_col_b11 set to de-activated
+DATA 4	DDRC_ADDRMAP1_1 	0x00080808	// addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
+DATA 4	DDRC_ADDRMAP5_1 	0x07070707	// addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
+DATA 4	DDRC_ADDRMAP6_1 	0x0F070707	// addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
+DATA 4	DDRC_DBICTL_1   	0x00000007	// rd_dbi_en=wr_dbi_en=dm_en=1
+DATA 4	DDRC_ODTMAP_1   	0x00002211	// rank[3:0]_wr_odt, rank[3:0]_wr_odt
+DATA 4	DDRC_PCTRL_0_1  	0x00000001	// Enable port 0
+DATA 4	DDRC_DFITMG0_SHADOW_1	0x00808000
+
+DATA 4	0x41a40208	0x1
+DATA 4	0x41d00208	0x1
+DATA 4 	0x41a40040	0xf
+DATA 4 	0x41d00040	0xf
+DATA 4 	0x41a40204	0x1
+DATA 4 	0x41d00204	0x1
+//-------------------------------------------
+// Configure registers for PHY initialization
+//--------------------------------------------
+// Set-up DRAM Configuration Register
+DATA 4	DDR_PHY_DCR_0	0x0000040D	// LPDDR4 selection with 8 bank
+// Set-up byte and bit swapping registers
+DATA 4	DDR_PHY_PGCR8_0    	0x000F0009
+DATA 4	DDR_PHY_DX0DQMAP0_0	0x00070142	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX0DQMAP1_0	0x00008653	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX1DQMAP0_0	0x00056210	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX1DQMAP1_0	0x00008473	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX2DQMAP0_0	0x00065734	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX2DQMAP1_0	0x00008012	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX3DQMAP0_0	0x00061037	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX3DQMAP1_0	0x00008452	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_CATR0_0    	0x00141032	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
+DATA 4	DDR_PHY_CATR1_0    	0x0013AAAA	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
+// Set-up PHY General Configuration Register
+SET_BIT 4 	DDR_PHY_PGCR1_0	0x000A0000	// DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
+DATA 4	DDR_PHY_PGCR0_0	0x87001E00	// Set ADCP=1 (Address Copy)
+DATA 4	DDR_PHY_PGCR2_0	0x00F0D879	// Set tREFPRD
+DATA 4	DDR_PHY_PGCR3_0	0x050A1080	// CKEN/CKNEN toggling and polarity
+// Set-up PHY Timing Register
+// PTR2 is untouched
+DATA 4	DDR_PHY_PTR0_0	0x64032010	// tPLLPD, tPLLGS, tPHYRST
+DATA 4	DDR_PHY_PTR1_0	0x4E201C20	// tPLLLOCK, tPLLRST
+// Set-up PLL Control Register
+DATA 4	DDR_PHY_PLLCR0_0      	0x001C0000
+DATA 4	DDR_PHY_DX8SLbPLLCR0_0	0x001C0000
+// Set-up Impedance Control Register
+DATA 4	DDR_PHY_ZQCR_0	0x008A2C58	// Set ODT_MODE=0b10(LPDDR4 stype pullup)
+// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
+DATA 4 	DDR_PHY_ZQ0PR0_0	0x0001B9BB	// Impedance control for CA bus
+DATA 4 	DDR_PHY_ZQ1PR0_0	0x0001B9BB	// Impedance control for DQ bus
+// Set-up PHY Initialization Register
+DATA 4 	DDR_PHY_PIR_0	0x32
+// Launch initialization (set bit 0)
+DATA 4	DDR_PHY_PIR_0	0x33
+//-------------------------------------------
+// Configure registers for PHY initialization
+//-------------------------------=------------
+// Set-up DRAM 1 PHY Configuration Register
+DATA 4	DDR_PHY_DCR_1	0x0000040D	// LPDDR4 selection with 8 bank
+// Set-up byte and bit swapping registers
+DATA 4	DDR_PHY_PGCR8_1	0x000F000A
+DATA 4	DDR_PHY_DX0DQMAP0_1	0x00021307	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX0DQMAP1_1	0x00008456	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX1DQMAP0_1	0x00072510	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX1DQMAP1_1	0x00008436	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX2DQMAP0_1	0x00056710	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX2DQMAP1_1	0x00008243	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX3DQMAP0_1	0x00031602	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX3DQMAP1_1	0x00008547	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_CATR0_1	0x00141032	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
+DATA 4	DDR_PHY_CATR1_1	0x0103AAAA	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
+// Set-up PHY General Configuration Register
+SET_BIT 4	DDR_PHY_PGCR1_1	0x000A0000	// DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
+DATA 4	DDR_PHY_PGCR0_1	0x87001E00	// Set ADCP=1 (Address Copy)
+DATA 4	DDR_PHY_PGCR2_1	0x00F0D879	// Set tREFPRD
+DATA 4	DDR_PHY_PGCR3_1	0x050A1080	// CKEN/CKNEN toggling and polarity
+// Set-up PHY Timing Register
+// PTR2 is untouched
+DATA 4	DDR_PHY_PTR0_1	0x64032010	// tPLLPD, tPLLGS, tPHYRST
+DATA 4	DDR_PHY_PTR1_1	0x4E201C20	// tPLLLOCK, tPLLRST
+// Set-up PLL Control Register
+DATA 4	DDR_PHY_PLLCR0_1	0x001C0000
+DATA 4	DDR_PHY_DX8SLbPLLCR0_1	0x001C0000
+// Set-up Impedance Control Register
+DATA 4	DDR_PHY_ZQCR_1	0x008A2C58	// Set ODT_MODE=0b10(LPDDR4 stype pullup)
+// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
+DATA 4	DDR_PHY_ZQ0PR0_1	0x0001B9BB	// Impedance control for CA bus
+DATA 4	DDR_PHY_ZQ1PR0_1	0x0001B9BB	// Impedance control for DQ bus
+// Set-up PHY Initialization Register
+DATA 4	DDR_PHY_PIR_1	0x32
+// Launch initialization (set bit 0)
+DATA 4	DDR_PHY_PIR_1	0x33
+//-------------------------------------------
+// Configure registers for DRAM initialization
+//-------------------------------------------
+// Set-up Mode Register
+// MR0, MR3, MR4, MR5 MR6 are untouched
+DATA 4	DDR_PHY_MR1_0	0x54	// Set BL, WR-PRE, nWR, RPST
+DATA 4	DDR_PHY_MR2_0	0x2D	// Set RL/WL
+DATA 4	DDR_PHY_MR3_0	0xF1	// Set drive strength
+
+DATA 4	DDR_PHY_MR11_0	0x54	// Set CA ODT and DQ ODT
+DATA 4	DDR_PHY_MR22_0	0x15	// Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
+/* LPDDR4 mode register writes for CA and DQ VREF settings */
+DATA 4	DDR_PHY_MR12_0	0x48
+DATA 4	DDR_PHY_MR14_0	0x48
+// Set-up DRAM Timing Parameters Register
+// DTPR6 is untouched
+DATA 4	DDR_PHY_DTPR0_0	0x1044220C	// tRRD, tRAS, tRP, tRTP
+DATA 4	DDR_PHY_DTPR1_0	0x28400417	// tWLMRD, tFAW, tODTUP, tMRD
+DATA 4	DDR_PHY_DTPR2_0	0x006CA1CC	// tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
+DATA 4	DDR_PHY_DTPR3_0	0x01800602	// tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
+DATA 4	DDR_PHY_DTPR4_0	0x01C02B0F	// tRFC, tWLO, tXP
+DATA 4	DDR_PHY_DTPR5_0	0x21651D11	// tRC, tRCD, tWTR
+// Set-up PHY Timing Register
+DATA 4	DDR_PHY_PTR3_0	0x0030D400	// tDINIT0
+DATA 4	DDR_PHY_PTR4_0	0x00000C80	// tDINIT1
+DATA 4	DDR_PHY_PTR5_0	0x0004E200	// tDINIT2
+DATA 4	DDR_PHY_PTR6_0	0x03300640	// tDINIT4, tDINIT3
+// Set-up ODT Configuration Register
+// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
+DATA 4	DDR_PHY_RANKIDR_0	0x00000001	// Select rank 1 to write
+DATA 4	DDR_PHY_ODTCR_0	0x00000000	// ODT of rank1 disabled
+DATA 4	DDR_PHY_RANKIDR_0	0x00000000	// Select rank 0 to write
+DATA 4	DDR_PHY_ODTCR_0	0x00000000	// ODT of rank0 disabled
+// Set-up AC I/O Configuration Register
+// ACIOCR1-4 are untouched
+DATA 4	DDR_PHY_ACIOCR0_0	0x30070800	// PNUM2 (i.e.LPDDR4) selection  [10:11] = 0x2
+DATA 4	DDR_PHY_ACIOCR5_0	0x09000000	// I/O mode = LPDDR4
+// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
+DATA 4	DDR_PHY_ACIOCR1_0	0x44000000
+// Set-up VREF Training Control Registers
+DATA 4	DDR_PHY_VTCR0_0	0xF0032008	// CK1, CK0, DRAM VREF set to same as MR12
+DATA 4	DDR_PHY_VTCR1_0	0x07F001AF	// HVIO=1, SHREN=1, SHRNK=0
+// Set-up DATX8 General Configuration Registers
+// DXnGCR0-4 are untouched
+SET_BIT 4	DDR_PHY_PGCR5_0	0x4
+DATA 4	DDR_PHY_PGCR6_0	0x00033200	// Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
+// Set-up DATX8 General Configuration Registers
+DATA 4	DDR_PHY_DX0GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX1GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX2GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX3GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX0GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX1GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX2GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX3GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+// Set-up DATX8 DX Control Register 2
+// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
+DATA 4	DDR_PHY_DX8SLbDXCTL2_0	0x001C1400
+// Set-up DATX8 IO Control Register
+DATA 4	DDR_PHY_DX8SLbIOCR_0	0x79000000	// I/O mode = LPDDR4
+//-------------------------------------------
+// Configure registers for DRAM initialization
+//-------------------------------------------
+// Set-up Mode Register
+// MR0, MR3, MR4, MR5 MR6 are untouched
+DATA 4	DDR_PHY_MR1_1	0x54	// Set BL, WR-PRE, nWR, RPST
+DATA 4	DDR_PHY_MR2_1	0x2D	// Set RL/WL
+DATA 4	DDR_PHY_MR3_1	0xF1	// Set drive strength
+
+DATA 4	DDR_PHY_MR11_1	0x54	// Set CA ODT and DQ ODT
+DATA 4	DDR_PHY_MR22_1	0x15	// Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
+/* LPDDR4 mode register writes for CA and DQ VREF settings */
+DATA 4	DDR_PHY_MR12_1	0x48
+DATA 4	DDR_PHY_MR14_1	0x48
+// Set-up DRAM Timing Parameters Register
+// DTPR6 is untouched
+DATA 4	DDR_PHY_DTPR0_1	0x1044220C	// tRRD, tRAS, tRP, tRTP
+DATA 4	DDR_PHY_DTPR1_1	0x28400417	// tWLMRD, tFAW, tODTUP, tMRD
+DATA 4	DDR_PHY_DTPR2_1	0x006CA1CC	// tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
+DATA 4	DDR_PHY_DTPR3_1	0x01800602	// tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
+DATA 4	DDR_PHY_DTPR4_1	0x01C02B0F	// tRFC, tWLO, tXP
+DATA 4	DDR_PHY_DTPR5_1	0x21651D11	// tRC, tRCD, tWTR
+// Set-up PHY Timing Register
+DATA 4	DDR_PHY_PTR3_1	0x0030D400	// tDINIT0
+DATA 4	DDR_PHY_PTR4_1	0x00000C80	// tDINIT1
+DATA 4	DDR_PHY_PTR5_1	0x0004E200	// tDINIT2
+DATA 4	DDR_PHY_PTR6_1	0x03300640	// tDINIT4, tDINIT3 (1us)
+// Set-up ODT Configuration Register
+// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
+DATA 4	DDR_PHY_RANKIDR_1	0x00000001	// Select rank 1 to write
+DATA 4	DDR_PHY_ODTCR_1	0x00000000	// ODT of rank1 disabled
+DATA 4	DDR_PHY_RANKIDR_1	0x00000000	// Select rank 0 to write
+DATA 4	DDR_PHY_ODTCR_1	0x00000000	// ODT of rank0 disabled
+// Set-up AC I/O Configuration Register
+// ACIOCR1-4 are untouched
+DATA 4	DDR_PHY_ACIOCR0_1	0x30070800	// PNUM2 (i.e.LPDDR4) selection  [10:11] = 0x2
+DATA 4	DDR_PHY_ACIOCR5_1	0x09000000	// I/O mode = LPDDR4
+// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
+DATA 4	DDR_PHY_ACIOCR1_1	0x44000000
+// Set-up VREF Training Control Registers
+DATA 4	DDR_PHY_VTCR0_1	0xF0032008	// CK1, CK0, DRAM VREF set to same as MR12
+DATA 4	DDR_PHY_VTCR1_1	0x07F001AF	// HVIO=1, SHREN=1, SHRNK=0
+// Set-up DATX8 General Configuration Registers
+// DXnGCR0-4 are untouched
+SET_BIT 4	DDR_PHY_PGCR5_1	0x4
+DATA 4	DDR_PHY_PGCR6_1	0x00033200	// Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
+// Set-up DATX8 General Configuration Registers
+DATA 4	DDR_PHY_DX0GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX1GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX2GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX3GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX0GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX1GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX2GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX3GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+// Set-up DATX8 DX Control Register 2
+// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
+DATA 4	DDR_PHY_DX8SLbDXCTL2_1	0x001C1400
+// Set-up DATX8 IO Control Register
+DATA 4	DDR_PHY_DX8SLbIOCR_1	0x79000000	// I/O mode = LPDDR4
+
+#if DDR_TRAIN_IN_DCD
+// Wait PHY initialization end then launch DRAM initialization
+// Wait for bit 0 of PGSR0 to be '1'
+CHECK_BITS_SET 4 	DDR_PHY_PGSR0_0	0x1
+// Wait for bit 0 of PGSR0 to be '1'
+CHECK_BITS_SET 4 	DDR_PHY_PGSR0_1	0x1
+
+// Launch DRAM 0 initialization (set bit 0)
+DATA 4 	DDR_PHY_PIR_0	0x180
+DATA 4 	DDR_PHY_PIR_0	0x181
+// Launch DRAM 1 initialization (set bit 0)
+DATA 4 	DDR_PHY_PIR_1	0x180
+DATA 4 	DDR_PHY_PIR_1	0x181
+
+// DRAM 0 initialization end
+CHECK_BITS_SET 4 	DDR_PHY_PGSR0_0	0x1
+// DRAM 1 initialization end
+CHECK_BITS_SET 4 	DDR_PHY_PGSR0_1	0x1
+
+// Launch a second time DRAM initialization due to following Synopsys PHY bug:
+// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
+// Workaround: "Run DRAM Initialization twice"
+DATA 4 	DDR_PHY_PIR_0	0x100
+DATA 4 	DDR_PHY_PIR_0	0x101
+DATA 4 	DDR_PHY_PIR_1	0x100
+DATA 4 	DDR_PHY_PIR_1	0x101
+
+// Wait (second time) DRAM 0 initialization end
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_0	0x1
+// Wait (second time) DRAM 1 initialization end
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1
+
+//---------------------------------------------------------------//
+// DATA training
+//---------------------------------------------------------------//
+// configure PHY for data training
+// The following register writes are recommended by SNPS prior to running training
+CLR_BIT 4 	DDR_PHY_DQSDR0_0	0x00000001	// Disable drift
+SET_BIT 4 	DDR_PHY_PGCR6_0	0x00000001	// Disable VT compensation
+CHECK_BITS_SET 4 	DDR_PHY_PGSR1_0	0x40000000	// Disable VT compensation
+SET_BIT 4 	DDR_PHY_PGCR1_0	0x00020040	// DISDIC=1; PUBMODE=1
+// Per SNPS initialize BIST registers for VREF training
+DATA 4 	DDR_PHY_BISTAR1_0	0x00010100	//BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
+DATA 4 	DDR_PHY_BISTAR2_0	0x700003FF	// BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
+DATA 4 	DDR_PHY_BISTAR4_0	0x00003FFF	// BMROW=0x4000 (limit to min rows in JEDEC)
+
+CLR_BIT 4 	DDR_PHY_DQSDR0_1	0x00000001	// Disable drift
+SET_BIT 4 	DDR_PHY_PGCR6_1	0x00000001	// Disable VT compensation
+CHECK_BITS_SET 4 	DDR_PHY_PGSR1_1	0x40000000	// Disable VT compensation
+SET_BIT 4 	DDR_PHY_PGCR1_1	0x00020040	// DISDIC=1; PUBMODE=1
+// Per SNPS initialize BIST registers for VREF training
+DATA 4 	DDR_PHY_BISTAR1_1	0x00010100	//BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
+DATA 4 	DDR_PHY_BISTAR2_1	0x700003FF	// BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
+DATA 4 	DDR_PHY_BISTAR4_1	0x00003FFF	// BMROW=0x4000 (limit to min rows in JEDEC)
+
+// Set-up Data Training Configuration Register
+// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
+// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).
+// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
+DATA 4 	DDR_PHY_DTCR0_0	0x000071C7	// Set DTRPTN to 0x7. RFSHDT=0
+DATA 4 	DDR_PHY_DTCR1_0	0x00030236	// Set RANKEN
+DATA 4 	DDR_PHY_DTCR0_1	0x000071C7	// Set DTRPTN to 0x7. RFSHDT=0
+DATA 4 	DDR_PHY_DTCR1_1	0x00030236	// Set RANKEN
+
+// Launch Write leveling
+DATA 4 	DDR_PHY_PIR_0	0x200
+DATA 4 	DDR_PHY_PIR_0	0x201
+DATA 4 	DDR_PHY_PIR_1	0x200
+DATA 4 	DDR_PHY_PIR_1	0x201
+// Wait Write leveling to complete
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_0	0x1
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_0	0x00200000
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_1	0x00200000
+
+// Set DQS/DQSn glitch suppression resistor for training PHY0
+DATA 4 	DDR_PHY_DX8SLbDQSCTL_0	0x012640F7
+// Launch Read DQS training
+DATA 4 	DDR_PHY_PIR_0	0x400
+DATA 4 	DDR_PHY_PIR_0	0x401
+// Set DQS/DQSn glitch suppression resistor for training PHY1
+DATA 4 	DDR_PHY_DX8SLbDQSCTL_1	0x012640F7
+// Launch Read DQS training
+DATA 4 	DDR_PHY_PIR_1	0x400
+DATA 4 	DDR_PHY_PIR_1	0x401
+// Wait Read DQS training to complete PHY0
+CHECK_BITS_SET 4 	DDR_PHY_PGSR0_0	0x1
+CHECK_BITS_CLR 4 	DDR_PHY_PGSR0_0	0x00400000
+// Remove DQS/DQSn glitch suppression resistor PHY0
+DATA 4 	DDR_PHY_DX8SLbDQSCTL_0	0x01264000
+// Wait Read DQS training to complete PHY1
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_1	0x00400000
+// Remove DQS/DQSn glitch suppression resistor PHY1
+DATA 4 	DDR_PHY_DX8SLbDQSCTL_1	0x01264000
+
+// DQS2DQ training, Write leveling, Deskew and eye trainings
+DATA 4	DDR_PHY_PIR_0	0x0010F800
+DATA 4	DDR_PHY_PIR_0	0x0010F801
+DATA 4	DDR_PHY_PIR_1	0x0010F800
+DATA 4	DDR_PHY_PIR_1	0x0010F801
+// Wait for training to complete
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_0 	0x1
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_0 	0x7FF40000
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_1 	0x1
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_1 	0x7FF40000
+
+// Launch VREF training
+DATA 4	DDR_PHY_PIR_0	0x00020000
+DATA 4	DDR_PHY_PIR_0	0x00020001
+DATA 4	DDR_PHY_PIR_1	0x00020000
+DATA 4	DDR_PHY_PIR_1	0x00020001
+// Wait for training to complete
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_0	0x1
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_0	0x00080000
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_1	0x00080000
+
+//Re-allow uMCTL2 to send commands to DDR
+CLR_BIT 4	DDR_PHY_PGCR1_0	0x00020040	// DISDIC=0, PUBMODE=0
+CLR_BIT 4	DDR_PHY_PGCR1_1	0x00020040	// DISDIC=0, PUBMODE=0
+
+//DQS Drift Registers PHY0
+CLR_BIT 4	DDR_PHY_DX0GCR3_0	0x08000000
+CLR_BIT 4	DDR_PHY_DX1GCR3_0	0x08000000
+CLR_BIT 4	DDR_PHY_DX2GCR3_0	0x08000000
+CLR_BIT 4	DDR_PHY_DX3GCR3_0	0x08000000
+// Enable DQS drift detection PHY0
+DATA 4 	DDR_PHY_DQSDR0_0	0x20188005
+DATA 4 	DDR_PHY_DQSDR1_0	0xA8AA0000
+DATA 4 	DDR_PHY_DQSDR2_0	0x00070200
+//DQS Drift Registers PHY1
+CLR_BIT 4	DDR_PHY_DX0GCR3_1	0x08000000
+CLR_BIT 4	DDR_PHY_DX1GCR3_1	0x08000000
+CLR_BIT 4	DDR_PHY_DX2GCR3_1	0x08000000
+CLR_BIT 4	DDR_PHY_DX3GCR3_1	0x08000000
+// Enable DQS drift detection PHY1
+DATA 4 	DDR_PHY_DQSDR0_1	0x20188005
+DATA 4 	DDR_PHY_DQSDR1_1	0xA8AA0000
+DATA 4 	DDR_PHY_DQSDR2_1	0x00070200
+
+// Enable VT compensation
+CLR_BIT 4	DDR_PHY_PGCR6_0	0x1
+CLR_BIT 4	DDR_PHY_PGCR6_1	0x1
+
+//Check that controller is ready to operate
+CHECK_BITS_SET 4	DDRC_STAT_0	0x1
+CHECK_BITS_SET 4	DDRC_STAT_1	0x1
+
+#endif
diff --git a/iMX8QM/imx8qm_apalis-imx8_dcd_800MHz.cfg b/iMX8QM/imx8qm_apalis-imx8_dcd_800MHz.cfg
new file mode 100755
index 0000000..8ded32d
--- /dev/null
+++ b/iMX8QM/imx8qm_apalis-imx8_dcd_800MHz.cfg
@@ -0,0 +1,523 @@
+#define __ASSEMBLY__			
+			
+#include <ddrc_mem_map.h>			
+#include <ddr_phy_mem_map.h>			
+			
+/*			
+ * Device Configuration Data (DCD)			
+ *			
+ * Each entry must have the format:			
+ * Addr-type           Address        Value			
+ *			
+ * where:			
+ * Addr-type register length (1,2 or 4 bytes)			
+ * Address   absolute address of the register			
+ * value   value to be stored in the register			
+ */			
+			
+#ifndef SCFW_DCD			
+/* For 800MHz DDR, DRC 400MHz operation */			
+DATA 4	0xff148000	0x00000C85	/* DRC0 bringup */
+DATA 4	0xff1a0000	0x00000C85	/* DRC1 bringup */
+#else			
+/* Set the DRC rate to 800MHz. */
+uint32_t rate2 = SC_400MHZ;			
+pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);			
+pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &rate2);			
+#endif			
+			
+DATA 4	0x41a40208	0x1	
+DATA 4	0x41d00208	0x1	
+DATA 4	0x41a40040	0xb	
+DATA 4	0x41d00040	0xb	
+DATA 4	0x41a40204	0x1	
+DATA 4	0x41d00204	0x1	
+/* DRAM 0 controller configuration begin */			
+DATA 4 	DDRC_MSTR_0   	0xC3080020	// Set LPDDR4, BL = 16 and active ranks
+DATA 4 	DDRC_RFSHTMG_0	0x002E0072	// tREFI, tRFC
+DATA 4 	DDRC_INIT0_0  	0x40020320	// pre_cke 
+DATA 4 	DDRC_INIT1_0  	0x00520000	// dram_rstn 
+DATA 4	DDRC_INIT3_0  	0x00240012	// MR1=0x54: nWR=30 BL=16;  MR2=0x2d: RL=28 WL=14
+DATA 4	DDRC_INIT4_0  	0x00310000	// MR3, MR13
+DATA 4	DDRC_RANKCTL_0  	0x0000075f	// diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd 
+DATA 4	DDRC_DRAMTMG0_0 	0x11110D11	// wr2pr, tFAW, tRASmax, tRASmin
+DATA 4	DDRC_DRAMTMG1_0 	0x0004041A	// tXP, rd2pre, tRC
+DATA 4	DDRC_DRAMTMG2_0 	0x04070C0D	// WL, RL, rd2wr, wr2rd
+DATA 4	DDRC_DRAMTMG3_0 	0x00606007	// tmrw, tmrd, tmod
+DATA 4	DDRC_DRAMTMG4_0 	0x08040509	// trcd, tccd, trrd, trp
+DATA 4	DDRC_DRAMTMG5_0 	0x02030707	// tCKCKEH, tCKCKEL, tckesr, tcke
+DATA 4	DDRC_DRAMTMG6_0 	0x02020005	// tckdpde, tckdpdx, tckcsx
+DATA 4	DDRC_DRAMTMG7_0 	0x00000302	// tckpde, tckpdx
+DATA 4	DDRC_DRAMTMG12_0	0x00020300	// tCMDCKE, tCKEHCMD (=tXP?)
+DATA 4	DDRC_DRAMTMG13_0	0x0a100002	// tODTLoff, tCCDMW, tPPD
+DATA 4	DDRC_DRAMTMG14_0	0x00000074	// txsr
+DATA 4	DDRC_ZQCTL0_0   	0x0192000d	// tZQCAL, tZQLAT
+DATA 4	DDRC_ZQCTL1_0   	0x01400100	// tZQReset, tzq_short_interval
+DATA 4	DDRC_DFITMG0_0  	0x048C8206	// dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
+DATA 4	DDRC_DFITMG1_0  	0x00060303	// dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
+DATA 4	DDRC_DFITMG2_0  	0x00000A04	// dfi_tphy_rdcslat, dfi_tphy_wrcslat
+DATA 4	DDRC_DFIMISC_0  	0x00000005	// dfi_data_cs_polarity
+DATA 4	DDRC_DFIUPD0_0  	0x00400003	// Disable the automatic dfi_ctrlupd_req generation
+DATA 4	DDRC_DFIUPD1_0  	0x008000A0	// dfi_ctrlupd_req generation interval generation (min and max)
+DATA 4	DDRC_DFIUPD2_0  	0x80000000	// dfi_phyupd_en
+DATA 4	DDRC_ADDRMAP4_0 0x00001F1F	// addrmap_col_b10 and addrmap_col_b11 set to de-activated
+DATA 4	DDRC_ADDRMAP1_0 0x00080808	// addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
+DATA 4	DDRC_ADDRMAP5_0 0x07070707	// addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
+
+// For 16Gb configurations
+// Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0
+DATA 4	DDRC_ADDRMAP0_0 0x00000016	// addrmap_cs_bit0 (board memory)
+DATA 4	DDRC_ADDRMAP6_0 0x0F070707	// addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 (board memory)
+
+// Per QXP team, ODTMAP not use for LP4, need to confirm for QM
+DATA 4	DDRC_ODTMAP_0 0x00002211	// rank[3:0]_wr_odt, rank[3:0]_wr_odt
+//DATA 4	DDRC_ODTMAP_0 0x00000000   
+DATA 4	DDRC_PCTRL_0_0 0x00000001	// Enable port 0
+
+DATA 4	DDRC_DFITMG0_SHADOW_0 0x00808000
+
+/* DRAM 1 controller initialization */			
+DATA 4	DDRC_MSTR_1     	0xC3080020	// Set LPDDR4, BL = 16 and active ranks
+DATA 4	DDRC_RFSHTMG_1  	0x002E0072	// tREFI, tRFC
+DATA 4	DDRC_INIT0_1    	0x40020320	// pre_cke 
+DATA 4	DDRC_INIT1_1    	0x00520000	// dram_rstn 
+DATA 4	DDRC_INIT3_1    	0x00240012	// MR1=0x54: nWR=30 BL=16;  MR2=0x2d: RL=28 WL=14
+DATA 4	DDRC_INIT4_1    	0x00310000	// MR3, MR13
+DATA 4	DDRC_RANKCTL_1  	0x0000075f	// diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd 
+DATA 4	DDRC_DRAMTMG0_1 	0x11110D11	// wr2pr, tFAW, tRASmax, tRASmin
+DATA 4	DDRC_DRAMTMG1_1 	0x0004041A	// tXP, rd2pre, tRC
+DATA 4	DDRC_DRAMTMG2_1 	0x04070C0D	// WL, RL, rd2wr, wr2rd
+DATA 4	DDRC_DRAMTMG3_1 	0x00606007	// tmrw, tmrd, tmod
+DATA 4	DDRC_DRAMTMG4_1 	0x08040509	// trcd, tccd, trrd, trp
+DATA 4	DDRC_DRAMTMG5_1 	0x02030707	// tCKCKEH, tCKCKEL, tckesr, tcke
+DATA 4	DDRC_DRAMTMG6_1 	0x02020005	// tckdpde, tckdpdx, tckcsx
+DATA 4	DDRC_DRAMTMG7_1 	0x00000302	// tckpde, tckpdx
+DATA 4	DDRC_DRAMTMG12_1	0x00020300	// tCMDCKE, tCKEHCMD (=tXP?)
+DATA 4	DDRC_DRAMTMG13_1	0x0a100002	// tODTLoff, tCCDMW, tPPD
+DATA 4	DDRC_DRAMTMG14_1	0x00000074	// txsr
+DATA 4	DDRC_ZQCTL0_1   	0x0192000d	// tZQCAL, tZQLAT
+DATA 4	DDRC_ZQCTL1_1   	0x01400100	// tZQReset, tzq_short_interval
+DATA 4	DDRC_DFITMG0_1  	0x048C8206	// dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
+DATA 4	DDRC_DFITMG1_1  	0x00060303	// dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
+DATA 4	DDRC_DFITMG2_1  	0x00000A04	// dfi_tphy_rdcslat, dfi_tphy_wrcslat
+DATA 4	DDRC_DFIMISC_1  	0x00000005	// dfi_data_cs_polarity
+DATA 4	DDRC_DFIUPD0_1  	0x00400003	// Disable the automatic dfi_ctrlupd_req generation
+DATA 4	DDRC_DFIUPD1_1  	0x008000A0	// dfi_ctrlupd_req generation interval generation (min and max)
+DATA 4	DDRC_DFIUPD2_1  	0x80000000	// dfi_phyupd_en
+DATA 4	DDRC_ADDRMAP4_1 	0x00001F1F	// addrmap_col_b10 and addrmap_col_b11 set to de-activated
+DATA 4	DDRC_ADDRMAP1_1 	0x00080808	// addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
+DATA 4	DDRC_ADDRMAP5_1 	0x07070707	// addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
+
+// For 16Gb configurations
+// Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0
+DATA 4	DDRC_ADDRMAP0_1 0x00000016	// addrmap_cs_bit0 (board memory)
+DATA 4	DDRC_ADDRMAP6_1 0x0F070707	// addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 (board memory)
+
+// Per QXP team, ODTMAP not use for LP4, need to confirm for QM
+DATA 4	DDRC_ODTMAP_1 0x00002211	// rank[3:0]_wr_odt, rank[3:0]_wr_odt
+//DATA 4	DDRC_ODTMAP_1 0x00000000 
+DATA 4	DDRC_PCTRL_0_1  	0x00000001	// Enable port 0
+DATA 4	DDRC_DFITMG0_SHADOW_1	0x00808000	
+DATA 4	0x41a40208	0x1	
+DATA 4	0x41d00208	0x1	
+DATA 4 	0x41a40040	0xf	
+DATA 4 	0x41d00040	0xf	
+DATA 4 	0x41a40204	0x1	
+DATA 4 	0x41d00204	0x1	
+//-------------------------------------------			
+// Configure registers for PHY initialization			
+// Timings are computed for 1600MHz DRAM operation			
+//--------------------------------------------			
+// Set-up DRAM Configuration Register			
+DATA 4	DDR_PHY_DCR_0	0x0000040D	// LPDDR4 selection with 8 bank
+// Set-up byte and bit swapping registers			
+DATA 4	DDR_PHY_PGCR8_0    	0x000F0009	// Set BSWAPMSB='b1001 (byte 0 and 1 are swapped)
+DATA 4	DDR_PHY_DX0DQMAP0_0	0x00070142	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX0DQMAP1_0	0x00008653	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX1DQMAP0_0	0x00056210	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX1DQMAP1_0	0x00008473	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX2DQMAP0_0	0x00065734	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX2DQMAP1_0	0x00008012	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX3DQMAP0_0	0x00061037	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX3DQMAP1_0	0x00008452	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_CATR0_0    	0x00141032	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
+DATA 4	DDR_PHY_CATR1_0    	0x0013AAAA	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
+// Set-up PHY General Configuration Register			
+// PGCR1,4,5,6,7 are untouched			
+SET_BIT 4 	DDR_PHY_PGCR1_0	0x00020000	// DISDIC=1 (no uMCTL2 commands can go to memory)
+DATA 4	DDR_PHY_PGCR0_0	0x87001E00	// Set ADCP=1 (Address Copy)
+DATA 4	DDR_PHY_PGCR2_0	0x00F06AAC	// Set tREFPRD (9*3.904us - 600)
+DATA 4	DDR_PHY_PGCR3_0	0x050A1080	// CKEN/CKNEN toggling and polarity
+// Set-up PHY Timing Register			
+// PTR2 is untouched			
+DATA 4	DDR_PHY_PTR0_0	0x32019010	// tPLLPD, tPLLGS, tPHYRST
+DATA 4	DDR_PHY_PTR1_0	0x27100E10	// tPLLLOCK reduced to 4.3us, tPLLRST=9us
+// Set-up PLL Control Register			
+DATA 4	DDR_PHY_PLLCR0_0      	0x02120000	// FREQSEL=2, CPPC=0x9
+DATA 4	DDR_PHY_DX8SLbPLLCR0_0	0x02120000	
+// Set-up Impedance Control Register			
+DATA 4	DDR_PHY_ZQCR_0 0x008A2C58	// Set ODT_MODE=0b10(LPDDR4 stype pullup)
+// ZPROG_DRAM_ODT and ZPROG_HOST_ODT = 60ohm
+DATA 4 	DDR_PHY_ZQ0PR0_0	0x1B9BB // Updated ZPROG_HOST_ODT per QXP analysis
+DATA 4 	DDR_PHY_ZQ1PR0_0	0x1B9BB	// Updated ZPROG_HOST_ODT per QXP analysis
+// Set-up PHY Initialization Register			
+DATA 4 	DDR_PHY_PIR_0	0x32	
+// Launch initialization (set bit 0)			
+DATA 4	DDR_PHY_PIR_0	0x33	
+//-------------------------------------------			
+// Configure registers for PHY initialization			
+// Timings are computed for a PHY at 800MHz (DRAM at 1600MHz)			
+//-------------------------------=------------			
+// Set-up DRAM 1 PHY Configuration Register			
+DATA 4	DDR_PHY_DCR_1	0x0000040D	// LPDDR4 selection with 8 bank
+// Set-up byte and bit swapping registers			
+DATA 4	DDR_PHY_PGCR8_1	0x000F000F	// Set BSWAPMSB='b0000
+DATA 4	DDR_PHY_DX0DQMAP0_1	0x00021307	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX0DQMAP1_1	0x00008456	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX1DQMAP0_1	0x00072510	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX1DQMAP1_1	0x00008436	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX2DQMAP0_1	0x00056710	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX2DQMAP1_1	0x00008243	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_DX3DQMAP0_1	0x00031602	// DQ bit 0/1/2/3/4 remapping
+DATA 4	DDR_PHY_DX3DQMAP1_1	0x00008547	// DQ bit 5/6/7 and DM remapping
+DATA 4	DDR_PHY_CATR0_1	0x00141032	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
+DATA 4	DDR_PHY_CATR1_1	0x0013AAAA	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
+// Set-up PHY General Configuration Register			
+// PGCR1,4,5,6,7 are untouched			
+SET_BIT 4	DDR_PHY_PGCR1_1	0x00020000	// DISDIC=1 (no uMCTL2 commands can go to memory)
+DATA 4	DDR_PHY_PGCR0_1	0x87001E00	// Set ADCP=1 (Address Copy)
+DATA 4	DDR_PHY_PGCR2_1	0x00F06AAC	// Set tREFPRD (9*3.904us - 600)
+DATA 4	DDR_PHY_PGCR3_1	0x050A1080	// CKEN/CKNEN toggling and polarity
+// Set-up PHY Timing Register			
+// PTR2 is untouched			
+DATA 4	DDR_PHY_PTR0_1	0x32019010	// tPLLPD, tPLLGS, tPHYRST
+DATA 4	DDR_PHY_PTR1_1	0x27100E10	// tPLLLOCK reduced to 4.3us, tPLLRST=9us
+// Set-up PLL Control Register			
+DATA 4	DDR_PHY_PLLCR0_1	0x02120000	// FREQSEL=2, CPPC=0x9
+DATA 4	DDR_PHY_DX8SLbPLLCR0_1	0x02120000
+// Set-up Impedance Control Register			
+DATA 4	DDR_PHY_ZQCR_1 0x008A2C58	// Set ODT_MODE=0b10(LPDDR4 stype pullup)
+// ZPROG_DRAM_ODT and ZPROG_HOST_ODT = 60ohm
+DATA 4	DDR_PHY_ZQ0PR0_1	0x1B9BB     	// Updated ZPROG_HOST_ODT per QXP analysis
+DATA 4	DDR_PHY_ZQ1PR0_1	0x1B9BB     	// Updated ZPROG_HOST_ODT per QXP analysis
+// Set-up PHY Initialization Register			
+DATA 4	DDR_PHY_PIR_1	0x32	
+// Launch initialization (set bit 0)			
+DATA 4	DDR_PHY_PIR_1	0x33	
+//-------------------------------------------			
+// Configure registers for DRAM initialization			
+//-------------------------------------------			
+// Set-up Mode Register			
+// MR0, MR3, MR4, MR5 MR6 are untouched			
+DATA 4	DDR_PHY_MR1_0	0x24	// Set BL, WR-PRE, nWR, RPST
+DATA 4	DDR_PHY_MR2_0	0x12	// Set RL=28/WL=14
+DATA 4	DDR_PHY_MR3_0	0x31	// Set drive strength (40 Ohms by default)
+			
+DATA 4	DDR_PHY_MR11_0	0x04	// Set CA ODT=RZQ/4, updated per QXP analysis
+DATA 4	DDR_PHY_MR22_0	0x15	// Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
+/* LPDDR4 mode register writes for CA and DQ VREF settings; range=1, 27.2% */			
+DATA 4	DDR_PHY_MR12_0	0x48	
+DATA 4	DDR_PHY_MR14_0	0x48	
+// Set-up DRAM Timing Parameters Register			
+// DTPR6 is untouched			
+DATA 4	DDR_PHY_DTPR0_0	0x09221108	// tRRD, tRAS, tRP, tRTP
+DATA 4	DDR_PHY_DTPR1_0	0x28200D0E	// tWLMRD, tFAW, tODTUP, tMRD
+DATA 4	DDR_PHY_DTPR2_0	0x006740E7	// tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
+DATA 4	DDR_PHY_DTPR3_0	0x01800302	// tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
+DATA 4	DDR_PHY_DTPR4_0	0x00E10F0A	// tRFC, tWLO, tXP
+DATA 4	DDR_PHY_DTPR5_0	0x11330F0A	// tRC, tRCD, tWTR
+// Set-up PHY Timing Register			
+DATA 4	DDR_PHY_PTR3_0	0x00186A10	// tDINIT0 - 2ms
+DATA 4	DDR_PHY_PTR4_0	0x00000650	// tDINIT1 (2000ns)
+DATA 4	DDR_PHY_PTR5_0	0x00027110	// tDINIT2 
+DATA 4	DDR_PHY_PTR6_0	0x01C00330	// tDINIT4 (30ns), tDINIT3 (1us)
+// Set-up DATX8 Common Configuration Register			
+// DXCCR is untouched
+
+// Set-up DDR System General Configuration Register
+// DSGCR is untouched
+
+// Set-up ODT Configuration Register
+// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
+DATA 4	DDR_PHY_RANKIDR_0 1         	// Select rank 1 to write
+DATA 4	DDR_PHY_ODTCR_0 0x00000000  	// ODT of rank1 disabled
+DATA 4	DDR_PHY_RANKIDR_0 0         	// Select rank 0 to write
+DATA 4	DDR_PHY_ODTCR_0 0x00000000  	// ODT of rank0 disabled
+
+// Set-up Anti-Aging Control Register
+// AACR is untouched
+
+// Set-up Data Training Address Register
+// DTAR0-3 are untouched
+// !! DTAR3 is not described in spec !!
+
+// Set-up AC I/O Configuration Register
+// ACIOCR1-4 are untouched
+DATA 4	DDR_PHY_ACIOCR0_0 0x30070800	// PNUM2 (i.e.LPDDR4) selection  [10:11] = 0x2
+DATA 4	DDR_PHY_ACIOCR5_0 0x09000000	// I/O mode = LPDDR4
+// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
+DATA 4	DDR_PHY_ACIOCR1_0 0x44000000
+
+// IOVCR0-1, DXnGCR0-4??, CALBYP
+// Set-up VREF Training Control Registers			
+DATA 4	DDR_PHY_VTCR0_0	0xF0032008	// CK1, CK0, DRAM VREF set to same as MR12
+DATA 4	DDR_PHY_VTCR1_0	0x07F00173	// HVIO=1, SHREN=1, SHRNK=0
+// Set-up DATX8 General Configuration Registers			
+// DXnGCR0-4 are untouched			
+SET_BIT 4	DDR_PHY_PGCR5_0	0x4	
+DATA 4	DDR_PHY_PGCR6_0	0x00033200	// Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
+// Set-up DATX8 General Configuration Registers			
+DATA 4	DDR_PHY_DX0GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX1GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX2GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX3GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX0GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX1GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX2GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX3GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+// Set-up DATX8 DX Control Register 2			
+// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA			
+DATA 4	DDR_PHY_DX8SLbDXCTL2_0	0x001C1400	
+// Set-up DATX8 IO Control Register			
+DATA 4	DDR_PHY_DX8SLbIOCR_0	0x79000000	// I/O mode = LPDDR4
+//-------------------------------------------			
+// Configure registers for DRAM initialization			
+//-------------------------------------------			
+// Set-up Mode Register			
+// MR0, MR3, MR4, MR5 MR6 are untouched			
+DATA 4	DDR_PHY_MR1_1	0x24	// Set BL, WR-PRE, nWR, RPST
+DATA 4	DDR_PHY_MR2_1	0x12	// Set RL=28/WL=14
+DATA 4	DDR_PHY_MR3_1	0x31	// Set drive strength (40 Ohms by default)
+			
+DATA 4	DDR_PHY_MR11_1	0x04	// Set CA ODT=RZQ/4, updated per QXP analysis
+DATA 4	DDR_PHY_MR22_1	0x15	// Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
+/* LPDDR4 mode register writes for CA and DQ VREF settings; range=1, 27.2% */			
+DATA 4	DDR_PHY_MR12_1	0x48	
+DATA 4	DDR_PHY_MR14_1	0x48	
+// Set-up DRAM Timing Parameters Register			
+// DTPR6 is untouched			
+DATA 4	DDR_PHY_DTPR0_1	0x09221108	// tRRD, tRAS, tRP, tRTP
+DATA 4	DDR_PHY_DTPR1_1	0x28200D0E	// tWLMRD, tFAW, tODTUP, tMRD
+DATA 4	DDR_PHY_DTPR2_1	0x006740E7	// tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
+DATA 4	DDR_PHY_DTPR3_1	0x01800302	// tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
+DATA 4	DDR_PHY_DTPR4_1	0x00E10F0A	// tRFC, tWLO, tXP
+DATA 4	DDR_PHY_DTPR5_1	0x11330F0A	// tRC, tRCD, tWTR
+// Set-up PHY Timing Register			
+DATA 4	DDR_PHY_PTR3_1	0x00186A10// tDINIT0 
+DATA 4	DDR_PHY_PTR4_1	0x00000650	// tDINIT1 (2000ns)
+DATA 4	DDR_PHY_PTR5_1	0x00027110	// tDINIT2
+DATA 4	DDR_PHY_PTR6_1	0x01C00330	// tDINIT4 (30ns), tDINIT3 (1us)
+
+// Set-up DATX8 Common Configuration Register
+// DXCCR is untouched
+
+// Set-up DDR System General Configuration Register
+// DSGCR is untouched
+
+// Set-up ODT Configuration Register
+// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
+DATA 4	DDR_PHY_RANKIDR_1 1         	// Select rank 1 to write
+DATA 4	DDR_PHY_ODTCR_1 0x00000000  	// ODT of rank1 disabled
+DATA 4	DDR_PHY_RANKIDR_1 0         	// Select rank 0 to write
+DATA 4	DDR_PHY_ODTCR_1 0x00000000  	// ODT of rank0 disabled
+
+// Set-up Anti-Aging Control Register
+// AACR is untouched
+
+// Set-up Data Training Address Register
+// DTAR0-3 are untouched
+// !! DTAR3 is not described in spec !!
+
+// Set-up AC I/O Configuration Register
+// ACIOCR2-4 are untouched
+DATA 4	DDR_PHY_ACIOCR0_1 0x30070800	// PNUM2 (i.e.LPDDR4) selection  [10:11] = 0x2
+DATA 4	DDR_PHY_ACIOCR5_1 0x09000000	// I/O mode = LPDDR4
+// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
+DATA 4	DDR_PHY_ACIOCR1_1 0x44000000
+
+// IOVCR0-1, DXnGCR0-4??, CALBYP
+
+// Set-up VREF Training Control Registers			
+DATA 4	DDR_PHY_VTCR0_1	0xF0032008	// CK1, CK0, DRAM VREF set to same as MR12
+DATA 4	DDR_PHY_VTCR1_1	0x07F00173	// HVIO=1, SHREN=1, SHRNK=0
+// Set-up DATX8 General Configuration Registers			
+// DXnGCR0-4 are untouched			
+SET_BIT 4	DDR_PHY_PGCR5_1	0x4	
+DATA 4	DDR_PHY_PGCR6_1	0x00033200	// Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
+// Set-up DATX8 General Configuration Registers			
+DATA 4	DDR_PHY_DX0GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX1GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX2GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX3GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
+DATA 4	DDR_PHY_DX0GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX1GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX2GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+DATA 4	DDR_PHY_DX3GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
+// Set-up DATX8 DX Control Register 2			
+// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA			
+DATA 4	DDR_PHY_DX8SLbDXCTL2_1	0x001C1400	
+// Set-up DATX8 IO Control Register			
+DATA 4	DDR_PHY_DX8SLbIOCR_1	0x79000000	// I/O mode = LPDDR4
+			
+#if DDR_TRAIN_IN_DCD			
+/* Training done in Firmware, due to DCD size limitation */			
+
+// Wait PHY initialization end then launch DRAM initialization			
+// Wait for bit 0 of PGSR0 to be '1'			
+CHECK_BITS_SET 4 	DDR_PHY_PGSR0_0	0x1	
+CHECK_BITS_CLR 4 	DDR_PHY_PGSR0_0	0x7FF40000	// Check that no error occured
+// Wait for bit 0 of PGSR0 to be '1'			
+CHECK_BITS_SET 4 	DDR_PHY_PGSR0_1	0x1	
+CHECK_BITS_CLR 4 	DDR_PHY_PGSR0_1	0x7FF40000	// Check that no error occured
+			
+// Launch DRAM 0 initialization (set bit 0)			
+DATA 4 	DDR_PHY_PIR_0	0x180	
+DATA 4 	DDR_PHY_PIR_0	0x181	
+// Launch DRAM 1 initialization (set bit 0)			
+DATA 4 	DDR_PHY_PIR_1	0x180	
+DATA 4 	DDR_PHY_PIR_1	0x181	
+			
+// DRAM 0 initialization end			
+CHECK_BITS_SET 4 	DDR_PHY_PGSR0_0	0x1	
+CHECK_BITS_CLR 4 	DDR_PHY_PGSR0_0	0x7FF40000	
+// DRAM 1 initialization end			
+CHECK_BITS_SET 4 	DDR_PHY_PGSR0_1	0x1	
+CHECK_BITS_CLR 4 	DDR_PHY_PGSR0_1	0x7FF40000	
+			
+// Launch a second time DRAM initialization due to following Synopsys PHY bug:			
+// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"			
+// Workaround: "Run DRAM Initialization twice"			
+DATA 4 	DDR_PHY_PIR_0	0x100	
+DATA 4 	DDR_PHY_PIR_0	0x101	
+DATA 4 	DDR_PHY_PIR_1	0x100	
+DATA 4 	DDR_PHY_PIR_1	0x101	
+			
+// Wait (second time) DRAM 0 initialization end			
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_0	0x1	
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_0	0x7FF40000	
+// Wait (second time) DRAM 1 initialization end			
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1	
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_1	0x7FF40000	
+			
+//---------------------------------------------------------------//			
+// DATA training			
+//---------------------------------------------------------------//			
+// configure PHY for data training			
+// The following register writes are recommended by SNPS prior to running training			
+CLR_BIT 4 	DDR_PHY_DQSDR0_0	0x00000001	// Disable drift
+SET_BIT 4 	DDR_PHY_PGCR6_0	0x00000001	// Disable VT compensation
+CHECK_BITS_SET 4 	DDR_PHY_PGSR1_0	0x40000000	// Disable VT compensation
+SET_BIT 4 	DDR_PHY_PGCR1_0	0x00020040	// DISDIC=1; PUBMODE=1
+// Per SNPS initialize BIST registers for VREF training			
+DATA 4 	DDR_PHY_BISTAR1_0	0x00010100	//BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
+DATA 4 	DDR_PHY_BISTAR2_0	0x700003FF	// BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
+DATA 4 	DDR_PHY_BISTAR4_0	0x00003FFF	// BMROW=0x4000 (limit to min rows in JEDEC)
+			
+CLR_BIT 4 	DDR_PHY_DQSDR0_1	0x00000001	// Disable drift
+SET_BIT 4 	DDR_PHY_PGCR6_1	0x00000001	// Disable VT compensation
+CHECK_BITS_SET 4 	DDR_PHY_PGSR1_1	0x40000000	// Disable VT compensation
+SET_BIT 4 	DDR_PHY_PGCR1_1	0x00020040	// DISDIC=1; PUBMODE=1
+// Per SNPS initialize BIST registers for VREF training			
+DATA 4 	DDR_PHY_BISTAR1_1	0x00010100	//BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
+DATA 4 	DDR_PHY_BISTAR2_1	0x700003FF	// BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
+DATA 4 	DDR_PHY_BISTAR4_1	0x00003FFF	// BMROW=0x4000 (limit to min rows in JEDEC)
+			
+// Set-up Data Training Configuration Register			
+// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys			
+// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).			
+// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).			
+DATA 4 	DDR_PHY_DTCR0_0	0x0000B1CF	// Set DTRPTN to 0xF. RFSHDT=0. (note this is for the non DBI setting)
+DATA 4 	DDR_PHY_DTCR1_0	0x00030236	// Set RANKEN=3
+DATA 4 	DDR_PHY_DTCR0_1	0x0000B1CF	// Set DTRPTN to 0xF. RFSHDT=0. (note this is for the non DBI setting)
+DATA 4 	DDR_PHY_DTCR1_1	0x00030236	// Set RANKEN=3
+			
+// Launch Write leveling			
+DATA 4 	DDR_PHY_PIR_0	0x200	
+DATA 4 	DDR_PHY_PIR_0	0x201	
+DATA 4 	DDR_PHY_PIR_1	0x200	
+DATA 4 	DDR_PHY_PIR_1	0x201	
+// Wait Write leveling to complete			
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_0	0x1	
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_0	0x00200000	
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1	
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_1	0x00200000	
+			
+// Set DQS/DQSn glitch suppression resistor for training PHY0			
+DATA 4 	DDR_PHY_DX8SLbDQSCTL_0	0x012640F7	
+// Launch Read DQS training			
+DATA 4 	DDR_PHY_PIR_0	0x400	
+DATA 4 	DDR_PHY_PIR_0	0x401	
+// Set DQS/DQSn glitch suppression resistor for training PHY1			
+DATA 4 	DDR_PHY_DX8SLbDQSCTL_1	0x012640F7	
+// Launch Read DQS training			
+DATA 4 	DDR_PHY_PIR_1	0x400	
+DATA 4 	DDR_PHY_PIR_1	0x401	
+// Wait Read DQS training to complete PHY0			
+CHECK_BITS_SET 4 	DDR_PHY_PGSR0_0	0x1	
+CHECK_BITS_CLR 4 	DDR_PHY_PGSR0_0	0x00400000	
+// Remove DQS/DQSn glitch suppression resistor PHY0			
+DATA 4 	DDR_PHY_DX8SLbDQSCTL_0	0x01264000	
+// Wait Read DQS training to complete PHY1			
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1	
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_1	0x00400000	
+// Remove DQS/DQSn glitch suppression resistor PHY1			
+DATA 4 	DDR_PHY_DX8SLbDQSCTL_1	0x01264000	
+			
+// DQS2DQ training, Write leveling, Deskew and eye trainings			
+DATA 4	DDR_PHY_PIR_0	0x0010F800	
+DATA 4	DDR_PHY_PIR_0	0x0010F801	
+DATA 4	DDR_PHY_PIR_1	0x0010F800	
+DATA 4	DDR_PHY_PIR_1	0x0010F801	
+// Wait for training to complete			
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_0 	0x1	
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_0 	0x7FF40000	
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_1 	0x1	
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_1 	0x7FF40000	
+			
+// Launch VREF training			
+DATA 4	DDR_PHY_PIR_0	0x00020000	
+DATA 4	DDR_PHY_PIR_0	0x00020001	
+DATA 4	DDR_PHY_PIR_1	0x00020000	
+DATA 4	DDR_PHY_PIR_1	0x00020001	
+// Wait for training to complete			
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_0	0x1	
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_0	0x00080000	
+CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1	
+CHECK_BITS_CLR 4	DDR_PHY_PGSR0_1	0x00080000	
+			
+//Re-allow uMCTL2 to send commands to DDR			
+CLR_BIT 4	DDR_PHY_PGCR1_0	0x00020040	// DISDIC=0, PUBMODE=0
+CLR_BIT 4	DDR_PHY_PGCR1_1	0x00020040	// DISDIC=0, PUBMODE=0
+// DISDIC=0, PUBMODE=0
+			
+//DQS Drift Registers PHY0			
+CLR_BIT 4	DDR_PHY_DX0GCR3_0	0x08000000	
+CLR_BIT 4	DDR_PHY_DX1GCR3_0	0x08000000	
+CLR_BIT 4	DDR_PHY_DX2GCR3_0	0x08000000	
+CLR_BIT 4	DDR_PHY_DX3GCR3_0	0x08000000	
+// Enable DQS drift detection PHY0			
+DATA 4 	DDR_PHY_DQSDR0_0	0x20188005	
+DATA 4 	DDR_PHY_DQSDR1_0	0xA8AA0000	
+DATA 4 	DDR_PHY_DQSDR2_0	0x00070200	
+//DQS Drift Registers PHY1			
+CLR_BIT 4	DDR_PHY_DX0GCR3_1	0x08000000	
+CLR_BIT 4	DDR_PHY_DX1GCR3_1	0x08000000	
+CLR_BIT 4	DDR_PHY_DX2GCR3_1	0x08000000	
+CLR_BIT 4	DDR_PHY_DX3GCR3_1	0x08000000	
+// Enable DQS drift detection PHY1			
+DATA 4 	DDR_PHY_DQSDR0_1	0x20188005	
+DATA 4 	DDR_PHY_DQSDR1_1	0xA8AA0000	
+DATA 4 	DDR_PHY_DQSDR2_1	0x00070200	
+			
+// Enable VT compensation			
+CLR_BIT 4	DDR_PHY_PGCR6_0	0x1 	
+CLR_BIT 4	DDR_PHY_PGCR6_1	0x1 	
+			
+//Check that controller is ready to operate			
+CHECK_BITS_SET 4	DDRC_STAT_0	0x1	
+CHECK_BITS_SET 4	DDRC_STAT_1	0x1	
+
+// Disable drift, not needed for 800MHz
+CLR_BIT 4 DDR_PHY_DQSDR0_0 0x1
+CLR_BIT 4 DDR_PHY_DQSDR0_1	0x1
+#endif
-- 
2.13.6