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authorMichal Simek <michal.simek@xilinx.com>2018-12-20 08:40:25 +0100
committerMichal Simek <michal.simek@xilinx.com>2019-01-24 10:03:44 +0100
commitd9eaae3bae99cf79fd1453f4980b2624a6be9501 (patch)
tree61222f1f448eaceea1e21ee39dddd42f93b2482a /.travis.yml
parent5d93e886f85810cb758f685361e0755779488663 (diff)
travis: Wire Xilinx Versal Virt platform
Test Xilinx Versal Virt platform running on the v3.1.0 Qemu. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to '.travis.yml')
-rw-r--r--.travis.yml7
1 files changed, 7 insertions, 0 deletions
diff --git a/.travis.yml b/.travis.yml
index 59e615abb2..49a7fa94f3 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -463,6 +463,13 @@ matrix:
QEMU_TARGET="arm-softmmu"
TEST_PY_ID="--id qemu"
BUILDMAN="^zynq_zc702$"
+ - name: "test/py xilinx_versal_virt"
+ env:
+ - TEST_PY_BD="xilinx_versal_virt"
+ TEST_PY_TEST_SPEC="not sleep"
+ QEMU_TARGET="aarch64-softmmu"
+ TEST_PY_ID="--id qemu"
+ BUILDMAN="^xilinx_versal_virt$"
- name: "test/py xtfpga"
env:
- TEST_PY_BD="xtfpga"