diff options
author | Scott Sweeny <scott.sweeny@timesys.com> | 2009-05-01 17:07:42 -0400 |
---|---|---|
committer | Scott Sweeny <scott.sweeny@timesys.com> | 2009-05-01 17:07:42 -0400 |
commit | 56829283f4cd2bde16116a474cac1156c9761477 (patch) | |
tree | bb98e507a815dbe6aee44ad9cc398acfd500f681 | |
parent | 3dc50005c0cbd385a3c6e4896f4080e310e6bca4 (diff) |
Add support for syncing NOR flash
This patch originally from LogicPD OMAP35x Release 1.5.0
Original Patch Name: u-boot-1.1.4-omap3430-lv-som-28-lolo-nor-sync.patch
-rw-r--r-- | board/omap3430lv_som/mem.c | 129 | ||||
-rw-r--r-- | board/omap3430lv_som/omap3430lv_som.c | 6 | ||||
-rw-r--r-- | include/asm-arm/arch-omap3/mem.h | 22 | ||||
-rw-r--r-- | include/asm-arm/arch-omap3/sys_info.h | 2 | ||||
-rw-r--r-- | include/configs/omap3530lv_som.h | 1 | ||||
-rw-r--r-- | lib_arm/board.c | 7 |
6 files changed, 149 insertions, 18 deletions
diff --git a/board/omap3430lv_som/mem.c b/board/omap3430lv_som/mem.c index 1a9d03c91e..c8bb98c9d2 100644 --- a/board/omap3430lv_som/mem.c +++ b/board/omap3430lv_som/mem.c @@ -88,23 +88,34 @@ u8 is_nand = 0; #endif static u32 gpmc_enet[GPMC_MAX_REG] = { - LAB_ENET_GPMC_CONFIG1, - LAB_ENET_GPMC_CONFIG2, - LAB_ENET_GPMC_CONFIG3, - LAB_ENET_GPMC_CONFIG4, - LAB_ENET_GPMC_CONFIG5, - LAB_ENET_GPMC_CONFIG6, 0 + OMAP3530LV_SOM_ENET_GPMC_CONFIG1, + OMAP3530LV_SOM_ENET_GPMC_CONFIG2, + OMAP3530LV_SOM_ENET_GPMC_CONFIG3, + OMAP3530LV_SOM_ENET_GPMC_CONFIG4, + OMAP3530LV_SOM_ENET_GPMC_CONFIG5, + OMAP3530LV_SOM_ENET_GPMC_CONFIG6, 0 }; -static u32 gpmc_stnor[GPMC_MAX_REG] = { - STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, - STNOR_GPMC_CONFIG3, - STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, - STNOR_GPMC_CONFIG6, 0 +#ifdef CFG_FIX_FLASH_SYNC +static u32 gpmc_stnor_async[GPMC_MAX_REG] = { + OMAP3530LV_SOM_STNOR_ASYNC_CONFIG1, + OMAP3530LV_SOM_STNOR_ASYNC_CONFIG2, + OMAP3530LV_SOM_STNOR_ASYNC_CONFIG3, + OMAP3530LV_SOM_STNOR_ASYNC_CONFIG4, + OMAP3530LV_SOM_STNOR_ASYNC_CONFIG5, + OMAP3530LV_SOM_STNOR_ASYNC_CONFIG6, 0 }; +static u32 gpmc_stnor_sync[GPMC_MAX_REG] = { + OMAP3530LV_SOM_STNOR_SYNC_CONFIG1, + OMAP3530LV_SOM_STNOR_SYNC_CONFIG2, + OMAP3530LV_SOM_STNOR_SYNC_CONFIG3, + OMAP3530LV_SOM_STNOR_SYNC_CONFIG4, + OMAP3530LV_SOM_STNOR_SYNC_CONFIG5, + OMAP3530LV_SOM_STNOR_SYNC_CONFIG6, 0 +}; +#endif + static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, M_NAND_GPMC_CONFIG2, @@ -114,7 +125,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG6, 0 }; -#if 1 // Compact Flash setup static u32 gpmc_m_cf[GPMC_MAX_REG] = { M_CF_GPMC_CONFIG1, @@ -124,7 +134,24 @@ static u32 gpmc_m_cf[GPMC_MAX_REG] = { M_CF_GPMC_CONFIG5, M_CF_GPMC_CONFIG6, 0 }; -#endif + +/* These are bit definitions for the RCR register of the NOR flash */ +/* 28FxxxP30 device. This register sets the bus configration for reads. */ +/* settings, located on address pins A[15:0]. */ +#define FLASH_28FxxxP30_RCR_RM 0x8000 +#define FLASH_28FxxxP30_RCR_R 0x4000 +#define FLASH_28FxxxP30_RCR_LC(x) ((x & 0x7) << 11) +#define FLASH_28FxxxP30_RCR_WP 0x0400 +#define FLASH_28FxxxP30_RCR_DH 0x0200 +#define FLASH_28FxxxP30_RCR_WD 0x0100 +#define FLASH_28FxxxP30_RCR_BS 0x0080 +#define FLASH_28FxxxP30_RCR_CE 0x0040 +#define FLASH_28FxxxP30_RCR_BW 0x0008 +#define FLASH_28FxxxP30_RCR_BL(x) ((x & 0x7) << 0) +#define FLASH_28FxxxP30_BL_4 0x1 +#define FLASH_28FxxxP30_BL_8 0x2 +#define FLASH_28FxxxP30_BL_16 0x3 +#define FLASH_28FxxxP30_BL_CONT 0x7 /********** Functions ****/ @@ -340,6 +367,19 @@ void enable_gpmc_config(u32 * gpmc_config, u32 gpmc_base, u32 base, u32 size) sdelay(2000); } +void gpmc_dump_config(int cs) +{ + u32 gpmc_base = GPMC_CONFIG_CS0 + (cs * GPMC_CONFIG_WIDTH); + + printf("CS %d: [%08x] %08x %08x %08x %08x %08x %08x %08x\n", + cs, __raw_readl(GPMC_CONFIG), + __raw_readl(GPMC_CONFIG1 + gpmc_base), __raw_readl(GPMC_CONFIG2 + gpmc_base), + __raw_readl(GPMC_CONFIG3 + gpmc_base), __raw_readl(GPMC_CONFIG4 + gpmc_base), + __raw_readl(GPMC_CONFIG5 + gpmc_base), __raw_readl(GPMC_CONFIG6 + gpmc_base), + __raw_readl(GPMC_CONFIG7 + gpmc_base)); + +} + /***************************************************** * gpmc_init(): init gpmc bus * Init GPMC for x16, MuxMode (SDRAM in x32). @@ -356,6 +396,7 @@ void gpmc_init(void) u32 f_off = CFG_MONITOR_LEN; u32 f_sec = 0; u32 config = 0; + u16 rcrval; unsigned char *config_sel = NULL; u32 i=0; @@ -368,7 +409,12 @@ void gpmc_init(void) __raw_writel(0, GPMC_TIMEOUT_CONTROL); /* timeout disable */ config = __raw_readl(GPMC_CONFIG); +#if 1 + config &= (~0xd00); // clear wait lines for all but WAIT1 as + // used by NOR flash +#else config &= (~0xf00); +#endif __raw_writel(config, GPMC_CONFIG); /* Disable the GPMC0 config set by ROM code @@ -434,3 +480,56 @@ void gpmc_init(void) #endif } + +void fix_flash_sync() +{ +#ifdef CFG_FIX_FLASH_SYNC + u32 *gpmc_config = NULL; + u32 gpmc_base; + u32 config; + u16 rcrval; + + /* CS 2 - Check if NOR is in sync, and if not, then put flash into + sync mode, and GPMC into sync */ + gpmc_dump_config(2); + gpmc_base = GPMC_CONFIG_CS0 + (2 * GPMC_CONFIG_WIDTH); + config = __raw_readl(GPMC_CONFIG1 + gpmc_base); + if (!(config & TYPE_READTYPE)) { + // Its in async mode, we have to put it into sync. + + puts ("FLASH: initialize in sync mode\n"); + + // clear WAIT1 polarity + __raw_writel(__raw_readl(GPMC_CONFIG) & ~0x200, GPMC_CONFIG); + + // clear GPMC_TIMEOUT + __raw_writel(0x0, GPMC_TIMEOUT_CONTROL); + + // First set the GPMC for async. + gpmc_config = gpmc_stnor_async; + enable_gpmc_config(gpmc_config, gpmc_base, FLASH_BASE, GPMC_SIZE_64M); + // Second, tell flash to go into sync mode. + + gpmc_dump_config(2); + + // 1st NOR cycle, send read config register setup 0x60 + *(volatile u16 *)FLASH_BASE = 0x0060; + + // 2nd NOR cycle, send 0x03 to latch in read + // configuration register setttings, located on A[15:0] + rcrval = FLASH_28FxxxP30_RCR_LC(4) | FLASH_28FxxxP30_RCR_WP | + FLASH_28FxxxP30_RCR_BS | FLASH_28FxxxP30_RCR_CE | + FLASH_28FxxxP30_RCR_BW | FLASH_28FxxxP30_RCR_BL(FLASH_28FxxxP30_BL_4); + *(volatile u16 *)(FLASH_BASE | (rcrval << 1)) = 0x0003; + + // Third, set GPMC for sync. + gpmc_config = gpmc_stnor_sync; + enable_gpmc_config(gpmc_config, gpmc_base, FLASH_BASE, GPMC_SIZE_64M); + // And lastly, set the WAIT1 polarity high + __raw_writel(__raw_readl(GPMC_CONFIG) | 0x200, GPMC_CONFIG); + + gpmc_dump_config(2); + + } +#endif +} diff --git a/board/omap3430lv_som/omap3430lv_som.c b/board/omap3430lv_som/omap3430lv_som.c index 06c6955e8e..654a5a75d9 100644 --- a/board/omap3430lv_som/omap3430lv_som.c +++ b/board/omap3430lv_som/omap3430lv_som.c @@ -508,9 +508,9 @@ void set_muxconf_regs(void) MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/ MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/ MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)); /*GPMC_nBE0_CLE*/ - MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)); /*GPMC_nBE1 lab*/ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/ + MUX_VAL(CP(GPMC_nBE0_CLE), (IEN | PTU | EN | M0)); /*GPMC_nBE0_CLE*/ + MUX_VAL(CP(GPMC_nBE1), (IDIS | PTU | EN | M0)); /*GPMC_nBE1 lab*/ + MUX_VAL(CP(GPMC_nWP), (IEN | PTU | EN | M0)); /*GPMC_nWP*/ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)); /*gpmc_nWait lab*/ diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h index cfd093ae11..3e11627469 100644 --- a/include/asm-arm/arch-omap3/mem.h +++ b/include/asm-arm/arch-omap3/mem.h @@ -303,6 +303,21 @@ typedef enum { # define STNOR_GPMC_CONFIG5 0x01131F1F # define STNOR_GPMC_CONFIG6 0x1F0F04c4 +# define OMAP3530LV_SOM_STNOR_ASYNC_CONFIG1 0x00491211 +# define OMAP3530LV_SOM_STNOR_ASYNC_CONFIG2 0x00080901 +# define OMAP3530LV_SOM_STNOR_ASYNC_CONFIG3 0x00020201 +# define OMAP3530LV_SOM_STNOR_ASYNC_CONFIG4 0x08010901 +# define OMAP3530LV_SOM_STNOR_ASYNC_CONFIG5 0x0008090a +# define OMAP3530LV_SOM_STNOR_ASYNC_CONFIG6 0x08030200 + +# define OMAP3530LV_SOM_STNOR_SYNC_CONFIG1 0x60411213 +# define OMAP3530LV_SOM_STNOR_SYNC_CONFIG2 0x000A1301 +# define OMAP3530LV_SOM_STNOR_SYNC_CONFIG3 0x00020201 +# define OMAP3530LV_SOM_STNOR_SYNC_CONFIG4 0x07021302 +# define OMAP3530LV_SOM_STNOR_SYNC_CONFIG5 0x020c0813 +# define OMAP3530LV_SOM_STNOR_SYNC_CONFIG6 0x070303c3 + + # define SIBNOR_GPMC_CONFIG1 0x1200 # define SIBNOR_GPMC_CONFIG2 0x001f1f00 # define SIBNOR_GPMC_CONFIG3 0x00080802 @@ -333,6 +348,13 @@ typedef enum { # define LAB_ENET_GPMC_CONFIG5 0x041D1F1F # define LAB_ENET_GPMC_CONFIG6 0x1D0904C4 +# define OMAP3530LV_SOM_ENET_GPMC_CONFIG1 0x00001000 +# define OMAP3530LV_SOM_ENET_GPMC_CONFIG2 0x00080802 +# define OMAP3530LV_SOM_ENET_GPMC_CONFIG3 0x00000000 +# define OMAP3530LV_SOM_ENET_GPMC_CONFIG4 0x08020802 +# define OMAP3530LV_SOM_ENET_GPMC_CONFIG5 0x00080a0a +# define OMAP3530LV_SOM_ENET_GPMC_CONFIG6 0x00000000 + // ComactFlash timing on CS3 # define M_CF_GPMC_CONFIG1 0x00001210 # define M_CF_GPMC_CONFIG2 0x00131000 diff --git a/include/asm-arm/arch-omap3/sys_info.h b/include/asm-arm/arch-omap3/sys_info.h index 18e2b491c7..dc2cb54e7c 100644 --- a/include/asm-arm/arch-omap3/sys_info.h +++ b/include/asm-arm/arch-omap3/sys_info.h @@ -59,6 +59,8 @@ #define TYPE_NOR 0x000 #define TYPE_ONENAND 0x800 +#define TYPE_READTYPE 0x20000000 // Readtype, 1==sync + #define WIDTH_8BIT 0x0000 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ diff --git a/include/configs/omap3530lv_som.h b/include/configs/omap3530lv_som.h index d5974737b7..7331410a99 100644 --- a/include/configs/omap3530lv_som.h +++ b/include/configs/omap3530lv_som.h @@ -328,6 +328,7 @@ /*----------------------------------------------------------------------- * CFI FLASH driver setup */ +#define CFG_FIX_FLASH_SYNC // Fix the NOR flash/GPMC so its in 'sync' mode #ifndef CONFIG_OPTIONAL_NOR_POPULATED #define CFG_NO_FLASH 1 /* Disable NOR Flash support */ #else diff --git a/lib_arm/board.c b/lib_arm/board.c index 69f231c476..7d2cab61d5 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -318,6 +318,13 @@ void start_armboot (void) /* armboot_start is defined in the board-specific linker script */ mem_malloc_init (_armboot_start - CFG_MALLOC_LEN); +#ifdef CFG_FIX_FLASH_SYNC + { + extern void fix_flash_sync(); + fix_flash_sync(); + } +#endif + #if (CONFIG_COMMANDS & CFG_CMD_NAND) #ifdef ENV_IS_VARIABLE if (is_nand) |