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authorAnthony Felice <tony.felice@timesys.com>2013-07-11 16:04:25 -0400
committerAnthony Felice <tony.felice@timesys.com>2013-07-11 16:04:25 -0400
commitfb0fcc84aa1682269a51fb472f853c31a248b7b0 (patch)
tree6378417ca8155c410fe9cddebae0c29afd2e7e3f
parent31378b8a6d6b98b7b7aef8cd1b46e59142e7f644 (diff)
Revert "Update the reset cause code for Vybrid"2011.12-mvf-201307111604
This reverts commit d684ca3779cb69dfbd40fc9c7287b52e6216d616. This commit breaks NAND boot.
-rw-r--r--arch/arm/cpu/armv7/vybrid-common/cpu.c80
1 files changed, 38 insertions, 42 deletions
diff --git a/arch/arm/cpu/armv7/vybrid-common/cpu.c b/arch/arm/cpu/armv7/vybrid-common/cpu.c
index ce223f5dd1..865c01fc58 100644
--- a/arch/arm/cpu/armv7/vybrid-common/cpu.c
+++ b/arch/arm/cpu/armv7/vybrid-common/cpu.c
@@ -37,38 +37,38 @@
static char *get_reset_cause(void)
{
- char resetcause[32][64] = {{"POR"},
- {"Cortex A5 WDOG Timer Reset"},
- {0},
- {"CA5 WDOG reset"},
- {"CM4 WDOG reset"},
- {"JTAG HIGH-Z"},
- {0},
- {"External Reset"},
- {"1.2V supply below 0.7V"},
- {"HP regulator's LVD"},
- {"ULP regulator's LVD"},
- {"3.3V main supply is unstable"},
- {"LP regulator's LVD"},
- {0},
- {0},
- {0},
- {"MDM-AP system reset request is set"},
- {"Hard Fail State of System Security Monitor"},
- {"SRC_SCR SW Reset is set"},
- {"Platform's CSU alarm event"},
- {0},
- {0},
- {0},
- {0},
- {"Anadig regulator 1.1V unstable"},
- {"Anadig regulator 2.5V unstable"},
- {"Anadig regulator 3.0V unstable"},
- {"CMU even when FOSC freq less than 40MHz"},
- {"CMU event when BUS freq is out of range"},
- {"No clock is detected on FOSC"},
- {"No clock is detected on SOSC"},
- {"CM4 is in lockup"}};
+ char resetcause[32][64] = {"POR",
+ "Cortex A5 WDOG Timer Reset",
+ 0,
+ "CA5 WDOG reset",
+ "CM4 WDOG reset",
+ "JTAG HIGH-Z",
+ 0,
+ "External Reset",
+ "1.2V supply below 0.7V",
+ "HP regulator's LVD",
+ "ULP regulator's LVD",
+ "3.3V main supply is unstable",
+ "LP regulator's LVD",
+ 0,
+ 0,
+ 0,
+ "MDM-AP system reset request is set",
+ "Hard Fail State of System Security Monitor",
+ "SRC_SCR SW Reset is set",
+ "Platform's CSU alarm event",
+ 0,
+ 0,
+ 0,
+ 0,
+ "Anadig regulator 1.1V unstable",
+ "Anadig regulator 2.5V unstable",
+ "Anadig regulator 3.0V unstable",
+ "CMU even when FOSC freq less than 40MHz",
+ "CMU event when BUS freq is out of range",
+ "No clock is detected on FOSC",
+ "No clock is detected on SOSC",
+ "CM4 is in lockup"};
char buf[512] = {0}, *pbuf;
u32 cause;
int i, bit;
@@ -83,10 +83,7 @@ static char *get_reset_cause(void)
bit = 1 << i;
if ((cause & bit) == bit) {
if (resetcause[i][0] != NULL)
- {
- sprintf(pbuf, "%s, ", resetcause[i]);
- break;
- }
+ pbuf += sprintf(pbuf, "%s, ", resetcause[i]);
}
}
@@ -100,16 +97,15 @@ static char *get_reset_cause(void)
int print_cpuinfo(void)
{
u32 cpurev;
- char *tmp;
cpurev = get_cpu_rev();
- printf("CPU: Freescale VyBrid %x family rev%d.%d at 396 MHz\n",
+ printf("CPU: Freescale VyBrid %x family rev%d.%d at %d MHz\n",
(cpurev & 0xFFF000) >> 12,
(cpurev & 0x000F0) >> 4,
- (cpurev & 0x0000F) >> 0);
- tmp = get_reset_cause();
- if (tmp != NULL)
- printf("Reset cause: %s\n", tmp);
+ (cpurev & 0x0000F) >> 0,
+ vybrid_get_clock(VYBRID_ARM_CLK) / 1000000);
+ if (get_reset_cause() != NULL)
+ printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif