diff options
| author | Jason Jin <Jason.jin@freescale.com> | 2012-12-20 16:25:03 +0800 |
|---|---|---|
| committer | Anthony Felice <tony.felice@timesys.com> | 2013-06-21 13:46:53 -0400 |
| commit | aa6377c80b0aa3b58719ae82035e62cb48789b4d (patch) | |
| tree | 5fdf311a8ab1a1c37d3e1c58bf61c50df2cf567b | |
| parent | d684ca3779cb69dfbd40fc9c7287b52e6216d616 (diff) | |
provide a workaround for GPU in Vybrid
The GPU frequently hang the system during testing. This
patch provide a workaroud to reset the soc after the pll
system was initialized.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <b35083@freescale.com>
| -rw-r--r-- | arch/arm/cpu/armv7/vybrid/lowlevel_init.S | 21 | ||||
| -rw-r--r-- | include/configs/vybrid.h | 4 |
2 files changed, 22 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S index 8c22e3c365..53e6f8884f 100644 --- a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S +++ b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S @@ -123,11 +123,17 @@ ldr r2, =ANATOP_BASE_ADDR ldr r1, =CONFIG_SYS_ANADIG_528_CTRL str r1, [r2, #0x30] + + /* check for lock */ +check: ldr r3, [r2, #0x30] + bic r3, r3, #0x7fffffff + cmp r3, #0x80000000 + bne check + ldr r1, =CONFIG_SYS_ANADIG_ENET_CTRL str r1, [r2, #0xE0] ldr r1, =CONFIG_SYS_ANADIG_SYS_CTRL str r1, [r2, #0x270] - /* check for lock */ ldr r1, =CONFIG_SYS_CLKCTRL_CCR str r1, [r0, #CLKCTL_CCR] @@ -155,6 +161,19 @@ ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR4 str r1, [r0, #CLKCTL_CSCDR4] + + ldr r2, =SRC_BASE_ADDR + ldr r3, [r2, #0x08] + cmp r3, #0x40000 + beq out + str r3, [r2, #0x08] + ldr r1, [r2] + orr r1, r1, #0x1000 + str r1, [r2] + b out2 +out: + str r3, [r2, #0x08] +out2: .endm .macro setup_wdog diff --git a/include/configs/vybrid.h b/include/configs/vybrid.h index 23297da553..f88caec0dd 100644 --- a/include/configs/vybrid.h +++ b/include/configs/vybrid.h @@ -234,12 +234,12 @@ #define CONFIG_SYS_CLKCTL_CCGR10 0xFFFFFFFF #define CONFIG_SYS_CLKCTL_CCGR11 0xFFFFFFFF -#define CONFIG_SYS_CLKCTRL_CCR 0x00010005 +#define CONFIG_SYS_CLKCTRL_CCR 0x00011005 #define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF24 #define CONFIG_SYS_CLKCTRL_CACRR 0x00000810 #define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000 #define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000 -#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240 +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114640 #define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F #define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000 #define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000 |