diff options
| author | Stefan Roese <sr@denx.de> | 2008-03-01 12:11:40 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-03-02 22:49:27 +0100 |
| commit | 76957cb3d621bf664311908e5962e151c633c285 (patch) | |
| tree | 4dc953f94b42ef062d2a143c048225af371e5158 | |
| parent | 118978c8eb43803e2794233922df4249fa278b83 (diff) | |
ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1
The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But
currently 4k/2k is configured. This patch fixes this issue.
Thanks to Thomas Kindler <tkindler@lenord.de> for pointing this out.
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | cpu/ppc4xx/4xx_enet.c | 5 | ||||
| -rw-r--r-- | include/ppc4xx_enet.h | 27 |
2 files changed, 24 insertions, 8 deletions
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 5ef1005b1f..599f5ceb56 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -975,9 +975,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set transmit enable & receive enable */ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); - /* set receive fifo to 4k and tx fifo to 2k */ mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); - mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; + + /* set rx-/tx-fifo size */ + mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; /* set speed */ if (speed == _1000BASET) { diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index f285500739..317604ae0a 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -356,12 +356,14 @@ typedef struct emac_4xx_hw_st { #define EMAC_M1_IST (0x01000000) #define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ #define EMAC_M1_MF_100MBPS (0x00400000) -#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_MASK (0x00380000) +#define EMAC_M1_RFS_16K (0x00280000) +#define EMAC_M1_RFS_8K (0x00200000) +#define EMAC_M1_RFS_4K (0x00180000) #define EMAC_M1_RFS_2K (0x00100000) #define EMAC_M1_RFS_1K (0x00080000) -#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_MASK (0x00070000) +#define EMAC_M1_TX_FIFO_16K (0x00050000) #define EMAC_M1_TX_FIFO_8K (0x00040000) #define EMAC_M1_TX_FIFO_4K (0x00030000) #define EMAC_M1_TX_FIFO_2K (0x00020000) @@ -386,11 +388,15 @@ typedef struct emac_4xx_hw_st { #define EMAC_M1_IST 0x01000000 #define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ #define EMAC_M1_MF_100MBPS 0x00400000 -#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ +#define EMAC_M1_RFS_MASK 0x00300000 +#define EMAC_M1_RFS_4K 0x00300000 #define EMAC_M1_RFS_2K 0x00200000 #define EMAC_M1_RFS_1K 0x00100000 -#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ +#define EMAC_M1_RFS_512 0x00000000 +#define EMAC_M1_TX_FIFO_MASK 0x000c0000 +#define EMAC_M1_TX_FIFO_2K 0x00080000 #define EMAC_M1_TX_FIFO_1K 0x00040000 +#define EMAC_M1_TX_FIFO_512 0x00000000 #define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ #define EMAC_M1_TR0_MULTI 0x00008000 #define EMAC_M1_TR1_DEPEND 0x00004000 @@ -400,6 +406,15 @@ typedef struct emac_4xx_hw_st { #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ #endif /* defined(CONFIG_440GX) */ +#define EMAC_MR1_FIFO_MASK (EMAC_M1_RFS_MASK | EMAC_M1_TX_FIFO_MASK) +#if defined(CONFIG_405EZ) +/* 405EZ only supports 512 bytes fifos */ +#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_512 | EMAC_M1_TX_FIFO_512) +#else +/* Set receive fifo to 4k and tx fifo to 2k */ +#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K) +#endif + /* Transmit Mode Register 0 */ #define EMAC_TXM0_GNP0 (0x80000000) #define EMAC_TXM0_GNP1 (0x40000000) |