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authorDave Liu <daveliu@freescale.com>2010-04-29 17:16:25 +0800
committerScott Sweeny <scott.sweeny@timesys.com>2010-09-30 11:17:16 -0400
commita4f510740875b9ceed882d6413d475f4f6befe03 (patch)
tree67b7497c2a68c2655d715c5e5359f763105af24a
parent04cbb96db06c5a1fba1a80d00f322b25ab656ede (diff)
p1022ds: Fix the DIU issue on RevB1 board2009.11-p1022ds-201004291116
DIU doesn't work on P1022DS RevB1 board in u-boot, it is because there are two code bugs in DIU code. 1) We must clear the PMUXCR[eLBC_DIU] bits before we set the eLBC_DIU=2'b01 for DIU mode. The PMUXCR[eLBC_DIU] POR value is 2'b10 in RevB1 board, however the eLBC_DIU is 2'b00 in RevA board due to design issue. 2) We must do dummy read to make sure the write FPGA PIXIS register be completed. Signed-off-by: Dave Liu <daveliu@freescale.com>
-rw-r--r--board/freescale/p1022ds/p1022ds_diu.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/board/freescale/p1022ds/p1022ds_diu.c b/board/freescale/p1022ds/p1022ds_diu.c
index af0bcb77fe7..b2f210a7092 100644
--- a/board/freescale/p1022ds/p1022ds_diu.c
+++ b/board/freescale/p1022ds/p1022ds_diu.c
@@ -91,12 +91,13 @@ void p1022ds_diu_init(void)
tmp_val_brdcfg0 = in_8(pixis_base + PIXIS_BRDCFG0);
tmp_val_brdcfg0 = (tmp_val_brdcfg0 & 0x3D) | 0x02;
out_8(pixis_base + PIXIS_BRDCFG0, tmp_val_brdcfg0);
+ /* we must do the dummy read from eLBC to sync the write as above */
+ in_8(pixis_base + PIXIS_BRDCFG0);
/* Setting PMUXCR to switch to DVI from ELBC */
/* Set pmuxcr to allow both i2c1 and i2c2 */
- gur->pmuxcr |= 0x40000000;
- tmp = gur->pmuxcr;
-
+ clrsetbits_be32(&gur->pmuxcr, 0xc0000000, 0x40000000);
+ tmp = in_be32(&gur->pmuxcr);
fsl_diu_init(xres, pixel_format, gamma_fix,
(unsigned char *)FSL_Logo_BMP);
}