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authorStefan Agner <stefan.agner@toradex.com>2018-06-05 15:18:50 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2018-06-06 13:18:31 +0200
commit63d856627d8a9875e5299459dc0054c1ab9d2352 (patch)
tree873fcce2cbb6ce05cb4b1d2e02c15e861b116b67
parent743e081f34bcc19e7026f21445a40b819f2d72a3 (diff)
ARM: vf610: ddrmc: do not write CR79 by default
The current value CTLUPD_AREF(0) is the reset value of the register, so there is no need to write a value. If needed, the register can be written using board specific CR settings. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-rw-r--r--arch/arm/imx-common/ddrmc-vf610.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/imx-common/ddrmc-vf610.c b/arch/arm/imx-common/ddrmc-vf610.c
index 8582ad8c2a..2a1d373785 100644
--- a/arch/arm/imx-common/ddrmc-vf610.c
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -189,7 +189,6 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
- writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);