vybrid: Fix hardware clock drift2011.12-mvf-201212191113

We must enable the external 32kHz oscillator in order to work
around a known clock drift issue with the internal 32kHz oscillator.

This fixes the Linux kernel system clock drift.

Signed-off-by: Anthony Huereca <B04178@freescale.com>
Signed-off-by: Jiri Kotzian <B36968@freescale.com>
Signed-off-by: Justin Waters <justin.waters@timesys.com>

2 files changed, 70 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-vybrid/scsc_regs.h b/arch/arm/include/asm/arch-vybrid/scsc_regs.h
new file mode 100644
index 0000000000..db019835a0
--- /dev/null
+++ b/arch/arm/include/asm/arch-vybrid/scsc_regs.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2012 Timesys Corporation All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+
+#ifndef __ARCH_ARM_MACH_VYBRID_SCSC_REGS_H__
+#define __ARCH_ARM_MACH_VYBRID_SCSC_REGS_H__
+
+struct vybrid_scsc_reg {
+	u32 sicr_ctr;	/* 0x0000 */
+	u32 sosc_ctr;
+	u32 lfsr_ctr;
+};
+
+/* Define the bits in register sicr_ctr */
+#define VYBRID_SCSC_SICR_CTR_SIRC_DIV_MASK		(0x7F << 8)
+#define VYBRID_SCSC_SICR_CTR_SIRC_DIV_OFFSET		8
+#define VYBRID_SCSC_SICR_CTR_SIRC_SIRC_ON_FAIL		(1 << 4)
+#define VYBRID_SCSC_SICR_CTR_SIRC_SIRC_EN		(1 << 0)
+
+/* Define the bits in register sosc_ctr */
+#define VYBRID_SCSC_SICR_CTR_SOSC_BYPASS		(1 << 3)
+#define VYBRID_SCSC_SICR_CTR_SOSC_EN			(1 << 0)
+
+#define VYBRID_SCSC_LFSR_POLY_LFSR_MASK			(0xFFFF << 16)
+#define VYBRID_SCSC_LFSR_POLY_LFSR_OFFSET		16
+#define VYBRID_SCSC_LFSR_EN_TZASC_VIO			(1 << 14)
+#define VYBRID_SCSC_LFSR_LFSR1_SEED 			(1 << 13)
+#define VYBRID_SCSC_LFSR_LFSR0_SEED 			(1 << 12)
+#define VYBRID_SCSC_LFSR_ACTIVE_SEL_4_5			(1 << 11)
+#define VYBRID_SCSC_LFSR_ACTIVE_SEL_2_3			(1 << 10)
+#define VYBRID_SCSC_LFSR_TAMPER5_INV			(1 << 9)
+#define VYBRID_SCSC_LFSR_TAMPER4_INV			(1 << 8)
+#define VYBRID_SCSC_LFSR_TAMPER3_INV			(1 << 7)
+#define VYBRID_SCSC_LFSR_TAMPER2_INV			(1 << 6)
+#define VYBRID_SCSC_LFSR_TAMPER1_INV			(1 << 5)
+#define VYBRID_SCSC_LFSR_TAMPER0_INV			(1 << 4)
+
+#endif /*__ARCH_ARM_MACH_VYBRID_SCSC_REGS_H__ */
diff --git a/board/freescale/vybrid/vybrid.c b/board/freescale/vybrid/vybrid.c
index a1507e170b..c9b423888f 100644
--- a/board/freescale/vybrid/vybrid.c
+++ b/board/freescale/vybrid/vybrid.c
@@ -30,6 +30,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/scsc_regs.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -512,9 +513,23 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	u32 temp;
+	struct vybrid_scsc_reg *scsc = (struct vybrid_scsc_reg *)SCSCM_BASE_ADDR;
+
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+	/*
+	 * Enable external 32K Oscillator
+	 *
+	 * The internal clock experiences significant drift
+         * so we must use the external oscillator in order
+	 * to maintain correct time in the hwclock
+	 */
+	temp = __raw_readl(&scsc->sosc_ctr);
+	temp |= VYBRID_SCSC_SICR_CTR_SOSC_EN;
+	__raw_writel(temp, &scsc->sosc_ctr);
+
 	return 0;
 }