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authorJingchang Lu <b35083@freescale.com>2012-07-03 13:21:44 +0800
committerJustin Waters <justin.waters@timesys.com>2012-09-07 15:22:42 -0400
commit56c5b506f71dfe063807c6e837ce06c265a6df65 (patch)
treec7e4a6f3dead87c88b294ce82e147b2b09e64cd6
parent98f181be8e400434698fd89b13e04dbda9e8935d (diff)
Add eSDHC support for Vybrid platform
On some platform, such as vybrid, there is no scr register, but the dis-order excution may wrongly excute the register write. The barrier used to prevent this. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
-rw-r--r--drivers/mmc/fsl_esdhc.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index a2f35e3e99..e8b304ab2f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
+ * Copyright 2007, 2010-2012 Freescale Semiconductor, Inc
* Andy Fleming
*
* Based vaguely on the pxa mmc code:
@@ -428,8 +428,11 @@ static int esdhc_init(struct mmc *mmc)
udelay(1000);
/* Enable cache snooping */
- if (cfg && !cfg->no_snoop)
+
+ if (cfg && !cfg->no_snoop) {
+ asm volatile("" ::: "memory");
esdhc_write32(&regs->scr, 0x00000040);
+ }
esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
@@ -542,6 +545,9 @@ int fsl_esdhc_mmc_init(bd_t *bis)
cfg = malloc(sizeof(struct fsl_esdhc_cfg));
memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+#ifdef CONFIG_ESDHC_NO_SNOOP
+ cfg->no_snoop = 1;
+#endif
return fsl_esdhc_initialize(bis, cfg);
}